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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tegra210_amx.h - Definitions for Tegra210 AMX driver4 *5 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.6 *7 */8 9#ifndef __TEGRA210_AMX_H__10#define __TEGRA210_AMX_H__11 12/* Register offsets from TEGRA210_AMX*_BASE */13#define TEGRA210_AMX_RX_STATUS 0x0c14#define TEGRA210_AMX_RX_INT_STATUS 0x1015#define TEGRA210_AMX_RX_INT_MASK 0x1416#define TEGRA210_AMX_RX_INT_SET 0x1817#define TEGRA210_AMX_RX_INT_CLEAR 0x1c18#define TEGRA210_AMX_RX1_CIF_CTRL 0x2019#define TEGRA210_AMX_RX2_CIF_CTRL 0x2420#define TEGRA210_AMX_RX3_CIF_CTRL 0x2821#define TEGRA210_AMX_RX4_CIF_CTRL 0x2c22#define TEGRA210_AMX_TX_STATUS 0x4c23#define TEGRA210_AMX_TX_INT_STATUS 0x5024#define TEGRA210_AMX_TX_INT_MASK 0x5425#define TEGRA210_AMX_TX_INT_SET 0x5826#define TEGRA210_AMX_TX_INT_CLEAR 0x5c27#define TEGRA210_AMX_TX_CIF_CTRL 0x6028#define TEGRA210_AMX_ENABLE 0x8029#define TEGRA210_AMX_SOFT_RESET 0x8430#define TEGRA210_AMX_CG 0x8831#define TEGRA210_AMX_STATUS 0x8c32#define TEGRA210_AMX_INT_STATUS 0x9033#define TEGRA210_AMX_CTRL 0xa434#define TEGRA210_AMX_OUT_BYTE_EN0 0xa835#define TEGRA210_AMX_OUT_BYTE_EN1 0xac36#define TEGRA210_AMX_CYA 0xb037#define TEGRA210_AMX_CFG_RAM_CTRL 0xb838#define TEGRA210_AMX_CFG_RAM_DATA 0xbc39 40#define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc041#define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc42#define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc43 44/* Fields in TEGRA210_AMX_ENABLE */45#define TEGRA210_AMX_ENABLE_SHIFT 046 47/* Fields in TEGRA210_AMX_CTRL */48#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 1449#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT)50 51#define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 1252#define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT)53 54/* Fields in TEGRA210_AMX_CFG_RAM_CTRL */55#define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 1456#define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT)57 58#define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 1359#define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)60 61#define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 1262#define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)63 64#define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 065 66/* Fields in TEGRA210_AMX_SOFT_RESET */67#define TEGRA210_AMX_SOFT_RESET_SOFT_EN 168#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK TEGRA210_AMX_SOFT_RESET_SOFT_EN69 70#define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 471#define TEGRA210_AMX_RAM_DEPTH 1672#define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 673#define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 274#define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 075 76enum {77 TEGRA210_AMX_WAIT_ON_ALL,78 TEGRA210_AMX_WAIT_ON_ANY,79};80 81struct tegra210_amx_soc_data {82 const struct regmap_config *regmap_conf;83 bool auto_disable;84};85 86struct tegra210_amx {87 const struct tegra210_amx_soc_data *soc_data;88 unsigned int map[TEGRA210_AMX_RAM_DEPTH];89 struct regmap *regmap;90 unsigned int byte_mask[2];91};92 93#endif94