129 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tegra210_i2s.h - Definitions for Tegra210 I2S driver4 *5 * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.6 *7 */8 9#ifndef __TEGRA210_I2S_H__10#define __TEGRA210_I2S_H__11 12/* Register offsets from I2S*_BASE */13#define TEGRA210_I2S_RX_ENABLE 0x014#define TEGRA210_I2S_RX_SOFT_RESET 0x415#define TEGRA210_I2S_RX_STATUS 0x0c16#define TEGRA210_I2S_RX_INT_STATUS 0x1017#define TEGRA210_I2S_RX_INT_MASK 0x1418#define TEGRA210_I2S_RX_INT_SET 0x1819#define TEGRA210_I2S_RX_INT_CLEAR 0x1c20#define TEGRA210_I2S_RX_CIF_CTRL 0x2021#define TEGRA210_I2S_RX_CTRL 0x2422#define TEGRA210_I2S_RX_SLOT_CTRL 0x2823#define TEGRA210_I2S_RX_CLK_TRIM 0x2c24#define TEGRA210_I2S_RX_CYA 0x3025#define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x3426#define TEGRA210_I2S_TX_ENABLE 0x4027#define TEGRA210_I2S_TX_SOFT_RESET 0x4428#define TEGRA210_I2S_TX_STATUS 0x4c29#define TEGRA210_I2S_TX_INT_STATUS 0x5030#define TEGRA210_I2S_TX_INT_MASK 0x5431#define TEGRA210_I2S_TX_INT_SET 0x5832#define TEGRA210_I2S_TX_INT_CLEAR 0x5c33#define TEGRA210_I2S_TX_CIF_CTRL 0x6034#define TEGRA210_I2S_TX_CTRL 0x6435#define TEGRA210_I2S_TX_SLOT_CTRL 0x6836#define TEGRA210_I2S_TX_CLK_TRIM 0x6c37#define TEGRA210_I2S_TX_CYA 0x7038#define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x7439#define TEGRA210_I2S_ENABLE 0x8040#define TEGRA210_I2S_SOFT_RESET 0x8441#define TEGRA210_I2S_CG 0x8842#define TEGRA210_I2S_STATUS 0x8c43#define TEGRA210_I2S_INT_STATUS 0x9044#define TEGRA210_I2S_CTRL 0xa045#define TEGRA210_I2S_TIMING 0xa446#define TEGRA210_I2S_SLOT_CTRL 0xa847#define TEGRA210_I2S_CLK_TRIM 0xac48#define TEGRA210_I2S_CYA 0xb049 50/* Bit fields, shifts and masks */51#define I2S_DATA_SHIFT 852#define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)53 54#define I2S_EN_SHIFT 055#define I2S_EN_MASK BIT(I2S_EN_SHIFT)56#define I2S_EN BIT(I2S_EN_SHIFT)57 58#define I2S_FSYNC_WIDTH_SHIFT 2459#define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)60 61#define I2S_POS_EDGE 062#define I2S_NEG_EDGE 163#define I2S_EDGE_SHIFT 2064#define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)65#define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)66#define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)67 68#define I2S_FMT_LRCK 069#define I2S_FMT_FSYNC 170#define I2S_FMT_SHIFT 1271#define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)72#define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)73#define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)74 75#define I2S_CTRL_MASTER_EN_SHIFT 1076#define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)77#define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)78 79#define I2S_CTRL_LRCK_POL_SHIFT 980#define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)81#define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)82#define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)83 84#define I2S_CTRL_LPBK_SHIFT 885#define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)86#define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)87 88#define I2S_BITS_8 189#define I2S_BITS_16 390#define I2S_BITS_32 791#define I2S_CTRL_BIT_SIZE_MASK 0x792 93#define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff94#define I2S_TIMING_CH_BIT_CNT_SHIFT 095 96#define I2S_SOFT_RESET_SHIFT 097#define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)98#define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)99 100#define I2S_RX_FIFO_DEPTH 64101#define DEFAULT_I2S_RX_FIFO_THRESHOLD 3102 103#define DEFAULT_I2S_SLOT_MASK 0xffff104 105enum tegra210_i2s_path {106 I2S_RX_PATH,107 I2S_TX_PATH,108 I2S_PATHS,109};110 111struct tegra210_i2s {112 struct clk *clk_i2s;113 struct clk *clk_sync_input;114 struct regmap *regmap;115 int client_sample_format;116 unsigned int client_channels;117 unsigned int stereo_to_mono[I2S_PATHS];118 unsigned int mono_to_stereo[I2S_PATHS];119 unsigned int dai_fmt;120 unsigned int fsync_width;121 unsigned int bclk_ratio;122 unsigned int tx_mask;123 unsigned int rx_mask;124 unsigned int rx_fifo_th;125 bool loopback;126};127 128#endif129