brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2//3// tegra210_sfc.c - Tegra210 SFC driver4//5// Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.6 7#include <linux/clk.h>8#include <linux/device.h>9#include <linux/io.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/platform_device.h>13#include <linux/pm_runtime.h>14#include <linux/regmap.h>15#include <sound/core.h>16#include <sound/pcm.h>17#include <sound/pcm_params.h>18#include <sound/soc.h>19 20#include "tegra210_sfc.h"21#include "tegra_cif.h"22 23#define UNSUPP_CONV ((void *)(-EOPNOTSUPP))24#define BYPASS_CONV NULL25 26static const struct reg_default tegra210_sfc_reg_defaults[] = {27	{ TEGRA210_SFC_RX_INT_MASK, 0x00000001},28	{ TEGRA210_SFC_RX_CIF_CTRL, 0x00007700},29	{ TEGRA210_SFC_TX_INT_MASK, 0x00000001},30	{ TEGRA210_SFC_TX_CIF_CTRL, 0x00007700},31	{ TEGRA210_SFC_CG, 0x1},32	{ TEGRA210_SFC_CFG_RAM_CTRL, 0x00004000},33};34 35static const int tegra210_sfc_rates[TEGRA210_SFC_NUM_RATES] = {36	8000,37	11025,38	16000,39	22050,40	24000,41	32000,42	44100,43	48000,44	64000,45	88200,46	96000,47	176400,48	192000,49};50 51/* coeff RAM tables required for SFC */52static u32 coef_8to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {53	0x000c6102,//header54	0x0001d727,//input gain55	0x00fc2fc7, 0xff9bb27b, 0x001c564c,56	0x00e55557, 0xffcadd5b, 0x003d80ba,57	0x00d13397, 0xfff232f8, 0x00683337,58	0x00000002,//output gain59	0x0018a102,//header60	0x000005d6,//input gain61	0x00c6543e, 0xff342935, 0x0052f116,62	0x000a1d78, 0xff3330c0, 0x005f88a3,63	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,64	0x00000003,//output gain65	0x00235204,//farrow66	0x000aaaab,67	0xffaaaaab,68	0xfffaaaab,69	0x00555555,70	0xff600000,71	0xfff55555,72	0x00155555,73	0x00055555,74	0xffeaaaab,75	0x00200000,76	0x00005102,//header77	0x0000015f,//input gain78	0x00a7909c, 0xff241c71, 0x005f5e00,79	0xffca77f4, 0xff20dd50, 0x006855eb,80	0xff86c552, 0xff18137a, 0x00773648,81	0x00000001//output gain82};83 84static u32 coef_8to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {85	0x00006102,//header86	0x0001d727,//input gain87	0x00fc2fc7, 0xff9bb27b, 0x001c564c,88	0x00e55557, 0xffcadd5b, 0x003d80ba,89	0x00d13397, 0xfff232f8, 0x00683337,90	0x00000002//output gain91};92 93static u32 coef_8to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {94	0x000c6102,//header95	0x0001d727,//input gain96	0x00fc2fc7, 0xff9bb27b, 0x001c564c,97	0x00e55557, 0xffcadd5b, 0x003d80ba,98	0x00d13397, 0xfff232f8, 0x00683337,99	0x00000002,//output gain100	0x0018a102,//header101	0x000005d6,//input gain102	0x00c6543e, 0xff342935, 0x0052f116,103	0x000a1d78, 0xff3330c0, 0x005f88a3,104	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,105	0x00000003,//output gain106	0x00230204,//farrow107	0x000aaaab,108	0xffaaaaab,109	0xfffaaaab,110	0x00555555,111	0xff600000,112	0xfff55555,113	0x00155555,114	0x00055555,115	0xffeaaaab,116	0x00200000,117	0x00005102,//header118	0x000005f3,//input gain119	0x00d816d6, 0xff385383, 0x004fe566,120	0x003c548d, 0xff38c23d, 0x005d0b1c,121	0xfff02f7d, 0xff31e983, 0x0072d65d,122	0x00000001//output gain123};124 125static u32 coef_8to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {126	0x0000a105,//header127	0x000005e1,//input gain128	0x00dca92f, 0xff45647a, 0x0046b59c,129	0x00429d1e, 0xff4fec62, 0x00516d30,130	0xffdea779, 0xff5e08ba, 0x0060185e,131	0xffafbab2, 0xff698d5a, 0x006ce3ae,132	0xff9a82d2, 0xff704674, 0x007633c5,133	0xff923433, 0xff721128, 0x007cff42,134	0x00000003//output gain135};136 137static u32 coef_8to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {138	0x000c6102,//header139	0x0001d727,//input gain140	0x00fc2fc7, 0xff9bb27b, 0x001c564c,141	0x00e55557, 0xffcadd5b, 0x003d80ba,142	0x00d13397, 0xfff232f8, 0x00683337,143	0x00000002,//output gain144	0x00006102,//header145	0x000013d9,//input gain146	0x00ebd477, 0xff4ce383, 0x0042049d,147	0x0089c278, 0xff54414d, 0x00531ded,148	0x004a5e07, 0xff53cf41, 0x006efbdc,149	0x00000002//output gain150};151 152static u32 coef_8to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {153	0x0156105,//interpolation + IIR filter154	0x0000d649,//input gain155	0x00e87afb, 0xff5f69d0, 0x003df3cf,156	0x007ce488, 0xff99a5c8, 0x0056a6a0,157	0x00344928, 0xffcba3e5, 0x006be470,158	0x00137aa7, 0xffe60276, 0x00773410,159	0x0005fa2a, 0xfff1ac11, 0x007c795b,160	0x00012d36, 0xfff5eca2, 0x007f10ef,161	0x00000002,//ouptut gain162	0x0021a102,//interpolation + IIR filter163	0x00000e00,//input gain164	0x00e2e000, 0xff6e1a00, 0x002aaa00,165	0x00610a00, 0xff5dda00, 0x003ccc00,166	0x00163a00, 0xff3c0400, 0x00633200,167	0x00000003,//Output gain168	0x00000204,//Farrow filter169	0x000aaaab,170	0xffaaaaab,171	0xfffaaaab,172	0x00555555,173	0xff600000,174	0xfff55555,175	0x00155555,176	0x00055555,177	0xffeaaaab,178	0x00200000179};180 181static u32 coef_8to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {182	0x00156105,//interpolation + IIR Filter183	0x0000d649,//input gain184	0x00e87afb, 0xff5f69d0, 0x003df3cf,185	0x007ce488, 0xff99a5c8, 0x0056a6a0,186	0x00344928, 0xffcba3e5, 0x006be470,187	0x00137aa7, 0xffe60276, 0x00773410,188	0x0005fa2a, 0xfff1ac11, 0x007c795b,189	0x00012d36, 0xfff5eca2, 0x007f10ef,190	0x00000002,//ouptut gain191	0x0000a102,//interpolation + IIR filter192	0x00000e00,//input gain193	0x00e2e000, 0xff6e1a00, 0x002aaa00,194	0x00610a00, 0xff5dda00, 0x003ccc00,195	0x00163a00, 0xff3c0400, 0x00633200,196	0x00000003//output gain197};198 199static u32 coef_8to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {200	0x000c6102,//header201	0x0001d727,//input gain202	0x00fc2fc7, 0xff9bb27b, 0x001c564c,203	0x00e55557, 0xffcadd5b, 0x003d80ba,204	0x00d13397, 0xfff232f8, 0x00683337,205	0x00000002,//output gain206	0x00186102,//header207	0x000013d9,//input gain208	0x00ebd477, 0xff4ce383, 0x0042049d,209	0x0089c278, 0xff54414d, 0x00531ded,210	0x004a5e07, 0xff53cf41, 0x006efbdc,211	0x00000002,//output gain212	0x0024a102,//header213	0x0000007d,//input gain214	0x007d1f20, 0xff1a540e, 0x00678bf9,215	0xff916625, 0xff16b0ff, 0x006e433a,216	0xff5af660, 0xff0eb91f, 0x00797356,217	0x00000003,//output gain218	0x00000204,//farrow219	0x000aaaab,220	0xffaaaaab,221	0xfffaaaab,222	0x00555555,223	0xff600000,224	0xfff55555,225	0x00155555,226	0x00055555,227	0xffeaaaab,228	0x00200000229};230 231static u32 coef_8to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {232	0x000c6102,//header233	0x0001d727,//input gain234	0x00fc2fc7, 0xff9bb27b, 0x001c564c,235	0x00e55557, 0xffcadd5b, 0x003d80ba,236	0x00d13397, 0xfff232f8, 0x00683337,237	0x00000002,//output gain238	0x00186102,//header239	0x000013d9,//input gain240	0x00ebd477, 0xff4ce383, 0x0042049d,241	0x0089c278, 0xff54414d, 0x00531ded,242	0x004a5e07, 0xff53cf41, 0x006efbdc,243	0x00000002,//output gain244	0x0000a102,//header245	0x0000007d,//input gain246	0x007d1f20, 0xff1a540e, 0x00678bf9,247	0xff916625, 0xff16b0ff, 0x006e433a,248	0xff5af660, 0xff0eb91f, 0x00797356,249	0x00000003//output gain250};251 252static u32 coef_11to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {253	0x000c6102,//header254	0x0000015f,//input gain255	0x00a7909c, 0xff241c71, 0x005f5e00,256	0xffca77f4, 0xff20dd50, 0x006855eb,257	0xff86c552, 0xff18137a, 0x00773648,258	0x00000002,//output gain259	0x00186102,//header260	0x000005f3,//input gain261	0x00d816d6, 0xff385383, 0x004fe566,262	0x003c548d, 0xff38c23d, 0x005d0b1c,263	0xfff02f7d, 0xff31e983, 0x0072d65d,264	0x00000002,//output gain265	0x00239204,//farrow266	0x000aaaab,267	0xffaaaaab,268	0xfffaaaab,269	0x00555555,270	0xff600000,271	0xfff55555,272	0x00155555,273	0x00055555,274	0xffeaaaab,275	0x00200000,276	0x00005102,//header277	0x0001d727,//input gain278	0x00fc2fc7, 0xff9bb27b, 0x001c564c,279	0x00e55557, 0xffcadd5b, 0x003d80ba,280	0x00d13397, 0xfff232f8, 0x00683337,281	0x00000001//output gain282};283 284static u32 coef_11to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {285	0x000c6102,//header286	0x0001d727,//input gain287	0x00fc2fc7, 0xff9bb27b, 0x001c564c,288	0x00e55557, 0xffcadd5b, 0x003d80ba,289	0x00d13397, 0xfff232f8, 0x00683337,290	0x00000002,//output gain291	0x00186102,//header292	0x000013d9,//input gain293	0x00ebd477, 0xff4ce383, 0x0042049d,294	0x0089c278, 0xff54414d, 0x00531ded,295	0x004a5e07, 0xff53cf41, 0x006efbdc,296	0x00000002,//output gain297	0x00009204,//farrow298	0x000aaaab,299	0xffaaaaab,300	0xfffaaaab,301	0x00555555,302	0xff600000,303	0xfff55555,304	0x00155555,305	0x00055555,306	0xffeaaaab,307	0x00200000308};309 310static u32 coef_11to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {311	0x00006102,//header312	0x0001d727,//input gain313	0x00fc2fc7, 0xff9bb27b, 0x001c564c,314	0x00e55557, 0xffcadd5b, 0x003d80ba,315	0x00d13397, 0xfff232f8, 0x00683337,316	0x00000002//output gain317};318 319static u32 coef_11to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {320	0x000c6102,//header321	0x0001d727,//input gain322	0x00fc2fc7, 0xff9bb27b, 0x001c564c,323	0x00e55557, 0xffcadd5b, 0x003d80ba,324	0x00d13397, 0xfff232f8, 0x00683337,325	0x00000002,//output gain326	0x00186102,//header327	0x000013d9,//input gain328	0x00ebd477, 0xff4ce383, 0x0042049d,329	0x0089c278, 0xff54414d, 0x00531ded,330	0x004a5e07, 0xff53cf41, 0x006efbdc,331	0x00000002,//output gain332	0x00005204,//farrow333	0x000aaaab,334	0xffaaaaab,335	0xfffaaaab,336	0x00555555,337	0xff600000,338	0xfff55555,339	0x00155555,340	0x00055555,341	0xffeaaaab,342	0x00200000343};344 345static u32 coef_11to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {346	0x000c6102,//header347	0x0001d727,//input gain348	0x00fc2fc7, 0xff9bb27b, 0x001c564c,349	0x00e55557, 0xffcadd5b, 0x003d80ba,350	0x00d13397, 0xfff232f8, 0x00683337,351	0x00000002,//output gain352	0x00186102,//header353	0x000013d9,//input gain354	0x00ebd477, 0xff4ce383, 0x0042049d,355	0x0089c278, 0xff54414d, 0x00531ded,356	0x004a5e07, 0xff53cf41, 0x006efbdc,357	0x00000002,//output gain358	0x00246102,//header359	0x0000010a,//input gain360	0x00c93dc4, 0xff26f5f6, 0x005d1041,361	0x001002c4, 0xff245b76, 0x00666002,362	0xffc30a45, 0xff1baecd, 0x00765921,363	0x00000002,//output gain364	0x00009204,//farrow365	0x000aaaab,366	0xffaaaaab,367	0xfffaaaab,368	0x00555555,369	0xff600000,370	0xfff55555,371	0x00155555,372	0x00055555,373	0xffeaaaab,374	0x00200000375};376 377static u32 coef_11to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {378	0x000c6102,//header379	0x0001d727,//input gain380	0x00fc2fc7, 0xff9bb27b, 0x001c564c,381	0x00e55557, 0xffcadd5b, 0x003d80ba,382	0x00d13397, 0xfff232f8, 0x00683337,383	0x00000002,//output gain384	0x00006102,//header385	0x000013d9,//input gain386	0x00ebd477, 0xff4ce383, 0x0042049d,387	0x0089c278, 0xff54414d, 0x00531ded,388	0x004a5e07, 0xff53cf41, 0x006efbdc,389	0x00000002//output gain390};391 392static u32 coef_11to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {393	0x000c6102,//header394	0x0001d727,//input gain395	0x00fc2fc7, 0xff9bb27b, 0x001c564c,396	0x00e55557, 0xffcadd5b, 0x003d80ba,397	0x00d13397, 0xfff232f8, 0x00683337,398	0x00000002,//output gain399	0x00186102,//header400	0x000013d9,//input gain401	0x00ebd477, 0xff4ce383, 0x0042049d,402	0x0089c278, 0xff54414d, 0x00531ded,403	0x004a5e07, 0xff53cf41, 0x006efbdc,404	0x00000002,//output gain405	0x00246102,//header406	0x0000010a,//input gain407	0x00c93dc4, 0xff26f5f6, 0x005d1041,408	0x001002c4, 0xff245b76, 0x00666002,409	0xffc30a45, 0xff1baecd, 0x00765921,410	0x00000002,//output gain411	0x00005204,//farrow412	0x000aaaab,413	0xffaaaaab,414	0xfffaaaab,415	0x00555555,416	0xff600000,417	0xfff55555,418	0x00155555,419	0x00055555,420	0xffeaaaab,421	0x00200000422};423 424static u32 coef_11to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {425	0x000c6102,//header426	0x0001d727,//input gain427	0x00fc2fc7, 0xff9bb27b, 0x001c564c,428	0x00e55557, 0xffcadd5b, 0x003d80ba,429	0x00d13397, 0xfff232f8, 0x00683337,430	0x00000002,//output gain431	0x00186102,//header432	0x000013d9,//input gain433	0x00ebd477, 0xff4ce383, 0x0042049d,434	0x0089c278, 0xff54414d, 0x00531ded,435	0x004a5e07, 0xff53cf41, 0x006efbdc,436	0x00000002,//output gain437	0x00006102,//header438	0x0000010a,//input gain439	0x00c93dc4, 0xff26f5f6, 0x005d1041,440	0x001002c4, 0xff245b76, 0x00666002,441	0xffc30a45, 0xff1baecd, 0x00765921,442	0x00000002//output gain443};444 445static u32 coef_11to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {446	0x000c6102,//header447	0x0001d727,//input gain448	0x00fc2fc7, 0xff9bb27b, 0x001c564c,449	0x00e55557, 0xffcadd5b, 0x003d80ba,450	0x00d13397, 0xfff232f8, 0x00683337,451	0x00000002,//output gain452	0x00186102,//header453	0x000013d9,//input gain454	0x00ebd477, 0xff4ce383, 0x0042049d,455	0x0089c278, 0xff54414d, 0x00531ded,456	0x004a5e07, 0xff53cf41, 0x006efbdc,457	0x00000002,//output gain458	0x00246102,//header459	0x0000010a,//input gain460	0x00c93dc4, 0xff26f5f6, 0x005d1041,461	0x001002c4, 0xff245b76, 0x00666002,462	0xffc30a45, 0xff1baecd, 0x00765921,463	0x00000002,//output gain464	0x00000204,//farrow465	0x000aaaab,466	0xffaaaaab,467	0xfffaaaab,468	0x00555555,469	0xff600000,470	0xfff55555,471	0x00155555,472	0x00055555,473	0xffeaaaab,474	0x00200000475};476 477static u32 coef_16to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {478	0x00005102,//header479	0x0001d727,//input gain480	0x00fc2fc7, 0xff9bb27b, 0x001c564c,481	0x00e55557, 0xffcadd5b, 0x003d80ba,482	0x00d13397, 0xfff232f8, 0x00683337,483	0x00000001//output gain484};485 486static u32 coef_16to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {487	0x000fa103,//header488	0x000001e0,//input gain489	0x00de44c0, 0xff380b7f, 0x004ffc73,490	0x00494b44, 0xff3d493a, 0x005908bf,491	0xffe9a3c8, 0xff425647, 0x006745f7,492	0xffc42d61, 0xff40a6c7, 0x00776709,493	0x00000003,//output gain494	0x001a5204,//farrow495	0x000aaaab,496	0xffaaaaab,497	0xfffaaaab,498	0x00555555,499	0xff600000,500	0xfff55555,501	0x00155555,502	0x00055555,503	0xffeaaaab,504	0x00200000,505	0x00005102,//header506	0x0001d727,//input gain507	0x00fc2fc7, 0xff9bb27b, 0x001c564c,508	0x00e55557, 0xffcadd5b, 0x003d80ba,509	0x00d13397, 0xfff232f8, 0x00683337,510	0x00000001//output gain511};512 513static u32 coef_16to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {514	0x000c6102,//header515	0x0001d727,//input gain516	0x00fc2fc7, 0xff9bb27b, 0x001c564c,517	0x00e55557, 0xffcadd5b, 0x003d80ba,518	0x00d13397, 0xfff232f8, 0x00683337,519	0x00000002,//output gain520	0x0018a102,//header521	0x000005d6,//input gain522	0x00c6543e, 0xff342935, 0x0052f116,523	0x000a1d78, 0xff3330c0, 0x005f88a3,524	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,525	0x00000003,//output gain526	0x00235204,//farrow527	0x000aaaab,528	0xffaaaaab,529	0xfffaaaab,530	0x00555555,531	0xff600000,532	0xfff55555,533	0x00155555,534	0x00055555,535	0xffeaaaab,536	0x00200000,537	0x00005102,//header538	0x0000015f,//input gain539	0x00a7909c, 0xff241c71, 0x005f5e00,540	0xffca77f4, 0xff20dd50, 0x006855eb,541	0xff86c552, 0xff18137a, 0x00773648,542	0x00000001//output gain543};544 545static u32 coef_16to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {546	0x0015a105,//header547	0x00000292,//input gain548	0x00e4320a, 0xff41d2d9, 0x004911ac,549	0x005dd9e3, 0xff4c7d80, 0x0052103e,550	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,551	0xffc4b414, 0xff68582c, 0x006b38e5,552	0xffabb861, 0xff704bec, 0x0074de52,553	0xffa19f4c, 0xff729059, 0x007c7e90,554	0x00000003,//output gain555	0x00005105,//header556	0x00000292,//input gain557	0x00e4320a, 0xff41d2d9, 0x004911ac,558	0x005dd9e3, 0xff4c7d80, 0x0052103e,559	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,560	0xffc4b414, 0xff68582c, 0x006b38e5,561	0xffabb861, 0xff704bec, 0x0074de52,562	0xffa19f4c, 0xff729059, 0x007c7e90,563	0x00000001//output gain564};565 566static u32 coef_16to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {567	0x00006102,//header568	0x0001d727,//input gain569	0x00fc2fc7, 0xff9bb27b, 0x001c564c,570	0x00e55557, 0xffcadd5b, 0x003d80ba,571	0x00d13397, 0xfff232f8, 0x00683337,572	0x00000002//output gain573};574 575static u32 coef_16to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {576	0x00156105,//interpolation + IIR filter577	0x0000d649,//input gain578	0x00e87afb, 0xff5f69d0, 0x003df3cf,579	0x007ce488, 0xff99a5c8, 0x0056a6a0,580	0x00344928, 0xffcba3e5, 0x006be470,581	0x00137aa7, 0xffe60276, 0x00773410,582	0x0005fa2a, 0xfff1ac11, 0x007c795b,583	0x00012d36, 0xfff5eca2, 0x007f10ef,584	0x00000002,//output gain585	0x0021a102,//interpolation + IIR filter586	0x00000e00,//input gain587	0x00e2e000, 0xff6e1a00, 0x002aaa00,588	0x00610a00, 0xff5dda00, 0x003ccc00,589	0x00163a00, 0xff3c0400, 0x00633200,590	0x00000003,//output gain591	0x002c0204,//Farrow Filter592	0x000aaaab,593	0xffaaaaab,594	0xfffaaaab,595	0x00555555,596	0xff600000,597	0xfff55555,598	0x00155555,599	0x00055555,600	0xffeaaaab,601	0x00200000,602	0x00005101,//IIR Filter + Decimator603	0x0000203c,//input gain604	0x00f52d35, 0xff2e2162, 0x005a21e0,605	0x00c6f0f0, 0xff2ecd69, 0x006fa78d,606	0x00000001//output gain607};608 609static u32 coef_16to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {610	0x0000a105,//interpolation + IIR Filter611	0x00000784,//input gain612	0x00cc516e, 0xff2c9639, 0x005ad5b3,613	0x0013ad0d, 0xff3d4799, 0x0063ce75,614	0xffb6f398, 0xff5138d1, 0x006e9e1f,615	0xff9186e5, 0xff5f96a4, 0x0076a86e,616	0xff82089c, 0xff676b81, 0x007b9f8a,617	0xff7c48a5, 0xff6a31e7, 0x007ebb7b,618	0x00000003//output gain619};620 621static u32 coef_16to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {622	0x000c6102,//header623	0x0001d727,//input gain624	0x00fc2fc7, 0xff9bb27b, 0x001c564c,625	0x00e55557, 0xffcadd5b, 0x003d80ba,626	0x00d13397, 0xfff232f8, 0x00683337,627	0x00000002,//output gain628	0x0018a102,//header629	0x000005d6,//input gain630	0x00c6543e, 0xff342935, 0x0052f116,631	0x000a1d78, 0xff3330c0, 0x005f88a3,632	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,633	0x00000003,//output gain634	0x00000204,//farrow635	0x000aaaab,636	0xffaaaaab,637	0xfffaaaab,638	0x00555555,639	0xff600000,640	0xfff55555,641	0x00155555,642	0x00055555,643	0xffeaaaab,644	0x00200000645};646 647static u32 coef_16to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {648	0x000c6102,//header649	0x0001d727,//input gain650	0x00fc2fc7, 0xff9bb27b, 0x001c564c,651	0x00e55557, 0xffcadd5b, 0x003d80ba,652	0x00d13397, 0xfff232f8, 0x00683337,653	0x00000002,//output gain654	0x0000a102,//header655	0x000005d6,//input gain656	0x00c6543e, 0xff342935, 0x0052f116,657	0x000a1d78, 0xff3330c0, 0x005f88a3,658	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,659	0x00000003//output gain660};661 662static u32 coef_16to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {663	0x000c6102,//header664	0x0001d727,//input gain665	0x00fc2fc7, 0xff9bb27b, 0x001c564c,666	0x00e55557, 0xffcadd5b, 0x003d80ba,667	0x00d13397, 0xfff232f8, 0x00683337,668	0x00000002,//output gain669	0x00186102,//header670	0x000013d9,//input gain671	0x00ebd477, 0xff4ce383, 0x0042049d,672	0x0089c278, 0xff54414d, 0x00531ded,673	0x004a5e07, 0xff53cf41, 0x006efbdc,674	0x00000002,//output gain675	0x0024a102,//header676	0x0000007d,//input gain677	0x007d1f20, 0xff1a540e, 0x00678bf9,678	0xff916625, 0xff16b0ff, 0x006e433a,679	0xff5af660, 0xff0eb91f, 0x00797356,680	0x00000003,//output gain681	0x00000204,//farrow682	0x000aaaab,683	0xffaaaaab,684	0xfffaaaab,685	0x00555555,686	0xff600000,687	0xfff55555,688	0x00155555,689	0x00055555,690	0xffeaaaab,691	0x00200000692};693 694static u32 coef_16to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {695	0x000c6102,//header696	0x0001d727,//input gain697	0x00fc2fc7, 0xff9bb27b, 0x001c564c,698	0x00e55557, 0xffcadd5b, 0x003d80ba,699	0x00d13397, 0xfff232f8, 0x00683337,700	0x00000002,//output gain701	0x00186102,//header702	0x000013d9,//input gain703	0x00ebd477, 0xff4ce383, 0x0042049d,704	0x0089c278, 0xff54414d, 0x00531ded,705	0x004a5e07, 0xff53cf41, 0x006efbdc,706	0x00000002,//output gain707	0x0000a102,//header708	0x0000007d,//input gain709	0x007d1f20, 0xff1a540e, 0x00678bf9,710	0xff916625, 0xff16b0ff, 0x006e433a,711	0xff5af660, 0xff0eb91f, 0x00797356,712	0x00000003//output gain713};714 715static u32 coef_22to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {716	0x000c6102,//header717	0x000005f3,//input gain718	0x00d816d6, 0xff385383, 0x004fe566,719	0x003c548d, 0xff38c23d, 0x005d0b1c,720	0xfff02f7d, 0xff31e983, 0x0072d65d,721	0x00000002,//output gain722	0x00179204,//farrow723	0x000aaaab,724	0xffaaaaab,725	0xfffaaaab,726	0x00555555,727	0xff600000,728	0xfff55555,729	0x00155555,730	0x00055555,731	0xffeaaaab,732	0x00200000,733	0x00005102,//header734	0x0001d727,//input gain735	0x00fc2fc7, 0xff9bb27b, 0x001c564c,736	0x00e55557, 0xffcadd5b, 0x003d80ba,737	0x00d13397, 0xfff232f8, 0x00683337,738	0x00000001//output gain739};740 741static u32 coef_22to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {742	0x00005102,//header743	0x0001d727,//input gain744	0x00fc2fc7, 0xff9bb27b, 0x001c564c,745	0x00e55557, 0xffcadd5b, 0x003d80ba,746	0x00d13397, 0xfff232f8, 0x00683337,747	0x00000001//output gain748};749 750static u32 coef_22to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {751	0x000c6102,//header752	0x0000015f,//input gain753	0x00a7909c, 0xff241c71, 0x005f5e00,754	0xffca77f4, 0xff20dd50, 0x006855eb,755	0xff86c552, 0xff18137a, 0x00773648,756	0x00000002,//output gain757	0x00186102,//header758	0x000005f3,//input gain759	0x00d816d6, 0xff385383, 0x004fe566,760	0x003c548d, 0xff38c23d, 0x005d0b1c,761	0xfff02f7d, 0xff31e983, 0x0072d65d,762	0x00000002,//output gain763	0x00239204,//farrow764	0x000aaaab,765	0xffaaaaab,766	0xfffaaaab,767	0x00555555,768	0xff600000,769	0xfff55555,770	0x00155555,771	0x00055555,772	0xffeaaaab,773	0x00200000,774	0x00005102,//header775	0x0001d727,//input gain776	0x00fc2fc7, 0xff9bb27b, 0x001c564c,777	0x00e55557, 0xffcadd5b, 0x003d80ba,778	0x00d13397, 0xfff232f8, 0x00683337,779	0x00000001//output gain780};781 782static u32 coef_22to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {783	0x000c6102,//header784	0x0001d727,//input gain785	0x00fc2fc7, 0xff9bb27b, 0x001c564c,786	0x00e55557, 0xffcadd5b, 0x003d80ba,787	0x00d13397, 0xfff232f8, 0x00683337,788	0x00000002,//output gain789	0x00186102,//header790	0x000013d9,//input gain791	0x00ebd477, 0xff4ce383, 0x0042049d,792	0x0089c278, 0xff54414d, 0x00531ded,793	0x004a5e07, 0xff53cf41, 0x006efbdc,794	0x00000002,//output gain795	0x00235204,//farrow796	0x000aaaab,797	0xffaaaaab,798	0xfffaaaab,799	0x00555555,800	0xff600000,801	0xfff55555,802	0x00155555,803	0x00055555,804	0xffeaaaab,805	0x00200000,806	0x00005102,//header807	0x0001d029,//input gain808	0x00f2a98b, 0xff92aa71, 0x001fcd16,809	0x00ae9004, 0xffb85140, 0x0041813a,810	0x007f8ed1, 0xffd585fc, 0x006a69e6,811	0x00000001//output gain812};813 814static u32 coef_22to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {815	0x000c6102,//header816	0x0001d727,//input gain817	0x00fc2fc7, 0xff9bb27b, 0x001c564c,818	0x00e55557, 0xffcadd5b, 0x003d80ba,819	0x00d13397, 0xfff232f8, 0x00683337,820	0x00000002,//output gain821	0x00186102,//header822	0x000013d9,//input gain823	0x00ebd477, 0xff4ce383, 0x0042049d,824	0x0089c278, 0xff54414d, 0x00531ded,825	0x004a5e07, 0xff53cf41, 0x006efbdc,826	0x00000002,//output gain827	0x00009204,//farrow828	0x000aaaab,829	0xffaaaaab,830	0xfffaaaab,831	0x00555555,832	0xff600000,833	0xfff55555,834	0x00155555,835	0x00055555,836	0xffeaaaab,837	0x00200000838};839 840static u32 coef_22to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {841	0x00006102,//header842	0x0001d727,//input gain843	0x00fc2fc7, 0xff9bb27b, 0x001c564c,844	0x00e55557, 0xffcadd5b, 0x003d80ba,845	0x00d13397, 0xfff232f8, 0x00683337,846	0x00000002//output gain847};848 849static u32 coef_22to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {850	0x000c6102,//header851	0x0001d727,//input gain852	0x00fc2fc7, 0xff9bb27b, 0x001c564c,853	0x00e55557, 0xffcadd5b, 0x003d80ba,854	0x00d13397, 0xfff232f8, 0x00683337,855	0x00000002,//output gain856	0x00186102,//header857	0x000013d9,//input gain858	0x00ebd477, 0xff4ce383, 0x0042049d,859	0x0089c278, 0xff54414d, 0x00531ded,860	0x004a5e07, 0xff53cf41, 0x006efbdc,861	0x00000002,//output gain862	0x00005204,//farrow863	0x000aaaab,864	0xffaaaaab,865	0xfffaaaab,866	0x00555555,867	0xff600000,868	0xfff55555,869	0x00155555,870	0x00055555,871	0xffeaaaab,872	0x00200000873};874 875static u32 coef_22to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {876	0x000c6102,//header877	0x0001d727,//input gain878	0x00fc2fc7, 0xff9bb27b, 0x001c564c,879	0x00e55557, 0xffcadd5b, 0x003d80ba,880	0x00d13397, 0xfff232f8, 0x00683337,881	0x00000002,//output gain882	0x00006102,//header883	0x000013d9,//input gain884	0x00ebd477, 0xff4ce383, 0x0042049d,885	0x0089c278, 0xff54414d, 0x00531ded,886	0x004a5e07, 0xff53cf41, 0x006efbdc,887	0x00000002//output gain888};889 890static u32 coef_22to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {891	0x000c6102,//header892	0x0001d727,//input gain893	0x00fc2fc7, 0xff9bb27b, 0x001c564c,894	0x00e55557, 0xffcadd5b, 0x003d80ba,895	0x00d13397, 0xfff232f8, 0x00683337,896	0x00000002,//output gain897	0x00186102,//header898	0x000013d9,//input gain899	0x00ebd477, 0xff4ce383, 0x0042049d,900	0x0089c278, 0xff54414d, 0x00531ded,901	0x004a5e07, 0xff53cf41, 0x006efbdc,902	0x00000002,//output gain903	0x00246102,//header904	0x0000010a,//input gain905	0x00c93dc4, 0xff26f5f6, 0x005d1041,906	0x001002c4, 0xff245b76, 0x00666002,907	0xffc30a45, 0xff1baecd, 0x00765921,908	0x00000002,//output gain909	0x00005204,//farrow910	0x000aaaab,911	0xffaaaaab,912	0xfffaaaab,913	0x00555555,914	0xff600000,915	0xfff55555,916	0x00155555,917	0x00055555,918	0xffeaaaab,919	0x00200000920};921 922static u32 coef_22to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {923	0x000c6102,//header924	0x0001d727,//input gain925	0x00fc2fc7, 0xff9bb27b, 0x001c564c,926	0x00e55557, 0xffcadd5b, 0x003d80ba,927	0x00d13397, 0xfff232f8, 0x00683337,928	0x00000002,//output gain929	0x00186102,//header930	0x000013d9,//input gain931	0x00ebd477, 0xff4ce383, 0x0042049d,932	0x0089c278, 0xff54414d, 0x00531ded,933	0x004a5e07, 0xff53cf41, 0x006efbdc,934	0x00000002,//output gain935	0x00006102,//header936	0x0000010a,//input gain937	0x00c93dc4, 0xff26f5f6, 0x005d1041,938	0x001002c4, 0xff245b76, 0x00666002,939	0xffc30a45, 0xff1baecd, 0x00765921,940	0x00000002//output gain941};942 943static u32 coef_22to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {944	0x000c6102,//header945	0x0001d727,//input gain946	0x00fc2fc7, 0xff9bb27b, 0x001c564c,947	0x00e55557, 0xffcadd5b, 0x003d80ba,948	0x00d13397, 0xfff232f8, 0x00683337,949	0x00000002,//output gain950	0x00186102,//header951	0x000013d9,//input gain952	0x00ebd477, 0xff4ce383, 0x0042049d,953	0x0089c278, 0xff54414d, 0x00531ded,954	0x004a5e07, 0xff53cf41, 0x006efbdc,955	0x00000002,//output gain956	0x00246102,//header957	0x0000010a,//input gain958	0x00c93dc4, 0xff26f5f6, 0x005d1041,959	0x001002c4, 0xff245b76, 0x00666002,960	0xffc30a45, 0xff1baecd, 0x00765921,961	0x00000002,//output gain962	0x00000204,//farrow963	0x000aaaab,964	0xffaaaaab,965	0xfffaaaab,966	0x00555555,967	0xff600000,968	0xfff55555,969	0x00155555,970	0x00055555,971	0xffeaaaab,972	0x00200000973};974 975static u32 coef_24to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {976	0x00009105,//header977	0x000005e1,//input gain978	0x00dca92f, 0xff45647a, 0x0046b59c,979	0x00429d1e, 0xff4fec62, 0x00516d30,980	0xffdea779, 0xff5e08ba, 0x0060185e,981	0xffafbab2, 0xff698d5a, 0x006ce3ae,982	0xff9a82d2, 0xff704674, 0x007633c5,983	0xff923433, 0xff721128, 0x007cff42,984	0x00000001//output gain985};986 987static u32 coef_24to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {988	0x000f6103,//header989	0x000001e0,//input gain990	0x00de44c0, 0xff380b7f, 0x004ffc73,991	0x00494b44, 0xff3d493a, 0x005908bf,992	0xffe9a3c8, 0xff425647, 0x006745f7,993	0xffc42d61, 0xff40a6c7, 0x00776709,994	0x00000002,//output gain995	0x001a5204,//farrow996	0x000aaaab,997	0xffaaaaab,998	0xfffaaaab,999	0x00555555,1000	0xff600000,1001	0xfff55555,1002	0x00155555,1003	0x00055555,1004	0xffeaaaab,1005	0x00200000,1006	0x00005102,//header1007	0x0001d727,//input gain1008	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1009	0x00e55557, 0xffcadd5b, 0x003d80ba,1010	0x00d13397, 0xfff232f8, 0x00683337,1011	0x00000001//output gain1012};1013 1014static u32 coef_24to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {1015	0x00156105,//header1016	0x00000292,//input gain1017	0x00e4320a, 0xff41d2d9, 0x004911ac,1018	0x005dd9e3, 0xff4c7d80, 0x0052103e,1019	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1020	0xffc4b414, 0xff68582c, 0x006b38e5,1021	0xffabb861, 0xff704bec, 0x0074de52,1022	0xffa19f4c, 0xff729059, 0x007c7e90,1023	0x00000002,//output gain1024	0x00009105,//header1025	0x00000292,//input gain1026	0x00e4320a, 0xff41d2d9, 0x004911ac,1027	0x005dd9e3, 0xff4c7d80, 0x0052103e,1028	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1029	0xffc4b414, 0xff68582c, 0x006b38e5,1030	0xffabb861, 0xff704bec, 0x0074de52,1031	0xffa19f4c, 0xff729059, 0x007c7e90,1032	0x00000001//output gain1033};1034 1035static u32 coef_24to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {1036	0x000c6102,//header1037	0x0001d029,//input gain1038	0x00f2a98b, 0xff92aa71, 0x001fcd16,1039	0x00ae9004, 0xffb85140, 0x0041813a,1040	0x007f8ed1, 0xffd585fc, 0x006a69e6,1041	0x00000002,//output gain1042	0x001b6103,//header1043	0x000001e0,//input gain1044	0x00de44c0, 0xff380b7f, 0x004ffc73,1045	0x00494b44, 0xff3d493a, 0x005908bf,1046	0xffe9a3c8, 0xff425647, 0x006745f7,1047	0xffc42d61, 0xff40a6c7, 0x00776709,1048	0x00000002,//output gain1049	0x00265204,//farrow1050	0x000aaaab,1051	0xffaaaaab,1052	0xfffaaaab,1053	0x00555555,1054	0xff600000,1055	0xfff55555,1056	0x00155555,1057	0x00055555,1058	0xffeaaaab,1059	0x00200000,1060	0x00005102,//header1061	0x0001d727,//input gain1062	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1063	0x00e55557, 0xffcadd5b, 0x003d80ba,1064	0x00d13397, 0xfff232f8, 0x00683337,1065	0x00000001//output gain1066};1067 1068static u32 coef_24to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {1069	0x000c6102,//header1070	0x0001d727,//input gain1071	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1072	0x00e55557, 0xffcadd5b, 0x003d80ba,1073	0x00d13397, 0xfff232f8, 0x00683337,1074	0x00000002,//output gain1075	0x00186102,//header1076	0x000013d9,//input gain1077	0x00ebd477, 0xff4ce383, 0x0042049d,1078	0x0089c278, 0xff54414d, 0x00531ded,1079	0x004a5e07, 0xff53cf41, 0x006efbdc,1080	0x00000002,//output gain1081	0x00009102,//header1082	0x000013d9,//input gain1083	0x00ebd477, 0xff4ce383, 0x0042049d,1084	0x0089c278, 0xff54414d, 0x00531ded,1085	0x004a5e07, 0xff53cf41, 0x006efbdc,1086	0x00000001//output gain1087};1088 1089static u32 coef_24to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {1090	0x000c6102,//header1091	0x0001d727,//input gain1092	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1093	0x00e55557, 0xffcadd5b, 0x003d80ba,1094	0x00d13397, 0xfff232f8, 0x00683337,1095	0x00000002,//output gain1096	0x00186102,//header1097	0x000013d9,//input gain1098	0x00ebd477, 0xff4ce383, 0x0042049d,1099	0x0089c278, 0xff54414d, 0x00531ded,1100	0x004a5e07, 0xff53cf41, 0x006efbdc,1101	0x00000002,//output gain1102	0x00230204,//farrow1103	0x000aaaab,1104	0xffaaaaab,1105	0xfffaaaab,1106	0x00555555,1107	0xff600000,1108	0xfff55555,1109	0x00155555,1110	0x00055555,1111	0xffeaaaab,1112	0x00200000,1113	0x00005102,//header1114	0x00001685,//input gain1115	0x00f53ae9, 0xff52f196, 0x003e3e08,1116	0x00b9f857, 0xff5d8985, 0x0050070a,1117	0x008c3e86, 0xff6053f0, 0x006d98ef,1118	0x00000001//output gain1119};1120 1121static u32 coef_24to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {1122	0x00006102,//header1123	0x0001d727,//input gain1124	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1125	0x00e55557, 0xffcadd5b, 0x003d80ba,1126	0x00d13397, 0xfff232f8, 0x00683337,1127	0x00000002//output gain1128};1129 1130static u32 coef_24to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {1131	0x000c6102,//header1132	0x0001d727,//input gain1133	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1134	0x00e55557, 0xffcadd5b, 0x003d80ba,1135	0x00d13397, 0xfff232f8, 0x00683337,1136	0x00000002,//output gain1137	0x00186102,//header1138	0x000013d9,//input gain1139	0x00ebd477, 0xff4ce383, 0x0042049d,1140	0x0089c278, 0xff54414d, 0x00531ded,1141	0x004a5e07, 0xff53cf41, 0x006efbdc,1142	0x00000002,//output gain1143	0x00246102,//header1144	0x0000010a,//input gain1145	0x00c93dc4, 0xff26f5f6, 0x005d1041,1146	0x001002c4, 0xff245b76, 0x00666002,1147	0xffc30a45, 0xff1baecd, 0x00765921,1148	0x00000002,//output gain1149	0x002f0204,//farrow1150	0x000aaaab,1151	0xffaaaaab,1152	0xfffaaaab,1153	0x00555555,1154	0xff600000,1155	0xfff55555,1156	0x00155555,1157	0x00055555,1158	0xffeaaaab,1159	0x00200000,1160	0x00005102,//header1161	0x00000138,//input gain1162	0x00d5d232, 0xff2a3bf8, 0x005a785c,1163	0x0034001b, 0xff283109, 0x006462a6,1164	0xffe6746a, 0xff1fb09c, 0x00758a91,1165	0x00000001//output gain1166};1167 1168static u32 coef_24to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {1169	0x000c6102,//header1170	0x0001d727,//input gain1171	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1172	0x00e55557, 0xffcadd5b, 0x003d80ba,1173	0x00d13397, 0xfff232f8, 0x00683337,1174	0x00000002,//output gain1175	0x00006102,//header1176	0x000013d9,//input gain1177	0x00ebd477, 0xff4ce383, 0x0042049d,1178	0x0089c278, 0xff54414d, 0x00531ded,1179	0x004a5e07, 0xff53cf41, 0x006efbdc,1180	0x00000002//output gain1181};1182 1183static u32 coef_24to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {1184	0x000c6102,//header1185	0x0001d727,//input gain1186	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1187	0x00e55557, 0xffcadd5b, 0x003d80ba,1188	0x00d13397, 0xfff232f8, 0x00683337,1189	0x00000002,//output gain1190	0x00186102,//header1191	0x000013d9,//input gain1192	0x00ebd477, 0xff4ce383, 0x0042049d,1193	0x0089c278, 0xff54414d, 0x00531ded,1194	0x004a5e07, 0xff53cf41, 0x006efbdc,1195	0x00000002,//output gain1196	0x00246102,//header1197	0x0000010a,//input gain1198	0x00c93dc4, 0xff26f5f6, 0x005d1041,1199	0x001002c4, 0xff245b76, 0x00666002,1200	0xffc30a45, 0xff1baecd, 0x00765921,1201	0x00000002,//output gain1202	0x00000204,//farrow1203	0x000aaaab,1204	0xffaaaaab,1205	0xfffaaaab,1206	0x00555555,1207	0xff600000,1208	0xfff55555,1209	0x00155555,1210	0x00055555,1211	0xffeaaaab,1212	0x002000001213};1214 1215static u32 coef_24to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {1216	0x000c6102,//header1217	0x0001d727,//input gain1218	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1219	0x00e55557, 0xffcadd5b, 0x003d80ba,1220	0x00d13397, 0xfff232f8, 0x00683337,1221	0x00000002,//output gain1222	0x00186102,//header1223	0x000013d9,//input gain1224	0x00ebd477, 0xff4ce383, 0x0042049d,1225	0x0089c278, 0xff54414d, 0x00531ded,1226	0x004a5e07, 0xff53cf41, 0x006efbdc,1227	0x00000002,//output gain1228	0x00006102,//header1229	0x0000010a,//input gain1230	0x00c93dc4, 0xff26f5f6, 0x005d1041,1231	0x001002c4, 0xff245b76, 0x00666002,1232	0xffc30a45, 0xff1baecd, 0x00765921,1233	0x00000002//output gain1234};1235 1236static u32 coef_32to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {1237	0x000c5102,//header1238	0x000013d9,//input gain1239	0x00ebd477, 0xff4ce383, 0x0042049d,1240	0x0089c278, 0xff54414d, 0x00531ded,1241	0x004a5e07, 0xff53cf41, 0x006efbdc,1242	0x00000001,//output gain1243	0x00005102,//header1244	0x0001d727,//input gain1245	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1246	0x00e55557, 0xffcadd5b, 0x003d80ba,1247	0x00d13397, 0xfff232f8, 0x00683337,1248	0x00000001//output gain1249};1250 1251static u32 coef_32to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {1252	0x000ca102,//header1253	0x000000af,//input gain1254	0x00c65663, 0xff23d2ce, 0x005f97d6,1255	0x00086ad6, 0xff20ec4f, 0x00683201,1256	0xffbbbef6, 0xff184447, 0x00770963,1257	0x00000003,//output gain1258	0x00175204,//farrow1259	0x000aaaab,1260	0xffaaaaab,1261	0xfffaaaab,1262	0x00555555,1263	0xff600000,1264	0xfff55555,1265	0x00155555,1266	0x00055555,1267	0xffeaaaab,1268	0x00200000,1269	0x0000d102,//header1270	0x000013d9,//input gain1271	0x00ebd477, 0xff4ce383, 0x0042049d,1272	0x0089c278, 0xff54414d, 0x00531ded,1273	0x004a5e07, 0xff53cf41, 0x006efbdc,1274	0x00000001//output gain1275};1276 1277static u32 coef_32to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {1278	0x00005102,//header1279	0x0001d727,//input gain1280	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1281	0x00e55557, 0xffcadd5b, 0x003d80ba,1282	0x00d13397, 0xfff232f8, 0x00683337,1283	0x00000001//output gain1284};1285 1286static u32 coef_32to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {1287	0x000fa103,//header1288	0x000001e0,//input gain1289	0x00de44c0, 0xff380b7f, 0x004ffc73,1290	0x00494b44, 0xff3d493a, 0x005908bf,1291	0xffe9a3c8, 0xff425647, 0x006745f7,1292	0xffc42d61, 0xff40a6c7, 0x00776709,1293	0x00000003,//output gain1294	0x001a5204,//farrow1295	0x000aaaab,1296	0xffaaaaab,1297	0xfffaaaab,1298	0x00555555,1299	0xff600000,1300	0xfff55555,1301	0x00155555,1302	0x00055555,1303	0xffeaaaab,1304	0x00200000,1305	0x00005102,//header1306	0x0001d727,//input gain1307	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1308	0x00e55557, 0xffcadd5b, 0x003d80ba,1309	0x00d13397, 0xfff232f8, 0x00683337,1310	0x00000001//output gain1311};1312 1313static u32 coef_32to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {1314	0x000ca102,//header1315	0x000013d9,//input gain1316	0x00ebd477, 0xff4ce383, 0x0042049d,1317	0x0089c278, 0xff54414d, 0x00531ded,1318	0x004a5e07, 0xff53cf41, 0x006efbdc,1319	0x00000003,//output gain1320	0x0000d102,//header1321	0x000013d9,//input gain1322	0x00ebd477, 0xff4ce383, 0x0042049d,1323	0x0089c278, 0xff54414d, 0x00531ded,1324	0x004a5e07, 0xff53cf41, 0x006efbdc,1325	0x00000001//output gain1326};1327 1328static u32 coef_32to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {1329	0x000c6102,//header1330	0x0001d727,//input gain1331	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1332	0x00e55557, 0xffcadd5b, 0x003d80ba,1333	0x00d13397, 0xfff232f8, 0x00683337,1334	0x00000002,//output gain1335	0x0018a102,//header1336	0x000005d6,//input gain1337	0x00c6543e, 0xff342935, 0x0052f116,1338	0x000a1d78, 0xff3330c0, 0x005f88a3,1339	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,1340	0x00000003,//output gain1341	0x00235204,//farrow1342	0x000aaaab,1343	0xffaaaaab,1344	0xfffaaaab,1345	0x00555555,1346	0xff600000,1347	0xfff55555,1348	0x00155555,1349	0x00055555,1350	0xffeaaaab,1351	0x00200000,1352	0x00005102,//header1353	0x0000015f,//input gain1354	0x00a7909c, 0xff241c71, 0x005f5e00,1355	0xffca77f4, 0xff20dd50, 0x006855eb,1356	0xff86c552, 0xff18137a, 0x00773648,1357	0x00000001//output gain1358};1359 1360static u32 coef_32to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {1361	0x0015a105,//header1362	0x00000292,//input gain1363	0x00e4320a, 0xff41d2d9, 0x004911ac,1364	0x005dd9e3, 0xff4c7d80, 0x0052103e,1365	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1366	0xffc4b414, 0xff68582c, 0x006b38e5,1367	0xffabb861, 0xff704bec, 0x0074de52,1368	0xffa19f4c, 0xff729059, 0x007c7e90,1369	0x00000003,//output gain1370	0x00005105,//header1371	0x00000292,//input gain1372	0x00e4320a, 0xff41d2d9, 0x004911ac,1373	0x005dd9e3, 0xff4c7d80, 0x0052103e,1374	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1375	0xffc4b414, 0xff68582c, 0x006b38e5,1376	0xffabb861, 0xff704bec, 0x0074de52,1377	0xffa19f4c, 0xff729059, 0x007c7e90,1378	0x00000001//output gain1379};1380 1381static u32 coef_32to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {1382	0x000c6102,//header1383	0x0001d727,//input gain1384	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1385	0x00e55557, 0xffcadd5b, 0x003d80ba,1386	0x00d13397, 0xfff232f8, 0x00683337,1387	0x00000002,//output gain1388	0x0018a102,//header1389	0x000005d6,//input gain1390	0x00c6543e, 0xff342935, 0x0052f116,1391	0x000a1d78, 0xff3330c0, 0x005f88a3,1392	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,1393	0x00000003,//output gain1394	0x00230204,//farrow1395	0x000aaaab,1396	0xffaaaaab,1397	0xfffaaaab,1398	0x00555555,1399	0xff600000,1400	0xfff55555,1401	0x00155555,1402	0x00055555,1403	0xffeaaaab,1404	0x00200000,1405	0x00005102,//header1406	0x000005f3,//input gain1407	0x00d816d6, 0xff385383, 0x004fe566,1408	0x003c548d, 0xff38c23d, 0x005d0b1c,1409	0xfff02f7d, 0xff31e983, 0x0072d65d,1410	0x00000001//output gain1411};1412 1413static u32 coef_32to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {1414	0x0000a105,//header1415	0x00000292,//input gain1416	0x00e4320a, 0xff41d2d9, 0x004911ac,1417	0x005dd9e3, 0xff4c7d80, 0x0052103e,1418	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1419	0xffc4b414, 0xff68582c, 0x006b38e5,1420	0xffabb861, 0xff704bec, 0x0074de52,1421	0xffa19f4c, 0xff729059, 0x007c7e90,1422	0x00000003//output gain1423};1424 1425static u32 coef_32to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {1426	0x000c6102,//header1427	0x0001d727,//input gain1428	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1429	0x00e55557, 0xffcadd5b, 0x003d80ba,1430	0x00d13397, 0xfff232f8, 0x00683337,1431	0x00000002,//output gain1432	0x0018a102,//header1433	0x000005d6,//input gain1434	0x00c6543e, 0xff342935, 0x0052f116,1435	0x000a1d78, 0xff3330c0, 0x005f88a3,1436	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,1437	0x00000003,//output gain1438	0x00000204,//farrow1439	0x000aaaab,1440	0xffaaaaab,1441	0xfffaaaab,1442	0x00555555,1443	0xff600000,1444	0xfff55555,1445	0x00155555,1446	0x00055555,1447	0xffeaaaab,1448	0x002000001449};1450 1451static u32 coef_32to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {1452	0x000c6102,//header1453	0x0001d727,//input gain1454	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1455	0x00e55557, 0xffcadd5b, 0x003d80ba,1456	0x00d13397, 0xfff232f8, 0x00683337,1457	0x00000002,//output gain1458	0x0000a102,//header1459	0x000005d6,//input gain1460	0x00c6543e, 0xff342935, 0x0052f116,1461	0x000a1d78, 0xff3330c0, 0x005f88a3,1462	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,1463	0x00000003//output gain1464};1465 1466static u32 coef_44to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {1467	0x00120104,//IIR Filter1468	0x00000af2,//input gain1469	0x0057eebe, 0xff1e9863, 0x00652604,1470	0xff7206ea, 0xff22ad7e, 0x006d47e1,1471	0xff42a4d7, 0xff26e722, 0x0075fd83,1472	0xff352f66, 0xff29312b, 0x007b986b,1473	0xff310a07, 0xff296f51, 0x007eca7c,1474	0x00000001,//output gain1475	0x001d9204,//Farrow Filter + decimation1476	0x000aaaab,1477	0xffaaaaab,1478	0xfffaaaab,1479	0x00555555,1480	0xff600000,1481	0xfff55555,1482	0x00155555,1483	0x00055555,1484	0xffeaaaab,1485	0x00200000,1486	0x00005105,//IIR Filter + Decimator1487	0x0000d649,//input gain1488	0x00e87afb, 0xff5f69d0, 0x003df3cf,1489	0x007ce488, 0xff99a5c8, 0x0056a6a0,1490	0x00344928, 0xffcba3e5, 0x006be470,1491	0x00137aa7, 0xffe60276, 0x00773410,1492	0x0005fa2a, 0xfff1ac11, 0x007c795b,1493	0x00012d36, 0xfff5eca2, 0x007f10ef,1494	0x00000001//output gain1495};1496 1497static u32 coef_44to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {1498	0x000c5102,//header1499	0x000013d9,//input gain1500	0x00ebd477, 0xff4ce383, 0x0042049d,1501	0x0089c278, 0xff54414d, 0x00531ded,1502	0x004a5e07, 0xff53cf41, 0x006efbdc,1503	0x00000001,//output gain1504	0x00005102,//header1505	0x0001d727,//input gain1506	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1507	0x00e55557, 0xffcadd5b, 0x003d80ba,1508	0x00d13397, 0xfff232f8, 0x00683337,1509	0x00000001//output gain1510};1511 1512static u32 coef_44to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {1513	0x00126104,//IIR Filter + interpolation1514	0x00000af2,//input gain1515	0x0057eebe, 0xff1e9863, 0x00652604,1516	0xff7206ea, 0xff22ad7e, 0x006d47e1,1517	0xff42a4d7, 0xff26e722, 0x0075fd83,1518	0xff352f66, 0xff29312b, 0x007b986b,1519	0xff310a07, 0xff296f51, 0x007eca7c,1520	0x00000002,//output gain1521	0x001d9204,//Farrow Filter + decimation1522	0x000aaaab,1523	0xffaaaaab,1524	0xfffaaaab,1525	0x00555555,1526	0xff600000,1527	0xfff55555,1528	0x00155555,1529	0x00055555,1530	0xffeaaaab,1531	0x00200000,1532	0x00005105,//IIR Filter + Decimator1533	0x0000d649,//input gain1534	0x00e87afb, 0xff5f69d0, 0x003df3cf,1535	0x007ce488, 0xff99a5c8, 0x0056a6a0,1536	0x00344928, 0xffcba3e5, 0x006be470,1537	0x00137aa7, 0xffe60276, 0x00773410,1538	0x0005fa2a, 0xfff1ac11, 0x007c795b,1539	0x00012d36, 0xfff5eca2, 0x007f10ef,1540	0x00000001//output gain1541};1542 1543static u32 coef_44to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {1544	0x00005102,//header1545	0x0001d727,//input gain1546	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1547	0x00e55557, 0xffcadd5b, 0x003d80ba,1548	0x00d13397, 0xfff232f8, 0x00683337,1549	0x00000001//output gain1550};1551 1552static u32 coef_44to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {1553	0x000c6102,//header1554	0x00001685,//input gain1555	0x00f53ae9, 0xff52f196, 0x003e3e08,1556	0x00b9f857, 0xff5d8985, 0x0050070a,1557	0x008c3e86, 0xff6053f0, 0x006d98ef,1558	0x00000002,//output gain1559	0x00175204,//farrow1560	0x000aaaab,1561	0xffaaaaab,1562	0xfffaaaab,1563	0x00555555,1564	0xff600000,1565	0xfff55555,1566	0x00155555,1567	0x00055555,1568	0xffeaaaab,1569	0x00200000,1570	0x00005102,//header1571	0x0001d727,//input gain1572	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1573	0x00e55557, 0xffcadd5b, 0x003d80ba,1574	0x00d13397, 0xfff232f8, 0x00683337,1575	0x00000001//output gain1576};1577 1578static u32 coef_44to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {1579	0x000c6102,//header1580	0x0000015f,//input gain1581	0x00a7909c, 0xff241c71, 0x005f5e00,1582	0xffca77f4, 0xff20dd50, 0x006855eb,1583	0xff86c552, 0xff18137a, 0x00773648,1584	0x00000002,//output gain1585	0x00186102,//header1586	0x000005f3,//input gain1587	0x00d816d6, 0xff385383, 0x004fe566,1588	0x003c548d, 0xff38c23d, 0x005d0b1c,1589	0xfff02f7d, 0xff31e983, 0x0072d65d,1590	0x00000002,//output gain1591	0x00239204,//farrow1592	0x000aaaab,1593	0xffaaaaab,1594	0xfffaaaab,1595	0x00555555,1596	0xff600000,1597	0xfff55555,1598	0x00155555,1599	0x00055555,1600	0xffeaaaab,1601	0x00200000,1602	0x00005102,//header1603	0x0001d727,//input gain1604	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1605	0x00e55557, 0xffcadd5b, 0x003d80ba,1606	0x00d13397, 0xfff232f8, 0x00683337,1607	0x00000001//output gain1608};1609 1610static u32 coef_44to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {1611	0x000c6102,//header1612	0x0001d727,//input gain1613	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1614	0x00e55557, 0xffcadd5b, 0x003d80ba,1615	0x00d13397, 0xfff232f8, 0x00683337,1616	0x00000002,//output gain1617	0x00186102,//header1618	0x000013d9,//input gain1619	0x00ebd477, 0xff4ce383, 0x0042049d,1620	0x0089c278, 0xff54414d, 0x00531ded,1621	0x004a5e07, 0xff53cf41, 0x006efbdc,1622	0x00000002,//output gain1623	0x00235204,//farrow1624	0x000aaaab,1625	0xffaaaaab,1626	0xfffaaaab,1627	0x00555555,1628	0xff600000,1629	0xfff55555,1630	0x00155555,1631	0x00055555,1632	0xffeaaaab,1633	0x00200000,1634	0x00005102,//header1635	0x0001d029,//input gain1636	0x00f2a98b, 0xff92aa71, 0x001fcd16,1637	0x00ae9004, 0xffb85140, 0x0041813a,1638	0x007f8ed1, 0xffd585fc, 0x006a69e6,1639	0x00000001//output gain1640};1641 1642static u32 coef_44to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {1643	0x00006102,//header1644	0x0001d727,//input gain1645	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1646	0x00e55557, 0xffcadd5b, 0x003d80ba,1647	0x00d13397, 0xfff232f8, 0x00683337,1648	0x00000002//output gain1649};1650 1651static u32 coef_44to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {1652	0x000c6102,//header1653	0x0001d727,//input gain1654	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1655	0x00e55557, 0xffcadd5b, 0x003d80ba,1656	0x00d13397, 0xfff232f8, 0x00683337,1657	0x00000002,//output gain1658	0x00186102,//header1659	0x000013d9,//input gain1660	0x00ebd477, 0xff4ce383, 0x0042049d,1661	0x0089c278, 0xff54414d, 0x00531ded,1662	0x004a5e07, 0xff53cf41, 0x006efbdc,1663	0x00000002,//output gain1664	0x00005204,//farrow1665	0x000aaaab,1666	0xffaaaaab,1667	0xfffaaaab,1668	0x00555555,1669	0xff600000,1670	0xfff55555,1671	0x00155555,1672	0x00055555,1673	0xffeaaaab,1674	0x002000001675};1676 1677static u32 coef_44to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {1678	0x000c6102,//header1679	0x0001d727,//input gain1680	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1681	0x00e55557, 0xffcadd5b, 0x003d80ba,1682	0x00d13397, 0xfff232f8, 0x00683337,1683	0x00000002,//output gain1684	0x00006102,//header1685	0x000013d9,//input gain1686	0x00ebd477, 0xff4ce383, 0x0042049d,1687	0x0089c278, 0xff54414d, 0x00531ded,1688	0x004a5e07, 0xff53cf41, 0x006efbdc,1689	0x00000002//output gain1690};1691 1692static u32 coef_44to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {1693	0x000c6102,//header1694	0x0001d727,//input gain1695	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1696	0x00e55557, 0xffcadd5b, 0x003d80ba,1697	0x00d13397, 0xfff232f8, 0x00683337,1698	0x00000002,//output gain1699	0x00186102,//header1700	0x000013d9,//input gain1701	0x00ebd477, 0xff4ce383, 0x0042049d,1702	0x0089c278, 0xff54414d, 0x00531ded,1703	0x004a5e07, 0xff53cf41, 0x006efbdc,1704	0x00000002,//output gain1705	0x00246102,//header1706	0x0000010a,//input gain1707	0x00c93dc4, 0xff26f5f6, 0x005d1041,1708	0x001002c4, 0xff245b76, 0x00666002,1709	0xffc30a45, 0xff1baecd, 0x00765921,1710	0x00000002,//output gain1711	0x00005204,//farrow1712	0x000aaaab,1713	0xffaaaaab,1714	0xfffaaaab,1715	0x00555555,1716	0xff600000,1717	0xfff55555,1718	0x00155555,1719	0x00055555,1720	0xffeaaaab,1721	0x002000001722};1723 1724static u32 coef_48to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {1725	0x000c9102,//IIR Filter + Decimator1726	0x00000e00,//input gain1727	0x00e2e000, 0xff6e1a00, 0x002aaa00,1728	0x00610a00, 0xff5dda00, 0x003ccc00,1729	0x00163a00, 0xff3c0400, 0x00633200,1730	0x00000001,//output gain1731	0x00005105,//IIR Filter + Decimator1732	0x0000d649,//input gain1733	0x00e87afb, 0xff5f69d0, 0x003df3cf,1734	0x007ce488, 0xff99a5c8, 0x0056a6a0,1735	0x00344928, 0xffcba3e5, 0x006be470,1736	0x00137aa7, 0xffe60276, 0x00773410,1737	0x0005fa2a, 0xfff1ac11, 0x007c795b,1738	0x00012d36, 0xfff5eca2, 0x007f10ef,1739	0x00000001//output gain1740};1741 1742static u32 coef_48to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {1743	0x000c6102,//header1744	0x000000af,//input gain1745	0x00c65663, 0xff23d2ce, 0x005f97d6,1746	0x00086ad6, 0xff20ec4f, 0x00683201,1747	0xffbbbef6, 0xff184447, 0x00770963,1748	0x00000002,//output gain1749	0x00175204,//farrow1750	0x000aaaab,1751	0xffaaaaab,1752	0xfffaaaab,1753	0x00555555,1754	0xff600000,1755	0xfff55555,1756	0x00155555,1757	0x00055555,1758	0xffeaaaab,1759	0x00200000,1760	0x00235102,//header1761	0x000013d9,//input gain1762	0x00ebd477, 0xff4ce383, 0x0042049d,1763	0x0089c278, 0xff54414d, 0x00531ded,1764	0x004a5e07, 0xff53cf41, 0x006efbdc,1765	0x00000001,//output gain1766	0x00005102,//header1767	0x0001d727,//input gain1768	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1769	0x00e55557, 0xffcadd5b, 0x003d80ba,1770	0x00d13397, 0xfff232f8, 0x00683337,1771	0x00000001//output gain1772};1773 1774static u32 coef_48to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {1775	0x00009105,//IIR Filter + Decimator1776	0x00000784,//input gain1777	0x00cc516e, 0xff2c9639, 0x005ad5b3,1778	0x0013ad0d, 0xff3d4799, 0x0063ce75,1779	0xffb6f398, 0xff5138d1, 0x006e9e1f,1780	0xff9186e5, 0xff5f96a4, 0x0076a86e,1781	0xff82089c, 0xff676b81, 0x007b9f8a,1782	0xff7c48a5, 0xff6a31e7, 0x007ebb7b,1783	0x00000001//output gain1784};1785 1786static u32 coef_48to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {1787	0x000f6103,//header1788	0x000001e0,//input gain1789	0x00de44c0, 0xff380b7f, 0x004ffc73,1790	0x00494b44, 0xff3d493a, 0x005908bf,1791	0xffe9a3c8, 0xff425647, 0x006745f7,1792	0xffc42d61, 0xff40a6c7, 0x00776709,1793	0x00000002,//output gain1794	0x001a5204,//farrow1795	0x000aaaab,1796	0xffaaaaab,1797	0xfffaaaab,1798	0x00555555,1799	0xff600000,1800	0xfff55555,1801	0x00155555,1802	0x00055555,1803	0xffeaaaab,1804	0x00200000,1805	0x00005102,//header1806	0x0001d727,//input gain1807	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1808	0x00e55557, 0xffcadd5b, 0x003d80ba,1809	0x00d13397, 0xfff232f8, 0x00683337,1810	0x00000001//output gain1811};1812 1813static u32 coef_48to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {1814	0x00005102,//header1815	0x0001d727,//input gain1816	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1817	0x00e55557, 0xffcadd5b, 0x003d80ba,1818	0x00d13397, 0xfff232f8, 0x00683337,1819	0x00000001//output gain1820};1821 1822static u32 coef_48to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {1823	0x00156105,//header1824	0x00000292,//input gain1825	0x00e4320a, 0xff41d2d9, 0x004911ac,1826	0x005dd9e3, 0xff4c7d80, 0x0052103e,1827	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1828	0xffc4b414, 0xff68582c, 0x006b38e5,1829	0xffabb861, 0xff704bec, 0x0074de52,1830	0xffa19f4c, 0xff729059, 0x007c7e90,1831	0x00000002,//output gain1832	0x00009105,//header1833	0x00000292,//input gain1834	0x00e4320a, 0xff41d2d9, 0x004911ac,1835	0x005dd9e3, 0xff4c7d80, 0x0052103e,1836	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,1837	0xffc4b414, 0xff68582c, 0x006b38e5,1838	0xffabb861, 0xff704bec, 0x0074de52,1839	0xffa19f4c, 0xff729059, 0x007c7e90,1840	0x00000001//output gain1841};1842 1843static u32 coef_48to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {1844	0x000c6102,//header1845	0x0001d029,//input gain1846	0x00f2a98b, 0xff92aa71, 0x001fcd16,1847	0x00ae9004, 0xffb85140, 0x0041813a,1848	0x007f8ed1, 0xffd585fc, 0x006a69e6,1849	0x00000002,//output gain1850	0x001b6103,//header1851	0x000001e0,//input gain1852	0x00de44c0, 0xff380b7f, 0x004ffc73,1853	0x00494b44, 0xff3d493a, 0x005908bf,1854	0xffe9a3c8, 0xff425647, 0x006745f7,1855	0xffc42d61, 0xff40a6c7, 0x00776709,1856	0x00000002,//output gain1857	0x00265204,//farrow1858	0x000aaaab,1859	0xffaaaaab,1860	0xfffaaaab,1861	0x00555555,1862	0xff600000,1863	0xfff55555,1864	0x00155555,1865	0x00055555,1866	0xffeaaaab,1867	0x00200000,1868	0x00005102,//header1869	0x0001d727,//input gain1870	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1871	0x00e55557, 0xffcadd5b, 0x003d80ba,1872	0x00d13397, 0xfff232f8, 0x00683337,1873	0x00000001//output gain1874};1875 1876static u32 coef_48to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {1877	0x000c6102,//header1878	0x0001d727,//input gain1879	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1880	0x00e55557, 0xffcadd5b, 0x003d80ba,1881	0x00d13397, 0xfff232f8, 0x00683337,1882	0x00000002,//output gain1883	0x00186102,//header1884	0x000013d9,//input gain1885	0x00ebd477, 0xff4ce383, 0x0042049d,1886	0x0089c278, 0xff54414d, 0x00531ded,1887	0x004a5e07, 0xff53cf41, 0x006efbdc,1888	0x00000002,//output gain1889	0x00230204,//farrow1890	0x000aaaab,1891	0xffaaaaab,1892	0xfffaaaab,1893	0x00555555,1894	0xff600000,1895	0xfff55555,1896	0x00155555,1897	0x00055555,1898	0xffeaaaab,1899	0x00200000,1900	0x00005102,//header1901	0x00001685,//input gain1902	0x00f53ae9, 0xff52f196, 0x003e3e08,1903	0x00b9f857, 0xff5d8985, 0x0050070a,1904	0x008c3e86, 0xff6053f0, 0x006d98ef,1905	0x00000001//output gain1906};1907 1908static u32 coef_48to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {1909	0x00006102,//header1910	0x0001d727,//input gain1911	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1912	0x00e55557, 0xffcadd5b, 0x003d80ba,1913	0x00d13397, 0xfff232f8, 0x00683337,1914	0x00000002//output gain1915};1916 1917static u32 coef_48to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {1918	0x000c6102,//header1919	0x0001d727,//input gain1920	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1921	0x00e55557, 0xffcadd5b, 0x003d80ba,1922	0x00d13397, 0xfff232f8, 0x00683337,1923	0x00000002,//output gain1924	0x00186102,//header1925	0x000013d9,//input gain1926	0x00ebd477, 0xff4ce383, 0x0042049d,1927	0x0089c278, 0xff54414d, 0x00531ded,1928	0x004a5e07, 0xff53cf41, 0x006efbdc,1929	0x00000002,//output gain1930	0x00246102,//header1931	0x0000010a,//input gain1932	0x00c93dc4, 0xff26f5f6, 0x005d1041,1933	0x001002c4, 0xff245b76, 0x00666002,1934	0xffc30a45, 0xff1baecd, 0x00765921,1935	0x00000002,//output gain1936	0x002f0204,//farrow1937	0x000aaaab,1938	0xffaaaaab,1939	0xfffaaaab,1940	0x00555555,1941	0xff600000,1942	0xfff55555,1943	0x00155555,1944	0x00055555,1945	0xffeaaaab,1946	0x00200000,1947	0x00005102,//header1948	0x00000138,//input gain1949	0x00d5d232, 0xff2a3bf8, 0x005a785c,1950	0x0034001b, 0xff283109, 0x006462a6,1951	0xffe6746a, 0xff1fb09c, 0x00758a91,1952	0x00000001//output gain1953};1954 1955static u32 coef_48to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {1956	0x000c6102,//header1957	0x0001d727,//input gain1958	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1959	0x00e55557, 0xffcadd5b, 0x003d80ba,1960	0x00d13397, 0xfff232f8, 0x00683337,1961	0x00000002,//output gain1962	0x00006102,//header1963	0x000013d9,//input gain1964	0x00ebd477, 0xff4ce383, 0x0042049d,1965	0x0089c278, 0xff54414d, 0x00531ded,1966	0x004a5e07, 0xff53cf41, 0x006efbdc,1967	0x00000002//output gain1968};1969 1970static u32 coef_88to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {1971	0x000c0102,//header1972	0x00000057,//input gain1973	0x00a8e717, 0xff1c748d, 0x0065b976,1974	0xffcbccab, 0xff190aff, 0x006cc1cf,1975	0xff871ce1, 0xff10d878, 0x0078cfc5,1976	0x00000001,//output gain1977	0x00179204,//farrow1978	0x000aaaab,1979	0xffaaaaab,1980	0xfffaaaab,1981	0x00555555,1982	0xff600000,1983	0xfff55555,1984	0x00155555,1985	0x00055555,1986	0xffeaaaab,1987	0x00200000,1988	0x00235102,//header1989	0x000013d9,//input gain1990	0x00ebd477, 0xff4ce383, 0x0042049d,1991	0x0089c278, 0xff54414d, 0x00531ded,1992	0x004a5e07, 0xff53cf41, 0x006efbdc,1993	0x00000001,//output gain1994	0x00005102,//header1995	0x0001d727,//input gain1996	0x00fc2fc7, 0xff9bb27b, 0x001c564c,1997	0x00e55557, 0xffcadd5b, 0x003d80ba,1998	0x00d13397, 0xfff232f8, 0x00683337,1999	0x00000001//output gain2000};2001 2002static u32 coef_88to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {2003	0x000c5102,//header2004	0x0000010a,//input gain2005	0x00c93dc4, 0xff26f5f6, 0x005d1041,2006	0x001002c4, 0xff245b76, 0x00666002,2007	0xffc30a45, 0xff1baecd, 0x00765921,2008	0x00000001,//output gain2009	0x00185102,//header2010	0x000013d9,//input gain2011	0x00ebd477, 0xff4ce383, 0x0042049d,2012	0x0089c278, 0xff54414d, 0x00531ded,2013	0x004a5e07, 0xff53cf41, 0x006efbdc,2014	0x00000001,//output gain2015	0x00005102,//header2016	0x0001d727,//input gain2017	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2018	0x00e55557, 0xffcadd5b, 0x003d80ba,2019	0x00d13397, 0xfff232f8, 0x00683337,2020	0x00000001//output gain2021};2022 2023static u32 coef_88to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {2024	0x000c0102,//header2025	0x000005f3,//input gain2026	0x00d816d6, 0xff385383, 0x004fe566,2027	0x003c548d, 0xff38c23d, 0x005d0b1c,2028	0xfff02f7d, 0xff31e983, 0x0072d65d,2029	0x00000001,//output gain2030	0x00179204,//farrow2031	0x000aaaab,2032	0xffaaaaab,2033	0xfffaaaab,2034	0x00555555,2035	0xff600000,2036	0xfff55555,2037	0x00155555,2038	0x00055555,2039	0xffeaaaab,2040	0x00200000,2041	0x00005102,//header2042	0x0001d727,//input gain2043	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2044	0x00e55557, 0xffcadd5b, 0x003d80ba,2045	0x00d13397, 0xfff232f8, 0x00683337,2046	0x00000001//output gain2047};2048 2049static u32 coef_88to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {2050	0x000c5102,//header2051	0x000013d9,//input gain2052	0x00ebd477, 0xff4ce383, 0x0042049d,2053	0x0089c278, 0xff54414d, 0x00531ded,2054	0x004a5e07, 0xff53cf41, 0x006efbdc,2055	0x00000001,//output gain2056	0x00005102,//header2057	0x0001d727,//input gain2058	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2059	0x00e55557, 0xffcadd5b, 0x003d80ba,2060	0x00d13397, 0xfff232f8, 0x00683337,2061	0x00000001//output gain2062};2063 2064static u32 coef_88to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {2065	0x000c0102,//header2066	0x00001685,//input gain2067	0x00f53ae9, 0xff52f196, 0x003e3e08,2068	0x00b9f857, 0xff5d8985, 0x0050070a,2069	0x008c3e86, 0xff6053f0, 0x006d98ef,2070	0x00000001,//output gain2071	0x00175204,//farrow2072	0x000aaaab,2073	0xffaaaaab,2074	0xfffaaaab,2075	0x00555555,2076	0xff600000,2077	0xfff55555,2078	0x00155555,2079	0x00055555,2080	0xffeaaaab,2081	0x00200000,2082	0x00005102,//header2083	0x0001d727,//input gain2084	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2085	0x00e55557, 0xffcadd5b, 0x003d80ba,2086	0x00d13397, 0xfff232f8, 0x00683337,2087	0x00000001//output gain2088};2089 2090static u32 coef_88to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {2091	0x000c6102,//header2092	0x000005f3,//input gain2093	0x00d816d6, 0xff385383, 0x004fe566,2094	0x003c548d, 0xff38c23d, 0x005d0b1c,2095	0xfff02f7d, 0xff31e983, 0x0072d65d,2096	0x00000002,//output gain2097	0x00179204,//farrow2098	0x000aaaab,2099	0xffaaaaab,2100	0xfffaaaab,2101	0x00555555,2102	0xff600000,2103	0xfff55555,2104	0x00155555,2105	0x00055555,2106	0xffeaaaab,2107	0x00200000,2108	0x00005102,//header2109	0x0001d727,//input gain2110	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2111	0x00e55557, 0xffcadd5b, 0x003d80ba,2112	0x00d13397, 0xfff232f8, 0x00683337,2113	0x00000001//output gain2114};2115 2116static u32 coef_88to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {2117	0x00005102,//header2118	0x0001d727,//input gain2119	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2120	0x00e55557, 0xffcadd5b, 0x003d80ba,2121	0x00d13397, 0xfff232f8, 0x00683337,2122	0x00000001//output gain2123};2124 2125static u32 coef_88to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {2126	0x000c6102,//header2127	0x00001685,//input gain2128	0x00f53ae9, 0xff52f196, 0x003e3e08,2129	0x00b9f857, 0xff5d8985, 0x0050070a,2130	0x008c3e86, 0xff6053f0, 0x006d98ef,2131	0x00000002,//output gain2132	0x00175204,//farrow2133	0x000aaaab,2134	0xffaaaaab,2135	0xfffaaaab,2136	0x00555555,2137	0xff600000,2138	0xfff55555,2139	0x00155555,2140	0x00055555,2141	0xffeaaaab,2142	0x00200000,2143	0x00005102,//header2144	0x0001d727,//input gain2145	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2146	0x00e55557, 0xffcadd5b, 0x003d80ba,2147	0x00d13397, 0xfff232f8, 0x00683337,2148	0x00000001//output gain2149};2150 2151static u32 coef_88to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {2152	0x000c6102,//header2153	0x000013d9,//input gain2154	0x00ebd477, 0xff4ce383, 0x0042049d,2155	0x0089c278, 0xff54414d, 0x00531ded,2156	0x004a5e07, 0xff53cf41, 0x006efbdc,2157	0x00000002,//output gain2158	0x00005204,//farrow2159	0x000aaaab,2160	0xffaaaaab,2161	0xfffaaaab,2162	0x00555555,2163	0xff600000,2164	0xfff55555,2165	0x00155555,2166	0x00055555,2167	0xffeaaaab,2168	0x002000002169};2170 2171static u32 coef_88to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {2172	0x00006102,//header2173	0x000013d9,//input gain2174	0x00ebd477, 0xff4ce383, 0x0042049d,2175	0x0089c278, 0xff54414d, 0x00531ded,2176	0x004a5e07, 0xff53cf41, 0x006efbdc,2177	0x00000002//output gain2178};2179 2180static u32 coef_88to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {2181	0x000c6102,//header2182	0x000013d9,//input gain2183	0x00ebd477, 0xff4ce383, 0x0042049d,2184	0x0089c278, 0xff54414d, 0x00531ded,2185	0x004a5e07, 0xff53cf41, 0x006efbdc,2186	0x00000002,//output gain2187	0x00186102,//header2188	0x0000010a,//input gain2189	0x00c93dc4, 0xff26f5f6, 0x005d1041,2190	0x001002c4, 0xff245b76, 0x00666002,2191	0xffc30a45, 0xff1baecd, 0x00765921,2192	0x00000002,//output gain2193	0x00005204,//farrow2194	0x000aaaab,2195	0xffaaaaab,2196	0xfffaaaab,2197	0x00555555,2198	0xff600000,2199	0xfff55555,2200	0x00155555,2201	0x00055555,2202	0xffeaaaab,2203	0x002000002204};2205 2206static u32 coef_96to8[TEGRA210_SFC_COEF_RAM_DEPTH] = {2207	0x000c9102,//header2208	0x0000007d,//input gain2209	0x007d1f20, 0xff1a540e, 0x00678bf9,2210	0xff916625, 0xff16b0ff, 0x006e433a,2211	0xff5af660, 0xff0eb91f, 0x00797356,2212	0x00000001,//output gain2213	0x00185102,//header2214	0x000013d9,//input gain2215	0x00ebd477, 0xff4ce383, 0x0042049d,2216	0x0089c278, 0xff54414d, 0x00531ded,2217	0x004a5e07, 0xff53cf41, 0x006efbdc,2218	0x00000001,//output gain2219	0x00005102,//header2220	0x0001d727,//input gain2221	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2222	0x00e55557, 0xffcadd5b, 0x003d80ba,2223	0x00d13397, 0xfff232f8, 0x00683337,2224	0x00000001//output gain2225};2226 2227static u32 coef_96to11[TEGRA210_SFC_COEF_RAM_DEPTH] = {2228	0x000c0102,//header2229	0x000000af,//input gain2230	0x00c65663, 0xff23d2ce, 0x005f97d6,2231	0x00086ad6, 0xff20ec4f, 0x00683201,2232	0xffbbbef6, 0xff184447, 0x00770963,2233	0x00000001,//output gain2234	0x00175204,//farrow2235	0x000aaaab,2236	0xffaaaaab,2237	0xfffaaaab,2238	0x00555555,2239	0xff600000,2240	0xfff55555,2241	0x00155555,2242	0x00055555,2243	0xffeaaaab,2244	0x00200000,2245	0x00235102,//header2246	0x000013d9,//input gain2247	0x00ebd477, 0xff4ce383, 0x0042049d,2248	0x0089c278, 0xff54414d, 0x00531ded,2249	0x004a5e07, 0xff53cf41, 0x006efbdc,2250	0x00000001,//output gain2251	0x00005102,//header2252	0x0001d727,//input gain2253	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2254	0x00e55557, 0xffcadd5b, 0x003d80ba,2255	0x00d13397, 0xfff232f8, 0x00683337,2256	0x00000001//output gain2257};2258 2259static u32 coef_96to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {2260	0x000c9102,//header2261	0x000005d6,//input gain2262	0x00c6543e, 0xff342935, 0x0052f116,2263	0x000a1d78, 0xff3330c0, 0x005f88a3,2264	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,2265	0x00000001,//output gain2266	0x00005102,//header2267	0x0001d727,//input gain2268	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2269	0x00e55557, 0xffcadd5b, 0x003d80ba,2270	0x00d13397, 0xfff232f8, 0x00683337,2271	0x00000001//output gain2272};2273 2274static u32 coef_96to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {2275	0x000c6102,//header2276	0x000000af,//input gain2277	0x00c65663, 0xff23d2ce, 0x005f97d6,2278	0x00086ad6, 0xff20ec4f, 0x00683201,2279	0xffbbbef6, 0xff184447, 0x00770963,2280	0x00000002,//output gain2281	0x00175204,//farrow2282	0x000aaaab,2283	0xffaaaaab,2284	0xfffaaaab,2285	0x00555555,2286	0xff600000,2287	0xfff55555,2288	0x00155555,2289	0x00055555,2290	0xffeaaaab,2291	0x00200000,2292	0x00235102,//header2293	0x000013d9,//input gain2294	0x00ebd477, 0xff4ce383, 0x0042049d,2295	0x0089c278, 0xff54414d, 0x00531ded,2296	0x004a5e07, 0xff53cf41, 0x006efbdc,2297	0x00000001,//output gain2298	0x00005102,//header2299	0x0001d727,//input gain2300	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2301	0x00e55557, 0xffcadd5b, 0x003d80ba,2302	0x00d13397, 0xfff232f8, 0x00683337,2303	0x00000001//output gain2304};2305 2306static u32 coef_96to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {2307	0x000c5102,//header2308	0x000013d9,//input gain2309	0x00ebd477, 0xff4ce383, 0x0042049d,2310	0x0089c278, 0xff54414d, 0x00531ded,2311	0x004a5e07, 0xff53cf41, 0x006efbdc,2312	0x00000001,//output gain2313	0x00005102,//header2314	0x0001d727,//input gain2315	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2316	0x00e55557, 0xffcadd5b, 0x003d80ba,2317	0x00d13397, 0xfff232f8, 0x00683337,2318	0x00000001//output gain2319};2320 2321static u32 coef_96to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {2322	0x00009105,//header2323	0x00000292,//input gain2324	0x00e4320a, 0xff41d2d9, 0x004911ac,2325	0x005dd9e3, 0xff4c7d80, 0x0052103e,2326	0xfff8ebef, 0xff5b6fab, 0x005f0a0d,2327	0xffc4b414, 0xff68582c, 0x006b38e5,2328	0xffabb861, 0xff704bec, 0x0074de52,2329	0xffa19f4c, 0xff729059, 0x007c7e90,2330	0x00000001//output gain2331};2332 2333static u32 coef_96to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {2334	0x000f6103,//header2335	0x000001e0,//input gain2336	0x00de44c0, 0xff380b7f, 0x004ffc73,2337	0x00494b44, 0xff3d493a, 0x005908bf,2338	0xffe9a3c8, 0xff425647, 0x006745f7,2339	0xffc42d61, 0xff40a6c7, 0x00776709,2340	0x00000002,//output gain2341	0x001a5204,//farrow2342	0x000aaaab,2343	0xffaaaaab,2344	0xfffaaaab,2345	0x00555555,2346	0xff600000,2347	0xfff55555,2348	0x00155555,2349	0x00055555,2350	0xffeaaaab,2351	0x00200000,2352	0x00005102,//header2353	0x0001d727,//input gain2354	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2355	0x00e55557, 0xffcadd5b, 0x003d80ba,2356	0x00d13397, 0xfff232f8, 0x00683337,2357	0x00000001//output gain2358};2359 2360static u32 coef_96to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {2361	0x00005102,//header2362	0x0001d727,//input gain2363	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2364	0x00e55557, 0xffcadd5b, 0x003d80ba,2365	0x00d13397, 0xfff232f8, 0x00683337,2366	0x00000001//output gain2367};2368 2369static u32 coef_96to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {2370	0x000f6103,//header2371	0x000001e0,//input gain2372	0x00de44c0, 0xff380b7f, 0x004ffc73,2373	0x00494b44, 0xff3d493a, 0x005908bf,2374	0xffe9a3c8, 0xff425647, 0x006745f7,2375	0xffc42d61, 0xff40a6c7, 0x00776709,2376	0x00000002,//output gain2377	0x001a0204,//farrow2378	0x000aaaab,2379	0xffaaaaab,2380	0xfffaaaab,2381	0x00555555,2382	0xff600000,2383	0xfff55555,2384	0x00155555,2385	0x00055555,2386	0xffeaaaab,2387	0x00200000,2388	0x00005102,//header2389	0x000013d9,//input gain2390	0x00ebd477, 0xff4ce383, 0x0042049d,2391	0x0089c278, 0xff54414d, 0x00531ded,2392	0x004a5e07, 0xff53cf41, 0x006efbdc,2393	0x00000001//output gain2394};2395 2396static u32 coef_96to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {2397	0x000f6103,//header2398	0x000001e0,//input gain2399	0x00de44c0, 0xff380b7f, 0x004ffc73,2400	0x00494b44, 0xff3d493a, 0x005908bf,2401	0xffe9a3c8, 0xff425647, 0x006745f7,2402	0xffc42d61, 0xff40a6c7, 0x00776709,2403	0x00000002,//output gain2404	0x001b6102,//header2405	0x000000af,//input gain2406	0x00c65663, 0xff23d2ce, 0x005f97d6,2407	0x00086ad6, 0xff20ec4f, 0x00683201,2408	0xffbbbef6, 0xff184447, 0x00770963,2409	0x00000002,//output gain2410	0x00260204,//farrow2411	0x000aaaab,2412	0xffaaaaab,2413	0xfffaaaab,2414	0x00555555,2415	0xff600000,2416	0xfff55555,2417	0x00155555,2418	0x00055555,2419	0xffeaaaab,2420	0x00200000,2421	0x00005102,//header2422	0x0000010a,//input gain2423	0x00c93dc4, 0xff26f5f6, 0x005d1041,2424	0x001002c4, 0xff245b76, 0x00666002,2425	0xffc30a45, 0xff1baecd, 0x00765921,2426	0x00000001//output gain2427};2428 2429static u32 coef_96to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {2430	0x00006103,//header2431	0x000001e0,//input gain2432	0x00de44c0, 0xff380b7f, 0x004ffc73,2433	0x00494b44, 0xff3d493a, 0x005908bf,2434	0xffe9a3c8, 0xff425647, 0x006745f7,2435	0xffc42d61, 0xff40a6c7, 0x00776709,2436	0x00000002//output gain2437};2438 2439static u32 coef_176to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {2440	0x000c0102,//header2441	0x00000057,//input gain2442	0x00a8e717, 0xff1c748d, 0x0065b976,2443	0xffcbccab, 0xff190aff, 0x006cc1cf,2444	0xff871ce1, 0xff10d878, 0x0078cfc5,2445	0x00000001,//output gain2446	0x00179204,//farrow2447	0x000aaaab,2448	0xffaaaaab,2449	0xfffaaaab,2450	0x00555555,2451	0xff600000,2452	0xfff55555,2453	0x00155555,2454	0x00055555,2455	0xffeaaaab,2456	0x00200000,2457	0x00235102,//header2458	0x000013d9,//input gain2459	0x00ebd477, 0xff4ce383, 0x0042049d,2460	0x0089c278, 0xff54414d, 0x00531ded,2461	0x004a5e07, 0xff53cf41, 0x006efbdc,2462	0x00000001,//output gain2463	0x00005102,//header2464	0x0001d727,//input gain2465	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2466	0x00e55557, 0xffcadd5b, 0x003d80ba,2467	0x00d13397, 0xfff232f8, 0x00683337,2468	0x00000001//output gain2469};2470 2471static u32 coef_176to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {2472	0x000c5102,//header2473	0x0000010a,//input gain2474	0x00c93dc4, 0xff26f5f6, 0x005d1041,2475	0x001002c4, 0xff245b76, 0x00666002,2476	0xffc30a45, 0xff1baecd, 0x00765921,2477	0x00000001,//output gain2478	0x00185102,//header2479	0x000013d9,//input gain2480	0x00ebd477, 0xff4ce383, 0x0042049d,2481	0x0089c278, 0xff54414d, 0x00531ded,2482	0x004a5e07, 0xff53cf41, 0x006efbdc,2483	0x00000001,//output gain2484	0x00005102,//header2485	0x0001d727,//input gain2486	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2487	0x00e55557, 0xffcadd5b, 0x003d80ba,2488	0x00d13397, 0xfff232f8, 0x00683337,2489	0x00000001//output gain2490};2491 2492static u32 coef_176to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {2493	0x000c0102,//header2494	0x00000138,//input gain2495	0x00d5d232, 0xff2a3bf8, 0x005a785c,2496	0x0034001b, 0xff283109, 0x006462a6,2497	0xffe6746a, 0xff1fb09c, 0x00758a91,2498	0x00000001,//output gain2499	0x00175204,//farrow2500	0x000aaaab,2501	0xffaaaaab,2502	0xfffaaaab,2503	0x00555555,2504	0xff600000,2505	0xfff55555,2506	0x00155555,2507	0x00055555,2508	0xffeaaaab,2509	0x00200000,2510	0x00235102,//header2511	0x000013d9,//input gain2512	0x00ebd477, 0xff4ce383, 0x0042049d,2513	0x0089c278, 0xff54414d, 0x00531ded,2514	0x004a5e07, 0xff53cf41, 0x006efbdc,2515	0x00000001,//output gain2516	0x00005102,//header2517	0x0001d727,//input gain2518	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2519	0x00e55557, 0xffcadd5b, 0x003d80ba,2520	0x00d13397, 0xfff232f8, 0x00683337,2521	0x00000001//output gain2522};2523 2524static u32 coef_176to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {2525	0x000c0102,//header2526	0x000005f3,//input gain2527	0x00d816d6, 0xff385383, 0x004fe566,2528	0x003c548d, 0xff38c23d, 0x005d0b1c,2529	0xfff02f7d, 0xff31e983, 0x0072d65d,2530	0x00000001,//output gain2531	0x00179204,//farrow2532	0x000aaaab,2533	0xffaaaaab,2534	0xfffaaaab,2535	0x00555555,2536	0xff600000,2537	0xfff55555,2538	0x00155555,2539	0x00055555,2540	0xffeaaaab,2541	0x00200000,2542	0x00005102,//header2543	0x0001d727,//input gain2544	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2545	0x00e55557, 0xffcadd5b, 0x003d80ba,2546	0x00d13397, 0xfff232f8, 0x00683337,2547	0x00000001//output gain2548};2549 2550static u32 coef_176to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {2551	0x000c5102,//header2552	0x000013d9,//input gain2553	0x00ebd477, 0xff4ce383, 0x0042049d,2554	0x0089c278, 0xff54414d, 0x00531ded,2555	0x004a5e07, 0xff53cf41, 0x006efbdc,2556	0x00000001,//output gain2557	0x00005102,//header2558	0x0001d727,//input gain2559	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2560	0x00e55557, 0xffcadd5b, 0x003d80ba,2561	0x00d13397, 0xfff232f8, 0x00683337,2562	0x00000001//output gain2563};2564 2565static u32 coef_176to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {2566	0x000c0102,//header2567	0x00001685,//input gain2568	0x00f53ae9, 0xff52f196, 0x003e3e08,2569	0x00b9f857, 0xff5d8985, 0x0050070a,2570	0x008c3e86, 0xff6053f0, 0x006d98ef,2571	0x00000001,//output gain2572	0x00175204,//farrow2573	0x000aaaab,2574	0xffaaaaab,2575	0xfffaaaab,2576	0x00555555,2577	0xff600000,2578	0xfff55555,2579	0x00155555,2580	0x00055555,2581	0xffeaaaab,2582	0x00200000,2583	0x00005102,//header2584	0x0001d727,//input gain2585	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2586	0x00e55557, 0xffcadd5b, 0x003d80ba,2587	0x00d13397, 0xfff232f8, 0x00683337,2588	0x00000001//output gain2589};2590 2591static u32 coef_176to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {2592	0x00005102,//header2593	0x000013d9,//input gain2594	0x00ebd477, 0xff4ce383, 0x0042049d,2595	0x0089c278, 0xff54414d, 0x00531ded,2596	0x004a5e07, 0xff53cf41, 0x006efbdc,2597	0x00000001//output gain2598};2599 2600static u32 coef_176to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {2601	0x000c6102,//header2602	0x0000010a,//input gain2603	0x00c93dc4, 0xff26f5f6, 0x005d1041,2604	0x001002c4, 0xff245b76, 0x00666002,2605	0xffc30a45, 0xff1baecd, 0x00765921,2606	0x00000002,//output gain2607	0x00175204,//farrow2608	0x000aaaab,2609	0xffaaaaab,2610	0xfffaaaab,2611	0x00555555,2612	0xff600000,2613	0xfff55555,2614	0x00155555,2615	0x00055555,2616	0xffeaaaab,2617	0x00200000,2618	0x00005103,//header2619	0x000001e0,//input gain2620	0x00de44c0, 0xff380b7f, 0x004ffc73,2621	0x00494b44, 0xff3d493a, 0x005908bf,2622	0xffe9a3c8, 0xff425647, 0x006745f7,2623	0xffc42d61, 0xff40a6c7, 0x00776709,2624	0x00000001//output gain2625};2626 2627static u32 coef_176to192[TEGRA210_SFC_COEF_RAM_DEPTH] = {2628	0x000c6102,//header2629	0x0000010a,//input gain2630	0x00c93dc4, 0xff26f5f6, 0x005d1041,2631	0x001002c4, 0xff245b76, 0x00666002,2632	0xffc30a45, 0xff1baecd, 0x00765921,2633	0x00000002,//output gain2634	0x00005204,//farrow2635	0x000aaaab,2636	0xffaaaaab,2637	0xfffaaaab,2638	0x00555555,2639	0xff600000,2640	0xfff55555,2641	0x00155555,2642	0x00055555,2643	0xffeaaaab,2644	0x002000002645};2646 2647static u32 coef_192to16[TEGRA210_SFC_COEF_RAM_DEPTH] = {2648	0x000c9102,//header2649	0x0000007d,//input gain2650	0x007d1f20, 0xff1a540e, 0x00678bf9,2651	0xff916625, 0xff16b0ff, 0x006e433a,2652	0xff5af660, 0xff0eb91f, 0x00797356,2653	0x00000001,//output gain2654	0x00185102,//header2655	0x000013d9,//input gain2656	0x00ebd477, 0xff4ce383, 0x0042049d,2657	0x0089c278, 0xff54414d, 0x00531ded,2658	0x004a5e07, 0xff53cf41, 0x006efbdc,2659	0x00000001,//output gain2660	0x00005102,//header2661	0x0001d727,//input gain2662	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2663	0x00e55557, 0xffcadd5b, 0x003d80ba,2664	0x00d13397, 0xfff232f8, 0x00683337,2665	0x00000001//output gain2666};2667 2668static u32 coef_192to22[TEGRA210_SFC_COEF_RAM_DEPTH] = {2669	0x000c0102,//header2670	0x000000af,//input gain2671	0x00c65663, 0xff23d2ce, 0x005f97d6,2672	0x00086ad6, 0xff20ec4f, 0x00683201,2673	0xffbbbef6, 0xff184447, 0x00770963,2674	0x00000001,//output gain2675	0x00175204,//farrow2676	0x000aaaab,2677	0xffaaaaab,2678	0xfffaaaab,2679	0x00555555,2680	0xff600000,2681	0xfff55555,2682	0x00155555,2683	0x00055555,2684	0xffeaaaab,2685	0x00200000,2686	0x00235102,//header2687	0x000013d9,//input gain2688	0x00ebd477, 0xff4ce383, 0x0042049d,2689	0x0089c278, 0xff54414d, 0x00531ded,2690	0x004a5e07, 0xff53cf41, 0x006efbdc,2691	0x00000001,//output gain2692	0x00005102,//header2693	0x0001d727,//input gain2694	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2695	0x00e55557, 0xffcadd5b, 0x003d80ba,2696	0x00d13397, 0xfff232f8, 0x00683337,2697	0x00000001//output gain2698};2699 2700static u32 coef_192to24[TEGRA210_SFC_COEF_RAM_DEPTH] = {2701	0x000c5102,//header2702	0x0000010a,//input gain2703	0x00c93dc4, 0xff26f5f6, 0x005d1041,2704	0x001002c4, 0xff245b76, 0x00666002,2705	0xffc30a45, 0xff1baecd, 0x00765921,2706	0x00000001,//output gain2707	0x00185102,//header2708	0x000013d9,//input gain2709	0x00ebd477, 0xff4ce383, 0x0042049d,2710	0x0089c278, 0xff54414d, 0x00531ded,2711	0x004a5e07, 0xff53cf41, 0x006efbdc,2712	0x00000001,//output gain2713	0x00005102,//header2714	0x0001d727,//input gain2715	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2716	0x00e55557, 0xffcadd5b, 0x003d80ba,2717	0x00d13397, 0xfff232f8, 0x00683337,2718	0x00000001//output gain2719};2720 2721static u32 coef_192to32[TEGRA210_SFC_COEF_RAM_DEPTH] = {2722	0x000c9102,//header2723	0x000005d6,//input gain2724	0x00c6543e, 0xff342935, 0x0052f116,2725	0x000a1d78, 0xff3330c0, 0x005f88a3,2726	0xffbee7c0, 0xff2b5ba5, 0x0073eb26,2727	0x00000001,//output gain2728	0x00005102,//header2729	0x0001d727,//input gain2730	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2731	0x00e55557, 0xffcadd5b, 0x003d80ba,2732	0x00d13397, 0xfff232f8, 0x00683337,2733	0x00000001//output gain2734};2735 2736static u32 coef_192to44[TEGRA210_SFC_COEF_RAM_DEPTH] = {2737	0x000c6102,//header2738	0x000000af,//input gain2739	0x00c65663, 0xff23d2ce, 0x005f97d6,2740	0x00086ad6, 0xff20ec4f, 0x00683201,2741	0xffbbbef6, 0xff184447, 0x00770963,2742	0x00000002,//output gain2743	0x00175204,//farrow2744	0x000aaaab,2745	0xffaaaaab,2746	0xfffaaaab,2747	0x00555555,2748	0xff600000,2749	0xfff55555,2750	0x00155555,2751	0x00055555,2752	0xffeaaaab,2753	0x00200000,2754	0x00235102,//header2755	0x000013d9,//input gain2756	0x00ebd477, 0xff4ce383, 0x0042049d,2757	0x0089c278, 0xff54414d, 0x00531ded,2758	0x004a5e07, 0xff53cf41, 0x006efbdc,2759	0x00000001,//output gain2760	0x00005102,//header2761	0x0001d727,//input gain2762	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2763	0x00e55557, 0xffcadd5b, 0x003d80ba,2764	0x00d13397, 0xfff232f8, 0x00683337,2765	0x00000001//output gain2766};2767 2768static u32 coef_192to48[TEGRA210_SFC_COEF_RAM_DEPTH] = {2769	0x000c5102,//header2770	0x000013d9,//input gain2771	0x00ebd477, 0xff4ce383, 0x0042049d,2772	0x0089c278, 0xff54414d, 0x00531ded,2773	0x004a5e07, 0xff53cf41, 0x006efbdc,2774	0x00000001,//output gain2775	0x00005102,//header2776	0x0001d727,//input gain2777	0x00fc2fc7, 0xff9bb27b, 0x001c564c,2778	0x00e55557, 0xffcadd5b, 0x003d80ba,2779	0x00d13397, 0xfff232f8, 0x00683337,2780	0x00000001//output gain2781};2782 2783static u32 coef_192to88[TEGRA210_SFC_COEF_RAM_DEPTH] = {2784	0x000c6102,//header2785	0x000000af,//input gain2786	0x00c65663, 0xff23d2ce, 0x005f97d6,2787	0x00086ad6, 0xff20ec4f, 0x00683201,2788	0xffbbbef6, 0xff184447, 0x00770963,2789	0x00000002,//output gain2790	0x00175204,//farrow2791	0x000aaaab,2792	0xffaaaaab,2793	0xfffaaaab,2794	0x00555555,2795	0xff600000,2796	0xfff55555,2797	0x00155555,2798	0x00055555,2799	0xffeaaaab,2800	0x00200000,2801	0x00005102,//header2802	0x000013d9,//input gain2803	0x00ebd477, 0xff4ce383, 0x0042049d,2804	0x0089c278, 0xff54414d, 0x00531ded,2805	0x004a5e07, 0xff53cf41, 0x006efbdc,2806	0x00000001//output gain2807};2808 2809static u32 coef_192to96[TEGRA210_SFC_COEF_RAM_DEPTH] = {2810	0x00005103,//header2811	0x000001e0,//input gain2812	0x00de44c0, 0xff380b7f, 0x004ffc73,2813	0x00494b44, 0xff3d493a, 0x005908bf,2814	0xffe9a3c8, 0xff425647, 0x006745f7,2815	0xffc42d61, 0xff40a6c7, 0x00776709,2816	0x00000001//output gain2817};2818 2819static u32 coef_192to176[TEGRA210_SFC_COEF_RAM_DEPTH] = {2820	0x000c6102,//header2821	0x000000af,//input gain2822	0x00c65663, 0xff23d2ce, 0x005f97d6,2823	0x00086ad6, 0xff20ec4f, 0x00683201,2824	0xffbbbef6, 0xff184447, 0x00770963,2825	0x00000002,//output gain2826	0x00170204,//farrow2827	0x000aaaab,2828	0xffaaaaab,2829	0xfffaaaab,2830	0x00555555,2831	0xff600000,2832	0xfff55555,2833	0x00155555,2834	0x00055555,2835	0xffeaaaab,2836	0x00200000,2837	0x00005102,//header2838	0x0000010a,//input gain2839	0x00c93dc4, 0xff26f5f6, 0x005d1041,2840	0x001002c4, 0xff245b76, 0x00666002,2841	0xffc30a45, 0xff1baecd, 0x00765921,2842	0x00000001//output gain2843};2844 2845/*2846 * Coefficient table for various sample rate conversions. The sample2847 * rates available are as per tegra210_sfc_rates[].2848 */2849static s32 *coef_addr_table[TEGRA210_SFC_NUM_RATES][TEGRA210_SFC_NUM_RATES] = {2850	/* Convertions from 8 kHz */2851	{2852		BYPASS_CONV,2853		coef_8to11,2854		coef_8to16,2855		coef_8to22,2856		coef_8to24,2857		coef_8to32,2858		coef_8to44,2859		coef_8to48,2860		UNSUPP_CONV,2861		coef_8to88,2862		coef_8to96,2863		UNSUPP_CONV,2864		UNSUPP_CONV,2865	},2866	/* Convertions from 11.025 kHz */2867	{2868		coef_11to8,2869		BYPASS_CONV,2870		coef_11to16,2871		coef_11to22,2872		coef_11to24,2873		coef_11to32,2874		coef_11to44,2875		coef_11to48,2876		UNSUPP_CONV,2877		coef_11to88,2878		coef_11to96,2879		UNSUPP_CONV,2880		UNSUPP_CONV,2881	},2882	/* Convertions from 16 kHz */2883	{2884		coef_16to8,2885		coef_16to11,2886		BYPASS_CONV,2887		coef_16to22,2888		coef_16to24,2889		coef_16to32,2890		coef_16to44,2891		coef_16to48,2892		UNSUPP_CONV,2893		coef_16to88,2894		coef_16to96,2895		coef_16to176,2896		coef_16to192,2897	},2898	/* Convertions from 22.05 kHz */2899	{2900		coef_22to8,2901		coef_22to11,2902		coef_22to16,2903		BYPASS_CONV,2904		coef_22to24,2905		coef_22to32,2906		coef_22to44,2907		coef_22to48,2908		UNSUPP_CONV,2909		coef_22to88,2910		coef_22to96,2911		coef_22to176,2912		coef_22to192,2913	},2914	/* Convertions from 24 kHz */2915	{2916		coef_24to8,2917		coef_24to11,2918		coef_24to16,2919		coef_24to22,2920		BYPASS_CONV,2921		coef_24to32,2922		coef_24to44,2923		coef_24to48,2924		UNSUPP_CONV,2925		coef_24to88,2926		coef_24to96,2927		coef_24to176,2928		coef_24to192,2929	},2930	/* Convertions from 32 kHz */2931	{2932		coef_32to8,2933		coef_32to11,2934		coef_32to16,2935		coef_32to22,2936		coef_32to24,2937		BYPASS_CONV,2938		coef_32to44,2939		coef_32to48,2940		UNSUPP_CONV,2941		coef_32to88,2942		coef_32to96,2943		coef_32to176,2944		coef_32to192,2945	},2946	/* Convertions from 44.1 kHz */2947	{2948		coef_44to8,2949		coef_44to11,2950		coef_44to16,2951		coef_44to22,2952		coef_44to24,2953		coef_44to32,2954		BYPASS_CONV,2955		coef_44to48,2956		UNSUPP_CONV,2957		coef_44to88,2958		coef_44to96,2959		coef_44to176,2960		coef_44to192,2961	},2962	/* Convertions from 48 kHz */2963	{2964		coef_48to8,2965		coef_48to11,2966		coef_48to16,2967		coef_48to22,2968		coef_48to24,2969		coef_48to32,2970		coef_48to44,2971		BYPASS_CONV,2972		UNSUPP_CONV,2973		coef_48to88,2974		coef_48to96,2975		coef_48to176,2976		coef_48to192,2977	},2978	/* Convertions from 64 kHz */2979	{2980		UNSUPP_CONV,2981		UNSUPP_CONV,2982		UNSUPP_CONV,2983		UNSUPP_CONV,2984		UNSUPP_CONV,2985		UNSUPP_CONV,2986		UNSUPP_CONV,2987		UNSUPP_CONV,2988		UNSUPP_CONV,2989		UNSUPP_CONV,2990		UNSUPP_CONV,2991		UNSUPP_CONV,2992		UNSUPP_CONV,2993	},2994	/* Convertions from 88.2 kHz */2995	{2996		coef_88to8,2997		coef_88to11,2998		coef_88to16,2999		coef_88to22,3000		coef_88to24,3001		coef_88to32,3002		coef_88to44,3003		coef_88to48,3004		UNSUPP_CONV,3005		BYPASS_CONV,3006		coef_88to96,3007		coef_88to176,3008		coef_88to192,3009	},3010	/* Convertions from 96 kHz */3011	{	coef_96to8,3012		coef_96to11,3013		coef_96to16,3014		coef_96to22,3015		coef_96to24,3016		coef_96to32,3017		coef_96to44,3018		coef_96to48,3019		UNSUPP_CONV,3020		coef_96to88,3021		BYPASS_CONV,3022		coef_96to176,3023		coef_96to192,3024	},3025	/* Convertions from 176.4 kHz */3026	{3027		UNSUPP_CONV,3028		UNSUPP_CONV,3029		coef_176to16,3030		coef_176to22,3031		coef_176to24,3032		coef_176to32,3033		coef_176to44,3034		coef_176to48,3035		UNSUPP_CONV,3036		coef_176to88,3037		coef_176to96,3038		BYPASS_CONV,3039		coef_176to192,3040	},3041	/* Convertions from 192 kHz */3042	{3043		UNSUPP_CONV,3044		UNSUPP_CONV,3045		coef_192to16,3046		coef_192to22,3047		coef_192to24,3048		coef_192to32,3049		coef_192to44,3050		coef_192to48,3051		UNSUPP_CONV,3052		coef_192to88,3053		coef_192to96,3054		coef_192to176,3055		BYPASS_CONV,3056	},3057};3058 3059static int __maybe_unused tegra210_sfc_runtime_suspend(struct device *dev)3060{3061	struct tegra210_sfc *sfc = dev_get_drvdata(dev);3062 3063	regcache_cache_only(sfc->regmap, true);3064	regcache_mark_dirty(sfc->regmap);3065 3066	return 0;3067}3068 3069static int __maybe_unused tegra210_sfc_runtime_resume(struct device *dev)3070{3071	struct tegra210_sfc *sfc = dev_get_drvdata(dev);3072 3073	regcache_cache_only(sfc->regmap, false);3074	regcache_sync(sfc->regmap);3075 3076	return 0;3077}3078 3079static inline void tegra210_sfc_write_ram(struct regmap *regmap,3080					  s32 *data)3081{3082	int i;3083 3084	regmap_write(regmap, TEGRA210_SFC_CFG_RAM_CTRL,3085		     TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN |3086		     TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN |3087		     TEGRA210_SFC_RAM_CTRL_RW_WRITE);3088 3089	for (i = 0; i < TEGRA210_SFC_COEF_RAM_DEPTH; i++)3090		regmap_write(regmap, TEGRA210_SFC_CFG_RAM_DATA, data[i]);3091}3092 3093static int tegra210_sfc_write_coeff_ram(struct snd_soc_component *cmpnt)3094{3095	struct tegra210_sfc *sfc = dev_get_drvdata(cmpnt->dev);3096	s32 *coeff_ram;3097 3098	/* Bypass */3099	if (sfc->srate_in == sfc->srate_out)3100		return 0;3101 3102	coeff_ram = coef_addr_table[sfc->srate_in][sfc->srate_out];3103	if (IS_ERR_OR_NULL(coeff_ram)) {3104		dev_err(cmpnt->dev,3105			"Conversion from %d to %d Hz is not supported\n",3106			sfc->srate_in, sfc->srate_out);3107 3108		return PTR_ERR_OR_ZERO(coeff_ram);3109	}3110 3111	tegra210_sfc_write_ram(sfc->regmap, coeff_ram);3112 3113	regmap_update_bits(sfc->regmap,3114			   TEGRA210_SFC_COEF_RAM,3115			   TEGRA210_SFC_COEF_RAM_EN,3116			   TEGRA210_SFC_COEF_RAM_EN);3117 3118	return 0;3119}3120 3121static int tegra210_sfc_set_audio_cif(struct tegra210_sfc *sfc,3122				      struct snd_pcm_hw_params *params,3123				      unsigned int reg)3124{3125	unsigned int channels, audio_bits, path;3126	struct tegra_cif_conf cif_conf;3127 3128	memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));3129 3130	channels = params_channels(params);3131 3132	switch (params_format(params)) {3133	case SNDRV_PCM_FORMAT_S16_LE:3134		audio_bits = TEGRA_ACIF_BITS_16;3135		break;3136	case SNDRV_PCM_FORMAT_S32_LE:3137		audio_bits = TEGRA_ACIF_BITS_32;3138		break;3139	default:3140		return -EOPNOTSUPP;3141	}3142 3143	cif_conf.audio_ch = channels;3144	cif_conf.client_ch = channels;3145	cif_conf.audio_bits = audio_bits;3146	cif_conf.client_bits = TEGRA_ACIF_BITS_32;3147 3148	if (reg == TEGRA210_SFC_RX_CIF_CTRL)3149		path = SFC_RX_PATH;3150	else3151		path = SFC_TX_PATH;3152 3153	cif_conf.stereo_conv = sfc->stereo_to_mono[path];3154	cif_conf.mono_conv = sfc->mono_to_stereo[path];3155 3156	tegra_set_cif(sfc->regmap, reg, &cif_conf);3157 3158	return 0;3159}3160 3161static int tegra210_sfc_soft_reset(struct tegra210_sfc *sfc)3162{3163	u32 val;3164 3165	/*3166	 * Soft Reset: Below performs module soft reset which clears3167	 * all FSM logic, flushes flow control of FIFO and resets the3168	 * state register. It also brings module back to disabled3169	 * state (without flushing the data in the pipe).3170	 */3171	regmap_update_bits(sfc->regmap, TEGRA210_SFC_SOFT_RESET,3172			   TEGRA210_SFC_SOFT_RESET_EN, 1);3173 3174	return regmap_read_poll_timeout(sfc->regmap,3175					TEGRA210_SFC_SOFT_RESET,3176					val,3177					!(val & TEGRA210_SFC_SOFT_RESET_EN),3178					10, 10000);3179}3180 3181static int tegra210_sfc_rate_to_idx(struct device *dev, int rate,3182				    int *rate_idx)3183{3184	int i;3185 3186	for (i = 0; i < ARRAY_SIZE(tegra210_sfc_rates); i++) {3187		if (rate == tegra210_sfc_rates[i]) {3188			*rate_idx = i;3189 3190			return 0;3191		}3192	}3193 3194	dev_err(dev, "Sample rate %d Hz is not supported\n", rate);3195 3196	return -EOPNOTSUPP;3197}3198 3199static int tegra210_sfc_startup(struct snd_pcm_substream *substream,3200				struct snd_soc_dai *dai)3201{3202	struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);3203	int err;3204 3205	regmap_update_bits(sfc->regmap, TEGRA210_SFC_COEF_RAM,3206			   TEGRA210_SFC_COEF_RAM_EN, 0);3207 3208	err = tegra210_sfc_soft_reset(sfc);3209	if (err < 0) {3210		dev_err(dai->dev, "Failed to reset SFC in %s, err = %d\n",3211			__func__, err);3212 3213		return err;3214	}3215 3216	return 0;3217}3218 3219static int tegra210_sfc_in_hw_params(struct snd_pcm_substream *substream,3220				     struct snd_pcm_hw_params *params,3221				     struct snd_soc_dai *dai)3222{3223	struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);3224	struct device *dev = dai->dev;3225	int err;3226 3227	err = tegra210_sfc_rate_to_idx(dev, params_rate(params),3228				       &sfc->srate_in);3229	if (err < 0)3230		return err;3231 3232	err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_RX_CIF_CTRL);3233	if (err < 0) {3234		dev_err(dev, "Can't set SFC RX CIF: %d\n", err);3235		return err;3236	}3237 3238	regmap_write(sfc->regmap, TEGRA210_SFC_RX_FREQ, sfc->srate_in);3239 3240	return err;3241}3242 3243static int tegra210_sfc_out_hw_params(struct snd_pcm_substream *substream,3244				      struct snd_pcm_hw_params *params,3245				      struct snd_soc_dai *dai)3246{3247	struct tegra210_sfc *sfc = snd_soc_dai_get_drvdata(dai);3248	struct device *dev = dai->dev;3249	int err;3250 3251	err = tegra210_sfc_rate_to_idx(dev, params_rate(params),3252				       &sfc->srate_out);3253	if (err < 0)3254		return err;3255 3256	err = tegra210_sfc_set_audio_cif(sfc, params, TEGRA210_SFC_TX_CIF_CTRL);3257	if (err < 0) {3258		dev_err(dev, "Can't set SFC TX CIF: %d\n", err);3259		return err;3260	}3261 3262	regmap_write(sfc->regmap, TEGRA210_SFC_TX_FREQ, sfc->srate_out);3263 3264	return 0;3265}3266 3267static int tegra210_sfc_init(struct snd_soc_dapm_widget *w,3268			     struct snd_kcontrol *kcontrol, int event)3269{3270	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);3271 3272	return tegra210_sfc_write_coeff_ram(cmpnt);3273}3274 3275static int tegra210_sfc_iget_stereo_to_mono(struct snd_kcontrol *kcontrol,3276				    struct snd_ctl_elem_value *ucontrol)3277{3278	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3279	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3280 3281	ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_RX_PATH];3282 3283	return 0;3284}3285 3286static int tegra210_sfc_iput_stereo_to_mono(struct snd_kcontrol *kcontrol,3287				    struct snd_ctl_elem_value *ucontrol)3288{3289	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3290	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3291	unsigned int value = ucontrol->value.enumerated.item[0];3292 3293	if (value == sfc->stereo_to_mono[SFC_RX_PATH])3294		return 0;3295 3296	sfc->stereo_to_mono[SFC_RX_PATH] = value;3297 3298	return 1;3299}3300 3301static int tegra210_sfc_iget_mono_to_stereo(struct snd_kcontrol *kcontrol,3302				    struct snd_ctl_elem_value *ucontrol)3303{3304	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3305	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3306 3307	ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_RX_PATH];3308 3309	return 0;3310}3311 3312static int tegra210_sfc_iput_mono_to_stereo(struct snd_kcontrol *kcontrol,3313				    struct snd_ctl_elem_value *ucontrol)3314{3315	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3316	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3317	unsigned int value = ucontrol->value.enumerated.item[0];3318 3319	if (value == sfc->mono_to_stereo[SFC_RX_PATH])3320		return 0;3321 3322	sfc->mono_to_stereo[SFC_RX_PATH] = value;3323 3324	return 1;3325}3326 3327static int tegra210_sfc_oget_stereo_to_mono(struct snd_kcontrol *kcontrol,3328				    struct snd_ctl_elem_value *ucontrol)3329{3330	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3331	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3332 3333	ucontrol->value.enumerated.item[0] = sfc->stereo_to_mono[SFC_TX_PATH];3334 3335	return 0;3336}3337 3338static int tegra210_sfc_oput_stereo_to_mono(struct snd_kcontrol *kcontrol,3339				    struct snd_ctl_elem_value *ucontrol)3340{3341	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3342	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3343	unsigned int value = ucontrol->value.enumerated.item[0];3344 3345	if (value == sfc->stereo_to_mono[SFC_TX_PATH])3346		return 0;3347 3348	sfc->stereo_to_mono[SFC_TX_PATH] = value;3349 3350	return 1;3351}3352 3353static int tegra210_sfc_oget_mono_to_stereo(struct snd_kcontrol *kcontrol,3354				    struct snd_ctl_elem_value *ucontrol)3355{3356	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3357	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3358 3359	ucontrol->value.enumerated.item[0] = sfc->mono_to_stereo[SFC_TX_PATH];3360 3361	return 0;3362}3363 3364static int tegra210_sfc_oput_mono_to_stereo(struct snd_kcontrol *kcontrol,3365				    struct snd_ctl_elem_value *ucontrol)3366{3367	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);3368	struct tegra210_sfc *sfc = snd_soc_component_get_drvdata(cmpnt);3369	unsigned int value = ucontrol->value.enumerated.item[0];3370 3371	if (value == sfc->mono_to_stereo[SFC_TX_PATH])3372		return 0;3373 3374	sfc->mono_to_stereo[SFC_TX_PATH] = value;3375 3376	return 1;3377}3378 3379static const struct snd_soc_dai_ops tegra210_sfc_in_dai_ops = {3380	.hw_params	= tegra210_sfc_in_hw_params,3381	.startup	= tegra210_sfc_startup,3382};3383 3384static const struct snd_soc_dai_ops tegra210_sfc_out_dai_ops = {3385	.hw_params	= tegra210_sfc_out_hw_params,3386};3387 3388static struct snd_soc_dai_driver tegra210_sfc_dais[] = {3389	{3390		.name = "SFC-RX-CIF",3391		.playback = {3392			.stream_name = "RX-CIF-Playback",3393			.channels_min = 1,3394			.channels_max = 2,3395			.rates = SNDRV_PCM_RATE_8000_192000,3396			.formats = SNDRV_PCM_FMTBIT_S8 |3397				SNDRV_PCM_FMTBIT_S16_LE |3398				SNDRV_PCM_FMTBIT_S32_LE,3399		},3400		.capture = {3401			.stream_name = "RX-CIF-Capture",3402			.channels_min = 1,3403			.channels_max = 2,3404			.rates = SNDRV_PCM_RATE_8000_192000,3405			.formats = SNDRV_PCM_FMTBIT_S8 |3406				SNDRV_PCM_FMTBIT_S16_LE |3407				SNDRV_PCM_FMTBIT_S32_LE,3408		},3409		.ops = &tegra210_sfc_in_dai_ops,3410	},3411	{3412		.name = "SFC-TX-CIF",3413		.playback = {3414			.stream_name = "TX-CIF-Playback",3415			.channels_min = 1,3416			.channels_max = 2,3417			.rates = SNDRV_PCM_RATE_8000_192000,3418			.formats = SNDRV_PCM_FMTBIT_S8 |3419				SNDRV_PCM_FMTBIT_S16_LE |3420				SNDRV_PCM_FMTBIT_S32_LE,3421		},3422		.capture = {3423			.stream_name = "TX-CIF-Capture",3424			.channels_min = 1,3425			.channels_max = 2,3426			.rates = SNDRV_PCM_RATE_8000_192000,3427			.formats = SNDRV_PCM_FMTBIT_S8 |3428				SNDRV_PCM_FMTBIT_S16_LE |3429				SNDRV_PCM_FMTBIT_S32_LE,3430		},3431		.ops = &tegra210_sfc_out_dai_ops,3432	},3433};3434 3435static const struct snd_soc_dapm_widget tegra210_sfc_widgets[] = {3436	SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),3437	SND_SOC_DAPM_AIF_OUT_E("TX", NULL, 0, TEGRA210_SFC_ENABLE,3438			       TEGRA210_SFC_EN_SHIFT, 0,3439			       tegra210_sfc_init, SND_SOC_DAPM_PRE_PMU),3440};3441 3442#define RESAMPLE_ROUTE(sname)					\3443	{ "RX XBAR-" sname,	NULL,	"XBAR-TX" },		\3444	{ "RX-CIF-" sname,	NULL,	"RX XBAR-" sname },	\3445	{ "RX",			NULL,	"RX-CIF-" sname },	\3446	{ "TX-CIF-" sname,	NULL,	"TX" },			\3447	{ "TX XBAR-" sname,	NULL,	"TX-CIF-" sname },	\3448	{ "XBAR-RX",		NULL,	"TX XBAR-" sname }3449 3450static const struct snd_soc_dapm_route tegra210_sfc_routes[] = {3451	{ "TX", NULL, "RX" },3452	RESAMPLE_ROUTE("Playback"),3453	RESAMPLE_ROUTE("Capture"),3454};3455 3456static const char * const tegra210_sfc_stereo_conv_text[] = {3457	"CH0", "CH1", "AVG",3458};3459 3460static const char * const tegra210_sfc_mono_conv_text[] = {3461	"Zero", "Copy",3462};3463 3464static const struct soc_enum tegra210_sfc_stereo_conv_enum =3465	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,3466			ARRAY_SIZE(tegra210_sfc_stereo_conv_text),3467			tegra210_sfc_stereo_conv_text);3468 3469static const struct soc_enum tegra210_sfc_mono_conv_enum =3470	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,3471			ARRAY_SIZE(tegra210_sfc_mono_conv_text),3472			tegra210_sfc_mono_conv_text);3473 3474static const struct snd_kcontrol_new tegra210_sfc_controls[] = {3475	SOC_ENUM_EXT("Input Stereo To Mono", tegra210_sfc_stereo_conv_enum,3476		     tegra210_sfc_iget_stereo_to_mono,3477		     tegra210_sfc_iput_stereo_to_mono),3478	SOC_ENUM_EXT("Input Mono To Stereo", tegra210_sfc_mono_conv_enum,3479		     tegra210_sfc_iget_mono_to_stereo,3480		     tegra210_sfc_iput_mono_to_stereo),3481	SOC_ENUM_EXT("Output Stereo To Mono", tegra210_sfc_stereo_conv_enum,3482		     tegra210_sfc_oget_stereo_to_mono,3483		     tegra210_sfc_oput_stereo_to_mono),3484	SOC_ENUM_EXT("Output Mono To Stereo", tegra210_sfc_mono_conv_enum,3485		     tegra210_sfc_oget_mono_to_stereo,3486		     tegra210_sfc_oput_mono_to_stereo),3487};3488 3489static const struct snd_soc_component_driver tegra210_sfc_cmpnt = {3490	.dapm_widgets		= tegra210_sfc_widgets,3491	.num_dapm_widgets	= ARRAY_SIZE(tegra210_sfc_widgets),3492	.dapm_routes		= tegra210_sfc_routes,3493	.num_dapm_routes	= ARRAY_SIZE(tegra210_sfc_routes),3494	.controls		= tegra210_sfc_controls,3495	.num_controls		= ARRAY_SIZE(tegra210_sfc_controls),3496};3497 3498static bool tegra210_sfc_wr_reg(struct device *dev, unsigned int reg)3499{3500	switch (reg) {3501	case TEGRA210_SFC_RX_INT_MASK ... TEGRA210_SFC_RX_FREQ:3502	case TEGRA210_SFC_TX_INT_MASK ... TEGRA210_SFC_TX_FREQ:3503	case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_CG:3504	case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:3505		return true;3506	default:3507		return false;3508	}3509}3510 3511static bool tegra210_sfc_rd_reg(struct device *dev, unsigned int reg)3512{3513	switch (reg) {3514	case TEGRA210_SFC_RX_STATUS ... TEGRA210_SFC_RX_FREQ:3515	case TEGRA210_SFC_TX_STATUS ... TEGRA210_SFC_TX_FREQ:3516	case TEGRA210_SFC_ENABLE ... TEGRA210_SFC_INT_STATUS:3517	case TEGRA210_SFC_COEF_RAM ... TEGRA210_SFC_CFG_RAM_DATA:3518		return true;3519	default:3520		return false;3521	}3522}3523 3524static bool tegra210_sfc_volatile_reg(struct device *dev, unsigned int reg)3525{3526	switch (reg) {3527	case TEGRA210_SFC_RX_STATUS:3528	case TEGRA210_SFC_RX_INT_STATUS:3529	case TEGRA210_SFC_RX_INT_SET:3530 3531	case TEGRA210_SFC_TX_STATUS:3532	case TEGRA210_SFC_TX_INT_STATUS:3533	case TEGRA210_SFC_TX_INT_SET:3534 3535	case TEGRA210_SFC_SOFT_RESET:3536	case TEGRA210_SFC_STATUS:3537	case TEGRA210_SFC_INT_STATUS:3538	case TEGRA210_SFC_CFG_RAM_CTRL:3539	case TEGRA210_SFC_CFG_RAM_DATA:3540		return true;3541	default:3542		return false;3543	}3544}3545 3546static bool tegra210_sfc_precious_reg(struct device *dev, unsigned int reg)3547{3548	switch (reg) {3549	case TEGRA210_SFC_CFG_RAM_DATA:3550		return true;3551	default:3552		return false;3553	}3554}3555 3556static const struct regmap_config tegra210_sfc_regmap_config = {3557	.reg_bits		= 32,3558	.reg_stride		= 4,3559	.val_bits		= 32,3560	.max_register		= TEGRA210_SFC_CFG_RAM_DATA,3561	.writeable_reg		= tegra210_sfc_wr_reg,3562	.readable_reg		= tegra210_sfc_rd_reg,3563	.volatile_reg		= tegra210_sfc_volatile_reg,3564	.precious_reg		= tegra210_sfc_precious_reg,3565	.reg_defaults		= tegra210_sfc_reg_defaults,3566	.num_reg_defaults	= ARRAY_SIZE(tegra210_sfc_reg_defaults),3567	.cache_type		= REGCACHE_FLAT,3568};3569 3570static const struct of_device_id tegra210_sfc_of_match[] = {3571	{ .compatible = "nvidia,tegra210-sfc" },3572	{},3573};3574MODULE_DEVICE_TABLE(of, tegra210_sfc_of_match);3575 3576static int tegra210_sfc_platform_probe(struct platform_device *pdev)3577{3578	struct device *dev = &pdev->dev;3579	struct tegra210_sfc *sfc;3580	void __iomem *regs;3581	int err;3582 3583	sfc = devm_kzalloc(dev, sizeof(*sfc), GFP_KERNEL);3584	if (!sfc)3585		return -ENOMEM;3586 3587	dev_set_drvdata(dev, sfc);3588 3589	regs = devm_platform_ioremap_resource(pdev, 0);3590	if (IS_ERR(regs))3591		return PTR_ERR(regs);3592 3593	sfc->regmap = devm_regmap_init_mmio(dev, regs,3594					    &tegra210_sfc_regmap_config);3595	if (IS_ERR(sfc->regmap)) {3596		dev_err(dev, "regmap init failed\n");3597		return PTR_ERR(sfc->regmap);3598	}3599 3600	regcache_cache_only(sfc->regmap, true);3601 3602	err = devm_snd_soc_register_component(dev, &tegra210_sfc_cmpnt,3603					      tegra210_sfc_dais,3604					      ARRAY_SIZE(tegra210_sfc_dais));3605	if (err) {3606		dev_err(dev, "can't register SFC component, err: %d\n", err);3607		return err;3608	}3609 3610	pm_runtime_enable(&pdev->dev);3611 3612	return 0;3613}3614 3615static void tegra210_sfc_platform_remove(struct platform_device *pdev)3616{3617	pm_runtime_disable(&pdev->dev);3618}3619 3620static const struct dev_pm_ops tegra210_sfc_pm_ops = {3621	SET_RUNTIME_PM_OPS(tegra210_sfc_runtime_suspend,3622			   tegra210_sfc_runtime_resume, NULL)3623	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,3624				pm_runtime_force_resume)3625};3626 3627static struct platform_driver tegra210_sfc_driver = {3628	.driver = {3629		.name = "tegra210-sfc",3630		.of_match_table = tegra210_sfc_of_match,3631		.pm = &tegra210_sfc_pm_ops,3632	},3633	.probe = tegra210_sfc_platform_probe,3634	.remove = tegra210_sfc_platform_remove,3635};3636module_platform_driver(tegra210_sfc_driver)3637 3638MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");3639MODULE_DESCRIPTION("Tegra210 SFC ASoC driver");3640MODULE_LICENSE("GPL v2");3641