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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor4 *5 * Multi-channel Audio Serial Port Driver6 *7 * Author: Nirmal Pandey <n-pandey@ti.com>,8 * Suresh Rajashekara <suresh.r@ti.com>9 * Steve Chen <schen@.mvista.com>10 *11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>12 * Copyright: (C) 2009 Texas Instruments, India13 */14 15#include <linux/init.h>16#include <linux/module.h>17#include <linux/device.h>18#include <linux/slab.h>19#include <linux/delay.h>20#include <linux/io.h>21#include <linux/clk.h>22#include <linux/pm_runtime.h>23#include <linux/of.h>24#include <linux/platform_data/davinci_asp.h>25#include <linux/math64.h>26#include <linux/bitmap.h>27#include <linux/gpio/driver.h>28 29#include <sound/asoundef.h>30#include <sound/core.h>31#include <sound/pcm.h>32#include <sound/pcm_params.h>33#include <sound/initval.h>34#include <sound/soc.h>35#include <sound/dmaengine_pcm.h>36 37#include "edma-pcm.h"38#include "sdma-pcm.h"39#include "udma-pcm.h"40#include "davinci-mcasp.h"41 42#define MCASP_MAX_AFIFO_DEPTH 6443 44#ifdef CONFIG_PM45static u32 context_regs[] = {46 DAVINCI_MCASP_TXFMCTL_REG,47 DAVINCI_MCASP_RXFMCTL_REG,48 DAVINCI_MCASP_TXFMT_REG,49 DAVINCI_MCASP_RXFMT_REG,50 DAVINCI_MCASP_ACLKXCTL_REG,51 DAVINCI_MCASP_ACLKRCTL_REG,52 DAVINCI_MCASP_AHCLKXCTL_REG,53 DAVINCI_MCASP_AHCLKRCTL_REG,54 DAVINCI_MCASP_PDIR_REG,55 DAVINCI_MCASP_PFUNC_REG,56 DAVINCI_MCASP_RXMASK_REG,57 DAVINCI_MCASP_TXMASK_REG,58 DAVINCI_MCASP_RXTDM_REG,59 DAVINCI_MCASP_TXTDM_REG,60};61 62struct davinci_mcasp_context {63 u32 config_regs[ARRAY_SIZE(context_regs)];64 u32 afifo_regs[2]; /* for read/write fifo control registers */65 u32 *xrsr_regs; /* for serializer configuration */66 bool pm_state;67};68#endif69 70struct davinci_mcasp_ruledata {71 struct davinci_mcasp *mcasp;72 int serializers;73};74 75struct davinci_mcasp {76 struct snd_dmaengine_dai_dma_data dma_data[2];77 struct davinci_mcasp_pdata *pdata;78 void __iomem *base;79 u32 fifo_base;80 struct device *dev;81 struct snd_pcm_substream *substreams[2];82 unsigned int dai_fmt;83 84 u32 iec958_status;85 86 /* Audio can not be enabled due to missing parameter(s) */87 bool missing_audio_param;88 89 /* McASP specific data */90 int tdm_slots;91 u32 tdm_mask[2];92 int slot_width;93 u8 op_mode;94 u8 dismod;95 u8 num_serializer;96 u8 *serial_dir;97 u8 version;98 u8 bclk_div;99 int streams;100 u32 irq_request[2];101 102 int sysclk_freq;103 bool bclk_master;104 u32 auxclk_fs_ratio;105 106 unsigned long pdir; /* Pin direction bitfield */107 108 /* McASP FIFO related */109 u8 txnumevt;110 u8 rxnumevt;111 112 bool dat_port;113 114 /* Used for comstraint setting on the second stream */115 u32 channels;116 int max_format_width;117 u8 active_serializers[2];118 119#ifdef CONFIG_GPIOLIB120 struct gpio_chip gpio_chip;121#endif122 123#ifdef CONFIG_PM124 struct davinci_mcasp_context context;125#endif126 127 struct davinci_mcasp_ruledata ruledata[2];128 struct snd_pcm_hw_constraint_list chconstr[2];129};130 131static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,132 u32 val)133{134 void __iomem *reg = mcasp->base + offset;135 __raw_writel(__raw_readl(reg) | val, reg);136}137 138static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,139 u32 val)140{141 void __iomem *reg = mcasp->base + offset;142 __raw_writel((__raw_readl(reg) & ~(val)), reg);143}144 145static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,146 u32 val, u32 mask)147{148 void __iomem *reg = mcasp->base + offset;149 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);150}151 152static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,153 u32 val)154{155 __raw_writel(val, mcasp->base + offset);156}157 158static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)159{160 return (u32)__raw_readl(mcasp->base + offset);161}162 163static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)164{165 int i = 0;166 167 mcasp_set_bits(mcasp, ctl_reg, val);168 169 /* programming GBLCTL needs to read back from GBLCTL and verfiy */170 /* loop count is to avoid the lock-up */171 for (i = 0; i < 1000; i++) {172 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)173 break;174 }175 176 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))177 printk(KERN_ERR "GBLCTL write error\n");178}179 180static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)181{182 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);183 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);184 185 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;186}187 188static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)189{190 u32 bit = PIN_BIT_AMUTE;191 192 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {193 if (enable)194 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));195 else196 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));197 }198}199 200static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)201{202 u32 bit;203 204 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {205 if (enable)206 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));207 else208 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));209 }210}211 212static void mcasp_start_rx(struct davinci_mcasp *mcasp)213{214 if (mcasp->rxnumevt) { /* enable FIFO */215 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;216 217 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);218 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);219 }220 221 /* Start clocks */222 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);223 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);224 /*225 * When ASYNC == 0 the transmit and receive sections operate226 * synchronously from the transmit clock and frame sync. We need to make227 * sure that the TX signlas are enabled when starting reception.228 */229 if (mcasp_is_synchronous(mcasp)) {230 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);231 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);232 mcasp_set_clk_pdir(mcasp, true);233 }234 235 /* Activate serializer(s) */236 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);237 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);238 /* Release RX state machine */239 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);240 /* Release Frame Sync generator */241 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);242 if (mcasp_is_synchronous(mcasp))243 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);244 245 /* enable receive IRQs */246 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,247 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);248}249 250static void mcasp_start_tx(struct davinci_mcasp *mcasp)251{252 u32 cnt;253 254 if (mcasp->txnumevt) { /* enable FIFO */255 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;256 257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);258 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);259 }260 261 /* Start clocks */262 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);263 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);264 mcasp_set_clk_pdir(mcasp, true);265 266 /* Activate serializer(s) */267 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);268 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);269 270 /* wait for XDATA to be cleared */271 cnt = 0;272 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&273 (cnt < 100000))274 cnt++;275 276 mcasp_set_axr_pdir(mcasp, true);277 278 /* Release TX state machine */279 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);280 /* Release Frame Sync generator */281 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);282 283 /* enable transmit IRQs */284 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,285 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);286}287 288static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)289{290 mcasp->streams++;291 292 if (stream == SNDRV_PCM_STREAM_PLAYBACK)293 mcasp_start_tx(mcasp);294 else295 mcasp_start_rx(mcasp);296}297 298static void mcasp_stop_rx(struct davinci_mcasp *mcasp)299{300 /* disable IRQ sources */301 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,302 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);303 304 /*305 * In synchronous mode stop the TX clocks if no other stream is306 * running307 */308 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {309 mcasp_set_clk_pdir(mcasp, false);310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);311 }312 313 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);314 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);315 316 if (mcasp->rxnumevt) { /* disable FIFO */317 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;318 319 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);320 }321}322 323static void mcasp_stop_tx(struct davinci_mcasp *mcasp)324{325 u32 val = 0;326 327 /* disable IRQ sources */328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,329 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);330 331 /*332 * In synchronous mode keep TX clocks running if the capture stream is333 * still running.334 */335 if (mcasp_is_synchronous(mcasp) && mcasp->streams)336 val = TXHCLKRST | TXCLKRST | TXFSRST;337 else338 mcasp_set_clk_pdir(mcasp, false);339 340 341 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);342 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);343 344 if (mcasp->txnumevt) { /* disable FIFO */345 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;346 347 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);348 }349 350 mcasp_set_axr_pdir(mcasp, false);351}352 353static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)354{355 mcasp->streams--;356 357 if (stream == SNDRV_PCM_STREAM_PLAYBACK)358 mcasp_stop_tx(mcasp);359 else360 mcasp_stop_rx(mcasp);361}362 363static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)364{365 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;366 struct snd_pcm_substream *substream;367 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];368 u32 handled_mask = 0;369 u32 stat;370 371 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);372 if (stat & XUNDRN & irq_mask) {373 dev_warn(mcasp->dev, "Transmit buffer underflow\n");374 handled_mask |= XUNDRN;375 376 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];377 if (substream)378 snd_pcm_stop_xrun(substream);379 }380 381 if (!handled_mask)382 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",383 stat);384 385 if (stat & XRERR)386 handled_mask |= XRERR;387 388 /* Ack the handled event only */389 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);390 391 return IRQ_RETVAL(handled_mask);392}393 394static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)395{396 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;397 struct snd_pcm_substream *substream;398 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];399 u32 handled_mask = 0;400 u32 stat;401 402 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);403 if (stat & ROVRN & irq_mask) {404 dev_warn(mcasp->dev, "Receive buffer overflow\n");405 handled_mask |= ROVRN;406 407 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];408 if (substream)409 snd_pcm_stop_xrun(substream);410 }411 412 if (!handled_mask)413 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",414 stat);415 416 if (stat & XRERR)417 handled_mask |= XRERR;418 419 /* Ack the handled event only */420 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);421 422 return IRQ_RETVAL(handled_mask);423}424 425static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)426{427 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;428 irqreturn_t ret = IRQ_NONE;429 430 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])431 ret = davinci_mcasp_tx_irq_handler(irq, data);432 433 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])434 ret |= davinci_mcasp_rx_irq_handler(irq, data);435 436 return ret;437}438 439static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,440 unsigned int fmt)441{442 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);443 int ret = 0;444 u32 data_delay;445 bool fs_pol_rising;446 bool inv_fs = false;447 448 if (!fmt)449 return 0;450 451 pm_runtime_get_sync(mcasp->dev);452 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {453 case SND_SOC_DAIFMT_DSP_A:454 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);455 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);456 /* 1st data bit occur one ACLK cycle after the frame sync */457 data_delay = 1;458 break;459 case SND_SOC_DAIFMT_DSP_B:460 case SND_SOC_DAIFMT_AC97:461 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);462 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);463 /* No delay after FS */464 data_delay = 0;465 break;466 case SND_SOC_DAIFMT_I2S:467 /* configure a full-word SYNC pulse (LRCLK) */468 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);469 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);470 /* 1st data bit occur one ACLK cycle after the frame sync */471 data_delay = 1;472 /* FS need to be inverted */473 inv_fs = true;474 break;475 case SND_SOC_DAIFMT_RIGHT_J:476 case SND_SOC_DAIFMT_LEFT_J:477 /* configure a full-word SYNC pulse (LRCLK) */478 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);479 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);480 /* No delay after FS */481 data_delay = 0;482 break;483 default:484 ret = -EINVAL;485 goto out;486 }487 488 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),489 FSXDLY(3));490 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),491 FSRDLY(3));492 493 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {494 case SND_SOC_DAIFMT_BP_FP:495 /* codec is clock and frame slave */496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);497 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);498 499 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);500 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);501 502 /* BCLK */503 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);504 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);505 /* Frame Sync */506 set_bit(PIN_BIT_AFSX, &mcasp->pdir);507 set_bit(PIN_BIT_AFSR, &mcasp->pdir);508 509 mcasp->bclk_master = 1;510 break;511 case SND_SOC_DAIFMT_BP_FC:512 /* codec is clock slave and frame master */513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);515 516 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);518 519 /* BCLK */520 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);521 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);522 /* Frame Sync */523 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);524 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);525 526 mcasp->bclk_master = 1;527 break;528 case SND_SOC_DAIFMT_BC_FP:529 /* codec is clock master and frame slave */530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);531 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);532 533 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);534 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);535 536 /* BCLK */537 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);538 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);539 /* Frame Sync */540 set_bit(PIN_BIT_AFSX, &mcasp->pdir);541 set_bit(PIN_BIT_AFSR, &mcasp->pdir);542 543 mcasp->bclk_master = 0;544 break;545 case SND_SOC_DAIFMT_BC_FC:546 /* codec is clock and frame master */547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);549 550 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);551 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);552 553 /* BCLK */554 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);555 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);556 /* Frame Sync */557 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);558 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);559 560 mcasp->bclk_master = 0;561 break;562 default:563 ret = -EINVAL;564 goto out;565 }566 567 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {568 case SND_SOC_DAIFMT_IB_NF:569 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);570 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);571 fs_pol_rising = true;572 break;573 case SND_SOC_DAIFMT_NB_IF:574 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);575 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);576 fs_pol_rising = false;577 break;578 case SND_SOC_DAIFMT_IB_IF:579 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);580 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);581 fs_pol_rising = false;582 break;583 case SND_SOC_DAIFMT_NB_NF:584 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);585 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);586 fs_pol_rising = true;587 break;588 default:589 ret = -EINVAL;590 goto out;591 }592 593 if (inv_fs)594 fs_pol_rising = !fs_pol_rising;595 596 if (fs_pol_rising) {597 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);598 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);599 } else {600 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);601 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);602 }603 604 mcasp->dai_fmt = fmt;605out:606 pm_runtime_put(mcasp->dev);607 return ret;608}609 610static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,611 int div, bool explicit)612{613 pm_runtime_get_sync(mcasp->dev);614 switch (div_id) {615 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,617 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);618 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,619 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);620 break;621 622 case MCASP_CLKDIV_BCLK: /* BCLK divider */623 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,624 ACLKXDIV(div - 1), ACLKXDIV_MASK);625 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,626 ACLKRDIV(div - 1), ACLKRDIV_MASK);627 if (explicit)628 mcasp->bclk_div = div;629 break;630 631 case MCASP_CLKDIV_BCLK_FS_RATIO:632 /*633 * BCLK/LRCLK ratio descries how many bit-clock cycles634 * fit into one frame. The clock ratio is given for a635 * full period of data (for I2S format both left and636 * right channels), so it has to be divided by number637 * of tdm-slots (for I2S - divided by 2).638 * Instead of storing this ratio, we calculate a new639 * tdm_slot width by dividing the ratio by the640 * number of configured tdm slots.641 */642 mcasp->slot_width = div / mcasp->tdm_slots;643 if (div % mcasp->tdm_slots)644 dev_warn(mcasp->dev,645 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",646 __func__, div, mcasp->tdm_slots);647 break;648 649 default:650 return -EINVAL;651 }652 653 pm_runtime_put(mcasp->dev);654 return 0;655}656 657static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,658 int div)659{660 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);661 662 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);663}664 665static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,666 unsigned int freq, int dir)667{668 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);669 670 pm_runtime_get_sync(mcasp->dev);671 672 if (dir == SND_SOC_CLOCK_IN) {673 switch (clk_id) {674 case MCASP_CLK_HCLK_AHCLK:675 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,676 AHCLKXE);677 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,678 AHCLKRE);679 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);680 break;681 case MCASP_CLK_HCLK_AUXCLK:682 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,683 AHCLKXE);684 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,685 AHCLKRE);686 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);687 break;688 default:689 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);690 goto out;691 }692 } else {693 /* Select AUXCLK as HCLK */694 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);695 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);696 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);697 }698 /*699 * When AHCLK X/R is selected to be output it means that the HCLK is700 * the same clock - coming via AUXCLK.701 */702 mcasp->sysclk_freq = freq;703out:704 pm_runtime_put(mcasp->dev);705 return 0;706}707 708/* All serializers must have equal number of channels */709static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,710 int serializers)711{712 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];713 unsigned int *list = (unsigned int *) cl->list;714 int slots = mcasp->tdm_slots;715 int i, count = 0;716 717 if (mcasp->tdm_mask[stream])718 slots = hweight32(mcasp->tdm_mask[stream]);719 720 for (i = 1; i <= slots; i++)721 list[count++] = i;722 723 for (i = 2; i <= serializers; i++)724 list[count++] = i*slots;725 726 cl->count = count;727 728 return 0;729}730 731static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)732{733 int rx_serializers = 0, tx_serializers = 0, ret, i;734 735 for (i = 0; i < mcasp->num_serializer; i++)736 if (mcasp->serial_dir[i] == TX_MODE)737 tx_serializers++;738 else if (mcasp->serial_dir[i] == RX_MODE)739 rx_serializers++;740 741 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,742 tx_serializers);743 if (ret)744 return ret;745 746 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,747 rx_serializers);748 749 return ret;750}751 752 753static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,754 unsigned int tx_mask,755 unsigned int rx_mask,756 int slots, int slot_width)757{758 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);759 760 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)761 return 0;762 763 dev_dbg(mcasp->dev,764 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",765 __func__, tx_mask, rx_mask, slots, slot_width);766 767 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {768 dev_err(mcasp->dev,769 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",770 tx_mask, rx_mask, slots);771 return -EINVAL;772 }773 774 if (slot_width &&775 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {776 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",777 __func__, slot_width);778 return -EINVAL;779 }780 781 mcasp->tdm_slots = slots;782 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;783 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;784 mcasp->slot_width = slot_width;785 786 return davinci_mcasp_set_ch_constraints(mcasp);787}788 789static int davinci_config_channel_size(struct davinci_mcasp *mcasp,790 int sample_width)791{792 u32 fmt;793 u32 tx_rotate, rx_rotate, slot_width;794 u32 mask = (1ULL << sample_width) - 1;795 796 if (mcasp->slot_width)797 slot_width = mcasp->slot_width;798 else if (mcasp->max_format_width)799 slot_width = mcasp->max_format_width;800 else801 slot_width = sample_width;802 /*803 * TX rotation:804 * right aligned formats: rotate w/ slot_width805 * left aligned formats: rotate w/ sample_width806 *807 * RX rotation:808 * right aligned formats: no rotation needed809 * left aligned formats: rotate w/ (slot_width - sample_width)810 */811 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==812 SND_SOC_DAIFMT_RIGHT_J) {813 tx_rotate = (slot_width / 4) & 0x7;814 rx_rotate = 0;815 } else {816 tx_rotate = (sample_width / 4) & 0x7;817 rx_rotate = (slot_width - sample_width) / 4;818 }819 820 /* mapping of the XSSZ bit-field as described in the datasheet */821 fmt = (slot_width >> 1) - 1;822 823 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),825 RXSSZ(0x0F));826 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),827 TXSSZ(0x0F));828 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),829 TXROT(7));830 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),831 RXROT(7));832 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);833 } else {834 /*835 * according to the TRM it should be TXROT=0, this one works:836 * 16 bit to 23-8 (TXROT=6, rotate 24 bits)837 * 24 bit to 23-0 (TXROT=0, rotate 0 bits)838 *839 * TXROT = 0 only works with 24bit samples840 */841 tx_rotate = (sample_width / 4 + 2) & 0x7;842 843 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),844 TXROT(7));845 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15),846 TXSSZ(0x0F));847 }848 849 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);850 851 return 0;852}853 854static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,855 int period_words, int channels)856{857 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];858 int i;859 u8 tx_ser = 0;860 u8 rx_ser = 0;861 u8 slots = mcasp->tdm_slots;862 u8 max_active_serializers, max_rx_serializers, max_tx_serializers;863 int active_serializers, numevt;864 u32 reg;865 866 /* In DIT mode we only allow maximum of one serializers for now */867 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)868 max_active_serializers = 1;869 else870 max_active_serializers = DIV_ROUND_UP(channels, slots);871 872 /* Default configuration */873 if (mcasp->version < MCASP_VERSION_3)874 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);875 876 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {877 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);878 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);879 max_tx_serializers = max_active_serializers;880 max_rx_serializers =881 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];882 } else {883 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);884 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);885 max_tx_serializers =886 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];887 max_rx_serializers = max_active_serializers;888 }889 890 for (i = 0; i < mcasp->num_serializer; i++) {891 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),892 mcasp->serial_dir[i]);893 if (mcasp->serial_dir[i] == TX_MODE &&894 tx_ser < max_tx_serializers) {895 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),896 mcasp->dismod, DISMOD_MASK);897 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);898 tx_ser++;899 } else if (mcasp->serial_dir[i] == RX_MODE &&900 rx_ser < max_rx_serializers) {901 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);902 rx_ser++;903 } else {904 /* Inactive or unused pin, set it to inactive */905 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),906 SRMOD_INACTIVE, SRMOD_MASK);907 /* If unused, set DISMOD for the pin */908 if (mcasp->serial_dir[i] != INACTIVE_MODE)909 mcasp_mod_bits(mcasp,910 DAVINCI_MCASP_XRSRCTL_REG(i),911 mcasp->dismod, DISMOD_MASK);912 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);913 }914 }915 916 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {917 active_serializers = tx_ser;918 numevt = mcasp->txnumevt;919 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;920 } else {921 active_serializers = rx_ser;922 numevt = mcasp->rxnumevt;923 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;924 }925 926 if (active_serializers < max_active_serializers) {927 dev_warn(mcasp->dev, "stream has more channels (%d) than are "928 "enabled in mcasp (%d)\n", channels,929 active_serializers * slots);930 return -EINVAL;931 }932 933 /* AFIFO is not in use */934 if (!numevt) {935 /* Configure the burst size for platform drivers */936 if (active_serializers > 1) {937 /*938 * If more than one serializers are in use we have one939 * DMA request to provide data for all serializers.940 * For example if three serializers are enabled the DMA941 * need to transfer three words per DMA request.942 */943 dma_data->maxburst = active_serializers;944 } else {945 dma_data->maxburst = 0;946 }947 948 goto out;949 }950 951 if (period_words % active_serializers) {952 dev_err(mcasp->dev, "Invalid combination of period words and "953 "active serializers: %d, %d\n", period_words,954 active_serializers);955 return -EINVAL;956 }957 958 /*959 * Calculate the optimal AFIFO depth for platform side:960 * The number of words for numevt need to be in steps of active961 * serializers.962 */963 numevt = (numevt / active_serializers) * active_serializers;964 965 while (period_words % numevt && numevt > 0)966 numevt -= active_serializers;967 if (numevt <= 0)968 numevt = active_serializers;969 970 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);971 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);972 973 /* Configure the burst size for platform drivers */974 if (numevt == 1)975 numevt = 0;976 dma_data->maxburst = numevt;977 978out:979 mcasp->active_serializers[stream] = active_serializers;980 981 return 0;982}983 984static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,985 int channels)986{987 int i, active_slots;988 int total_slots;989 int active_serializers;990 u32 mask = 0;991 u32 busel = 0;992 993 total_slots = mcasp->tdm_slots;994 995 /*996 * If more than one serializer is needed, then use them with997 * all the specified tdm_slots. Otherwise, one serializer can998 * cope with the transaction using just as many slots as there999 * are channels in the stream.1000 */1001 if (mcasp->tdm_mask[stream]) {1002 active_slots = hweight32(mcasp->tdm_mask[stream]);1003 active_serializers = DIV_ROUND_UP(channels, active_slots);1004 if (active_serializers == 1)1005 active_slots = channels;1006 for (i = 0; i < total_slots; i++) {1007 if ((1 << i) & mcasp->tdm_mask[stream]) {1008 mask |= (1 << i);1009 if (--active_slots <= 0)1010 break;1011 }1012 }1013 } else {1014 active_serializers = DIV_ROUND_UP(channels, total_slots);1015 if (active_serializers == 1)1016 active_slots = channels;1017 else1018 active_slots = total_slots;1019 1020 for (i = 0; i < active_slots; i++)1021 mask |= (1 << i);1022 }1023 1024 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);1025 1026 if (!mcasp->dat_port)1027 busel = TXSEL;1028 1029 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {1030 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);1031 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);1032 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,1033 FSXMOD(total_slots), FSXMOD(0x1FF));1034 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {1035 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);1037 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,1038 FSRMOD(total_slots), FSRMOD(0x1FF));1039 /*1040 * If McASP is set to be TX/RX synchronous and the playback is1041 * not running already we need to configure the TX slots in1042 * order to have correct FSX on the bus1043 */1044 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)1045 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,1046 FSXMOD(total_slots), FSXMOD(0x1FF));1047 }1048 1049 return 0;1050}1051 1052/* S/PDIF */1053static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,1054 unsigned int rate)1055{1056 u8 *cs_bytes = (u8 *)&mcasp->iec958_status;1057 1058 if (!mcasp->dat_port)1059 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);1060 else1061 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL);1062 1063 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */1064 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));1065 1066 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF);1067 1068 /* Set the TX tdm : for all the slots */1069 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);1070 1071 /* Set the TX clock controls : div = 1 and internal */1072 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);1073 1074 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);1075 1076 /* Set S/PDIF channel status bits */1077 cs_bytes[3] &= ~IEC958_AES3_CON_FS;1078 switch (rate) {1079 case 22050:1080 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;1081 break;1082 case 24000:1083 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;1084 break;1085 case 32000:1086 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;1087 break;1088 case 44100:1089 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;1090 break;1091 case 48000:1092 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;1093 break;1094 case 88200:1095 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;1096 break;1097 case 96000:1098 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;1099 break;1100 case 176400:1101 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;1102 break;1103 case 192000:1104 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;1105 break;1106 default:1107 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate);1108 return -EINVAL;1109 }1110 1111 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status);1112 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status);1113 1114 /* Enable the DIT */1115 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);1116 1117 return 0;1118}1119 1120static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,1121 unsigned int sysclk_freq,1122 unsigned int bclk_freq, bool set)1123{1124 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);1125 int div = sysclk_freq / bclk_freq;1126 int rem = sysclk_freq % bclk_freq;1127 int error_ppm;1128 int aux_div = 1;1129 1130 if (div > (ACLKXDIV_MASK + 1)) {1131 if (reg & AHCLKXE) {1132 aux_div = div / (ACLKXDIV_MASK + 1);1133 if (div % (ACLKXDIV_MASK + 1))1134 aux_div++;1135 1136 sysclk_freq /= aux_div;1137 div = sysclk_freq / bclk_freq;1138 rem = sysclk_freq % bclk_freq;1139 } else if (set) {1140 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",1141 sysclk_freq);1142 }1143 }1144 1145 if (rem != 0) {1146 if (div == 0 ||1147 ((sysclk_freq / div) - bclk_freq) >1148 (bclk_freq - (sysclk_freq / (div+1)))) {1149 div++;1150 rem = rem - bclk_freq;1151 }1152 }1153 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,1154 (int)bclk_freq)) / div - 1000000;1155 1156 if (set) {1157 if (error_ppm)1158 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",1159 error_ppm);1160 1161 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);1162 if (reg & AHCLKXE)1163 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,1164 aux_div, 0);1165 }1166 1167 return error_ppm;1168}1169 1170static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)1171{1172 if (!mcasp->txnumevt)1173 return 0;1174 1175 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);1176}1177 1178static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)1179{1180 if (!mcasp->rxnumevt)1181 return 0;1182 1183 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);1184}1185 1186static snd_pcm_sframes_t davinci_mcasp_delay(1187 struct snd_pcm_substream *substream,1188 struct snd_soc_dai *cpu_dai)1189{1190 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1191 u32 fifo_use;1192 1193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)1194 fifo_use = davinci_mcasp_tx_delay(mcasp);1195 else1196 fifo_use = davinci_mcasp_rx_delay(mcasp);1197 1198 /*1199 * Divide the used locations with the channel count to get the1200 * FIFO usage in samples (don't care about partial samples in the1201 * buffer).1202 */1203 return fifo_use / substream->runtime->channels;1204}1205 1206static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,1207 struct snd_pcm_hw_params *params,1208 struct snd_soc_dai *cpu_dai)1209{1210 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1211 int word_length;1212 int channels = params_channels(params);1213 int period_size = params_period_size(params);1214 int ret;1215 1216 switch (params_format(params)) {1217 case SNDRV_PCM_FORMAT_U8:1218 case SNDRV_PCM_FORMAT_S8:1219 word_length = 8;1220 break;1221 1222 case SNDRV_PCM_FORMAT_U16_LE:1223 case SNDRV_PCM_FORMAT_S16_LE:1224 word_length = 16;1225 break;1226 1227 case SNDRV_PCM_FORMAT_U24_3LE:1228 case SNDRV_PCM_FORMAT_S24_3LE:1229 word_length = 24;1230 break;1231 1232 case SNDRV_PCM_FORMAT_U24_LE:1233 case SNDRV_PCM_FORMAT_S24_LE:1234 word_length = 24;1235 break;1236 1237 case SNDRV_PCM_FORMAT_U32_LE:1238 case SNDRV_PCM_FORMAT_S32_LE:1239 word_length = 32;1240 break;1241 1242 default:1243 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");1244 return -EINVAL;1245 }1246 1247 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);1248 if (ret)1249 return ret;1250 1251 /*1252 * If mcasp is BCLK master, and a BCLK divider was not provided by1253 * the machine driver, we need to calculate the ratio.1254 */1255 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {1256 int slots = mcasp->tdm_slots;1257 int rate = params_rate(params);1258 int sbits = params_width(params);1259 unsigned int bclk_target;1260 1261 if (mcasp->slot_width)1262 sbits = mcasp->slot_width;1263 1264 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)1265 bclk_target = rate * sbits * slots;1266 else1267 bclk_target = rate * 128;1268 1269 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,1270 bclk_target, true);1271 }1272 1273 ret = mcasp_common_hw_param(mcasp, substream->stream,1274 period_size * channels, channels);1275 if (ret)1276 return ret;1277 1278 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)1279 ret = mcasp_dit_hw_param(mcasp, params_rate(params));1280 else1281 ret = mcasp_i2s_hw_param(mcasp, substream->stream,1282 channels);1283 1284 if (ret)1285 return ret;1286 1287 davinci_config_channel_size(mcasp, word_length);1288 1289 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {1290 mcasp->channels = channels;1291 if (!mcasp->max_format_width)1292 mcasp->max_format_width = word_length;1293 }1294 1295 return 0;1296}1297 1298static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,1299 int cmd, struct snd_soc_dai *cpu_dai)1300{1301 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1302 int ret = 0;1303 1304 switch (cmd) {1305 case SNDRV_PCM_TRIGGER_RESUME:1306 case SNDRV_PCM_TRIGGER_START:1307 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:1308 davinci_mcasp_start(mcasp, substream->stream);1309 break;1310 case SNDRV_PCM_TRIGGER_SUSPEND:1311 case SNDRV_PCM_TRIGGER_STOP:1312 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:1313 davinci_mcasp_stop(mcasp, substream->stream);1314 break;1315 1316 default:1317 ret = -EINVAL;1318 }1319 1320 return ret;1321}1322 1323static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,1324 struct snd_pcm_hw_rule *rule)1325{1326 struct davinci_mcasp_ruledata *rd = rule->private;1327 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);1328 struct snd_mask nfmt;1329 int slot_width;1330 snd_pcm_format_t i;1331 1332 snd_mask_none(&nfmt);1333 slot_width = rd->mcasp->slot_width;1334 1335 pcm_for_each_format(i) {1336 if (snd_mask_test_format(fmt, i)) {1337 if (snd_pcm_format_width(i) <= slot_width) {1338 snd_mask_set_format(&nfmt, i);1339 }1340 }1341 }1342 1343 return snd_mask_refine(fmt, &nfmt);1344}1345 1346static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,1347 struct snd_pcm_hw_rule *rule)1348{1349 struct davinci_mcasp_ruledata *rd = rule->private;1350 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);1351 struct snd_mask nfmt;1352 int format_width;1353 snd_pcm_format_t i;1354 1355 snd_mask_none(&nfmt);1356 format_width = rd->mcasp->max_format_width;1357 1358 pcm_for_each_format(i) {1359 if (snd_mask_test_format(fmt, i)) {1360 if (snd_pcm_format_width(i) == format_width) {1361 snd_mask_set_format(&nfmt, i);1362 }1363 }1364 }1365 1366 return snd_mask_refine(fmt, &nfmt);1367}1368 1369static const unsigned int davinci_mcasp_dai_rates[] = {1370 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,1371 88200, 96000, 176400, 192000,1372};1373 1374#define DAVINCI_MAX_RATE_ERROR_PPM 10001375 1376static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,1377 struct snd_pcm_hw_rule *rule)1378{1379 struct davinci_mcasp_ruledata *rd = rule->private;1380 struct snd_interval *ri =1381 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);1382 int sbits = params_width(params);1383 int slots = rd->mcasp->tdm_slots;1384 struct snd_interval range;1385 int i;1386 1387 if (rd->mcasp->slot_width)1388 sbits = rd->mcasp->slot_width;1389 1390 snd_interval_any(&range);1391 range.empty = 1;1392 1393 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {1394 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {1395 uint bclk_freq = sbits * slots *1396 davinci_mcasp_dai_rates[i];1397 unsigned int sysclk_freq;1398 int ppm;1399 1400 if (rd->mcasp->auxclk_fs_ratio)1401 sysclk_freq = davinci_mcasp_dai_rates[i] *1402 rd->mcasp->auxclk_fs_ratio;1403 else1404 sysclk_freq = rd->mcasp->sysclk_freq;1405 1406 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,1407 bclk_freq, false);1408 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {1409 if (range.empty) {1410 range.min = davinci_mcasp_dai_rates[i];1411 range.empty = 0;1412 }1413 range.max = davinci_mcasp_dai_rates[i];1414 }1415 }1416 }1417 1418 dev_dbg(rd->mcasp->dev,1419 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",1420 ri->min, ri->max, range.min, range.max, sbits, slots);1421 1422 return snd_interval_refine(hw_param_interval(params, rule->var),1423 &range);1424}1425 1426static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,1427 struct snd_pcm_hw_rule *rule)1428{1429 struct davinci_mcasp_ruledata *rd = rule->private;1430 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);1431 struct snd_mask nfmt;1432 int rate = params_rate(params);1433 int slots = rd->mcasp->tdm_slots;1434 int count = 0;1435 snd_pcm_format_t i;1436 1437 snd_mask_none(&nfmt);1438 1439 pcm_for_each_format(i) {1440 if (snd_mask_test_format(fmt, i)) {1441 uint sbits = snd_pcm_format_width(i);1442 unsigned int sysclk_freq;1443 int ppm;1444 1445 if (rd->mcasp->auxclk_fs_ratio)1446 sysclk_freq = rate *1447 rd->mcasp->auxclk_fs_ratio;1448 else1449 sysclk_freq = rd->mcasp->sysclk_freq;1450 1451 if (rd->mcasp->slot_width)1452 sbits = rd->mcasp->slot_width;1453 1454 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,1455 sbits * slots * rate,1456 false);1457 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {1458 snd_mask_set_format(&nfmt, i);1459 count++;1460 }1461 }1462 }1463 dev_dbg(rd->mcasp->dev,1464 "%d possible sample format for %d Hz and %d tdm slots\n",1465 count, rate, slots);1466 1467 return snd_mask_refine(fmt, &nfmt);1468}1469 1470static int davinci_mcasp_hw_rule_min_periodsize(1471 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)1472{1473 struct snd_interval *period_size = hw_param_interval(params,1474 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);1475 u8 numevt = *((u8 *)rule->private);1476 struct snd_interval frames;1477 1478 snd_interval_any(&frames);1479 frames.min = numevt;1480 frames.integer = 1;1481 1482 return snd_interval_refine(period_size, &frames);1483}1484 1485static int davinci_mcasp_startup(struct snd_pcm_substream *substream,1486 struct snd_soc_dai *cpu_dai)1487{1488 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1489 struct davinci_mcasp_ruledata *ruledata =1490 &mcasp->ruledata[substream->stream];1491 u32 max_channels = 0;1492 int i, dir, ret;1493 int tdm_slots = mcasp->tdm_slots;1494 u8 *numevt;1495 1496 /* Do not allow more then one stream per direction */1497 if (mcasp->substreams[substream->stream])1498 return -EBUSY;1499 1500 mcasp->substreams[substream->stream] = substream;1501 1502 if (mcasp->tdm_mask[substream->stream])1503 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);1504 1505 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)1506 return 0;1507 1508 /*1509 * Limit the maximum allowed channels for the first stream:1510 * number of serializers for the direction * tdm slots per serializer1511 */1512 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)1513 dir = TX_MODE;1514 else1515 dir = RX_MODE;1516 1517 for (i = 0; i < mcasp->num_serializer; i++) {1518 if (mcasp->serial_dir[i] == dir)1519 max_channels++;1520 }1521 ruledata->serializers = max_channels;1522 ruledata->mcasp = mcasp;1523 max_channels *= tdm_slots;1524 /*1525 * If the already active stream has less channels than the calculated1526 * limit based on the seirializers * tdm_slots, and only one serializer1527 * is in use we need to use that as a constraint for the second stream.1528 * Otherwise (first stream or less allowed channels or more than one1529 * serializer in use) we use the calculated constraint.1530 */1531 if (mcasp->channels && mcasp->channels < max_channels &&1532 ruledata->serializers == 1)1533 max_channels = mcasp->channels;1534 /*1535 * But we can always allow channels upto the amount of1536 * the available tdm_slots.1537 */1538 if (max_channels < tdm_slots)1539 max_channels = tdm_slots;1540 1541 snd_pcm_hw_constraint_minmax(substream->runtime,1542 SNDRV_PCM_HW_PARAM_CHANNELS,1543 0, max_channels);1544 1545 snd_pcm_hw_constraint_list(substream->runtime,1546 0, SNDRV_PCM_HW_PARAM_CHANNELS,1547 &mcasp->chconstr[substream->stream]);1548 1549 if (mcasp->max_format_width) {1550 /*1551 * Only allow formats which require same amount of bits on the1552 * bus as the currently running stream1553 */1554 ret = snd_pcm_hw_rule_add(substream->runtime, 0,1555 SNDRV_PCM_HW_PARAM_FORMAT,1556 davinci_mcasp_hw_rule_format_width,1557 ruledata,1558 SNDRV_PCM_HW_PARAM_FORMAT, -1);1559 if (ret)1560 return ret;1561 }1562 else if (mcasp->slot_width) {1563 /* Only allow formats require <= slot_width bits on the bus */1564 ret = snd_pcm_hw_rule_add(substream->runtime, 0,1565 SNDRV_PCM_HW_PARAM_FORMAT,1566 davinci_mcasp_hw_rule_slot_width,1567 ruledata,1568 SNDRV_PCM_HW_PARAM_FORMAT, -1);1569 if (ret)1570 return ret;1571 }1572 1573 /*1574 * If we rely on implicit BCLK divider setting we should1575 * set constraints based on what we can provide.1576 */1577 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {1578 ret = snd_pcm_hw_rule_add(substream->runtime, 0,1579 SNDRV_PCM_HW_PARAM_RATE,1580 davinci_mcasp_hw_rule_rate,1581 ruledata,1582 SNDRV_PCM_HW_PARAM_FORMAT, -1);1583 if (ret)1584 return ret;1585 ret = snd_pcm_hw_rule_add(substream->runtime, 0,1586 SNDRV_PCM_HW_PARAM_FORMAT,1587 davinci_mcasp_hw_rule_format,1588 ruledata,1589 SNDRV_PCM_HW_PARAM_RATE, -1);1590 if (ret)1591 return ret;1592 }1593 1594 numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?1595 &mcasp->txnumevt :1596 &mcasp->rxnumevt;1597 snd_pcm_hw_rule_add(substream->runtime, 0,1598 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,1599 davinci_mcasp_hw_rule_min_periodsize, numevt,1600 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);1601 1602 return 0;1603}1604 1605static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,1606 struct snd_soc_dai *cpu_dai)1607{1608 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1609 1610 mcasp->substreams[substream->stream] = NULL;1611 mcasp->active_serializers[substream->stream] = 0;1612 1613 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)1614 return;1615 1616 if (!snd_soc_dai_active(cpu_dai)) {1617 mcasp->channels = 0;1618 mcasp->max_format_width = 0;1619 }1620}1621 1622static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol,1623 struct snd_ctl_elem_info *uinfo)1624{1625 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;1626 uinfo->count = 1;1627 1628 return 0;1629}1630 1631static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol,1632 struct snd_ctl_elem_value *uctl)1633{1634 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1635 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1636 1637 memcpy(uctl->value.iec958.status, &mcasp->iec958_status,1638 sizeof(mcasp->iec958_status));1639 1640 return 0;1641}1642 1643static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol,1644 struct snd_ctl_elem_value *uctl)1645{1646 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1647 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1648 1649 memcpy(&mcasp->iec958_status, uctl->value.iec958.status,1650 sizeof(mcasp->iec958_status));1651 1652 return 0;1653}1654 1655static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol,1656 struct snd_ctl_elem_value *ucontrol)1657{1658 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1659 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);1660 1661 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status));1662 return 0;1663}1664 1665static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = {1666 {1667 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |1668 SNDRV_CTL_ELEM_ACCESS_VOLATILE),1669 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1670 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),1671 .info = davinci_mcasp_iec958_info,1672 .get = davinci_mcasp_iec958_get,1673 .put = davinci_mcasp_iec958_put,1674 }, {1675 .access = SNDRV_CTL_ELEM_ACCESS_READ,1676 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,1677 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),1678 .info = davinci_mcasp_iec958_info,1679 .get = davinci_mcasp_iec958_con_mask_get,1680 },1681};1682 1683static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp)1684{1685 unsigned char *cs = (u8 *)&mcasp->iec958_status;1686 1687 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;1688 cs[1] = IEC958_AES1_CON_PCM_CODER;1689 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;1690 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM;1691}1692 1693static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)1694{1695 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);1696 int stream;1697 1698 for_each_pcm_streams(stream)1699 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]);1700 1701 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) {1702 davinci_mcasp_init_iec958_status(mcasp);1703 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls,1704 ARRAY_SIZE(davinci_mcasp_iec958_ctls));1705 }1706 1707 return 0;1708}1709 1710static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {1711 .probe = davinci_mcasp_dai_probe,1712 .startup = davinci_mcasp_startup,1713 .shutdown = davinci_mcasp_shutdown,1714 .trigger = davinci_mcasp_trigger,1715 .delay = davinci_mcasp_delay,1716 .hw_params = davinci_mcasp_hw_params,1717 .set_fmt = davinci_mcasp_set_dai_fmt,1718 .set_clkdiv = davinci_mcasp_set_clkdiv,1719 .set_sysclk = davinci_mcasp_set_sysclk,1720 .set_tdm_slot = davinci_mcasp_set_tdm_slot,1721};1722 1723#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_1920001724 1725#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \1726 SNDRV_PCM_FMTBIT_U8 | \1727 SNDRV_PCM_FMTBIT_S16_LE | \1728 SNDRV_PCM_FMTBIT_U16_LE | \1729 SNDRV_PCM_FMTBIT_S24_LE | \1730 SNDRV_PCM_FMTBIT_U24_LE | \1731 SNDRV_PCM_FMTBIT_S24_3LE | \1732 SNDRV_PCM_FMTBIT_U24_3LE | \1733 SNDRV_PCM_FMTBIT_S32_LE | \1734 SNDRV_PCM_FMTBIT_U32_LE)1735 1736static struct snd_soc_dai_driver davinci_mcasp_dai[] = {1737 {1738 .name = "davinci-mcasp.0",1739 .playback = {1740 .stream_name = "IIS Playback",1741 .channels_min = 1,1742 .channels_max = 32 * 16,1743 .rates = DAVINCI_MCASP_RATES,1744 .formats = DAVINCI_MCASP_PCM_FMTS,1745 },1746 .capture = {1747 .stream_name = "IIS Capture",1748 .channels_min = 1,1749 .channels_max = 32 * 16,1750 .rates = DAVINCI_MCASP_RATES,1751 .formats = DAVINCI_MCASP_PCM_FMTS,1752 },1753 .ops = &davinci_mcasp_dai_ops,1754 1755 .symmetric_rate = 1,1756 },1757 {1758 .name = "davinci-mcasp.1",1759 .playback = {1760 .stream_name = "DIT Playback",1761 .channels_min = 1,1762 .channels_max = 384,1763 .rates = DAVINCI_MCASP_RATES,1764 .formats = SNDRV_PCM_FMTBIT_S16_LE |1765 SNDRV_PCM_FMTBIT_S24_LE,1766 },1767 .ops = &davinci_mcasp_dai_ops,1768 },1769 1770};1771 1772static const struct snd_soc_component_driver davinci_mcasp_component = {1773 .name = "davinci-mcasp",1774 .legacy_dai_naming = 1,1775};1776 1777/* Some HW specific values and defaults. The rest is filled in from DT. */1778static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {1779 .tx_dma_offset = 0x400,1780 .rx_dma_offset = 0x400,1781 .version = MCASP_VERSION_1,1782};1783 1784static struct davinci_mcasp_pdata da830_mcasp_pdata = {1785 .tx_dma_offset = 0x2000,1786 .rx_dma_offset = 0x2000,1787 .version = MCASP_VERSION_2,1788};1789 1790static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {1791 .tx_dma_offset = 0,1792 .rx_dma_offset = 0,1793 .version = MCASP_VERSION_3,1794};1795 1796static struct davinci_mcasp_pdata dra7_mcasp_pdata = {1797 /* The CFG port offset will be calculated if it is needed */1798 .tx_dma_offset = 0,1799 .rx_dma_offset = 0,1800 .version = MCASP_VERSION_4,1801};1802 1803static struct davinci_mcasp_pdata omap_mcasp_pdata = {1804 .tx_dma_offset = 0x200,1805 .rx_dma_offset = 0,1806 .version = MCASP_VERSION_OMAP,1807};1808 1809static const struct of_device_id mcasp_dt_ids[] = {1810 {1811 .compatible = "ti,dm646x-mcasp-audio",1812 .data = &dm646x_mcasp_pdata,1813 },1814 {1815 .compatible = "ti,da830-mcasp-audio",1816 .data = &da830_mcasp_pdata,1817 },1818 {1819 .compatible = "ti,am33xx-mcasp-audio",1820 .data = &am33xx_mcasp_pdata,1821 },1822 {1823 .compatible = "ti,dra7-mcasp-audio",1824 .data = &dra7_mcasp_pdata,1825 },1826 {1827 .compatible = "ti,omap4-mcasp-audio",1828 .data = &omap_mcasp_pdata,1829 },1830 { /* sentinel */ }1831};1832MODULE_DEVICE_TABLE(of, mcasp_dt_ids);1833 1834static int mcasp_reparent_fck(struct platform_device *pdev)1835{1836 struct device_node *node = pdev->dev.of_node;1837 struct clk *gfclk, *parent_clk;1838 const char *parent_name;1839 int ret;1840 1841 if (!node)1842 return 0;1843 1844 parent_name = of_get_property(node, "fck_parent", NULL);1845 if (!parent_name)1846 return 0;1847 1848 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");1849 1850 gfclk = clk_get(&pdev->dev, "fck");1851 if (IS_ERR(gfclk)) {1852 dev_err(&pdev->dev, "failed to get fck\n");1853 return PTR_ERR(gfclk);1854 }1855 1856 parent_clk = clk_get(NULL, parent_name);1857 if (IS_ERR(parent_clk)) {1858 dev_err(&pdev->dev, "failed to get parent clock\n");1859 ret = PTR_ERR(parent_clk);1860 goto err1;1861 }1862 1863 ret = clk_set_parent(gfclk, parent_clk);1864 if (ret) {1865 dev_err(&pdev->dev, "failed to reparent fck\n");1866 goto err2;1867 }1868 1869err2:1870 clk_put(parent_clk);1871err1:1872 clk_put(gfclk);1873 return ret;1874}1875 1876static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp)1877{1878#ifdef CONFIG_OF_GPIO1879 return of_property_read_bool(mcasp->dev->of_node, "gpio-controller");1880#else1881 return false;1882#endif1883}1884 1885static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp,1886 struct platform_device *pdev)1887{1888 struct device_node *np = pdev->dev.of_node;1889 struct davinci_mcasp_pdata *pdata = NULL;1890 const struct davinci_mcasp_pdata *match_pdata =1891 device_get_match_data(&pdev->dev);1892 const u32 *of_serial_dir32;1893 u32 val;1894 int i;1895 1896 if (pdev->dev.platform_data) {1897 pdata = pdev->dev.platform_data;1898 pdata->dismod = DISMOD_LOW;1899 goto out;1900 } else if (match_pdata) {1901 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata),1902 GFP_KERNEL);1903 if (!pdata)1904 return -ENOMEM;1905 } else {1906 dev_err(&pdev->dev, "No compatible match found\n");1907 return -EINVAL;1908 }1909 1910 if (of_property_read_u32(np, "op-mode", &val) == 0) {1911 pdata->op_mode = val;1912 } else {1913 mcasp->missing_audio_param = true;1914 goto out;1915 }1916 1917 if (of_property_read_u32(np, "tdm-slots", &val) == 0) {1918 if (val < 2 || val > 32) {1919 dev_err(&pdev->dev, "tdm-slots must be in rage [2-32]\n");1920 return -EINVAL;1921 }1922 1923 pdata->tdm_slots = val;1924 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) {1925 mcasp->missing_audio_param = true;1926 goto out;1927 }1928 1929 of_serial_dir32 = of_get_property(np, "serial-dir", &val);1930 val /= sizeof(u32);1931 if (of_serial_dir32) {1932 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,1933 (sizeof(*of_serial_dir) * val),1934 GFP_KERNEL);1935 if (!of_serial_dir)1936 return -ENOMEM;1937 1938 for (i = 0; i < val; i++)1939 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);1940 1941 pdata->num_serializer = val;1942 pdata->serial_dir = of_serial_dir;1943 } else {1944 mcasp->missing_audio_param = true;1945 goto out;1946 }1947 1948 if (of_property_read_u32(np, "tx-num-evt", &val) == 0)1949 pdata->txnumevt = val;1950 1951 if (of_property_read_u32(np, "rx-num-evt", &val) == 0)1952 pdata->rxnumevt = val;1953 1954 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0)1955 mcasp->auxclk_fs_ratio = val;1956 1957 if (of_property_read_u32(np, "dismod", &val) == 0) {1958 if (val == 0 || val == 2 || val == 3) {1959 pdata->dismod = DISMOD_VAL(val);1960 } else {1961 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);1962 pdata->dismod = DISMOD_LOW;1963 }1964 } else {1965 pdata->dismod = DISMOD_LOW;1966 }1967 1968out:1969 mcasp->pdata = pdata;1970 1971 if (mcasp->missing_audio_param) {1972 if (davinci_mcasp_have_gpiochip(mcasp)) {1973 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n");1974 return 0;1975 }1976 1977 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n");1978 return -ENODEV;1979 }1980 1981 mcasp->op_mode = pdata->op_mode;1982 /* sanity check for tdm slots parameter */1983 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {1984 if (pdata->tdm_slots < 2) {1985 dev_warn(&pdev->dev, "invalid tdm slots: %d\n",1986 pdata->tdm_slots);1987 mcasp->tdm_slots = 2;1988 } else if (pdata->tdm_slots > 32) {1989 dev_warn(&pdev->dev, "invalid tdm slots: %d\n",1990 pdata->tdm_slots);1991 mcasp->tdm_slots = 32;1992 } else {1993 mcasp->tdm_slots = pdata->tdm_slots;1994 }1995 } else {1996 mcasp->tdm_slots = 32;1997 }1998 1999 mcasp->num_serializer = pdata->num_serializer;2000#ifdef CONFIG_PM2001 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,2002 mcasp->num_serializer, sizeof(u32),2003 GFP_KERNEL);2004 if (!mcasp->context.xrsr_regs)2005 return -ENOMEM;2006#endif2007 mcasp->serial_dir = pdata->serial_dir;2008 mcasp->version = pdata->version;2009 mcasp->txnumevt = pdata->txnumevt;2010 mcasp->rxnumevt = pdata->rxnumevt;2011 mcasp->dismod = pdata->dismod;2012 2013 return 0;2014}2015 2016enum {2017 PCM_EDMA,2018 PCM_SDMA,2019 PCM_UDMA,2020};2021static const char *sdma_prefix = "ti,omap";2022 2023static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)2024{2025 struct dma_chan *chan;2026 const char *tmp;2027 int ret = PCM_EDMA;2028 2029 if (!mcasp->dev->of_node)2030 return PCM_EDMA;2031 2032 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;2033 chan = dma_request_chan(mcasp->dev, tmp);2034 if (IS_ERR(chan))2035 return dev_err_probe(mcasp->dev, PTR_ERR(chan),2036 "Can't verify DMA configuration\n");2037 if (WARN_ON(!chan->device || !chan->device->dev)) {2038 dma_release_channel(chan);2039 return -EINVAL;2040 }2041 2042 if (chan->device->dev->of_node)2043 ret = of_property_read_string(chan->device->dev->of_node,2044 "compatible", &tmp);2045 else2046 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");2047 2048 dma_release_channel(chan);2049 if (ret)2050 return ret;2051 2052 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);2053 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))2054 return PCM_SDMA;2055 else if (strstr(tmp, "udmap"))2056 return PCM_UDMA;2057 else if (strstr(tmp, "bcdma"))2058 return PCM_UDMA;2059 2060 return PCM_EDMA;2061}2062 2063static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)2064{2065 int i;2066 u32 offset = 0;2067 2068 if (pdata->version != MCASP_VERSION_4)2069 return pdata->tx_dma_offset;2070 2071 for (i = 0; i < pdata->num_serializer; i++) {2072 if (pdata->serial_dir[i] == TX_MODE) {2073 if (!offset) {2074 offset = DAVINCI_MCASP_TXBUF_REG(i);2075 } else {2076 pr_err("%s: Only one serializer allowed!\n",2077 __func__);2078 break;2079 }2080 }2081 }2082 2083 return offset;2084}2085 2086static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)2087{2088 int i;2089 u32 offset = 0;2090 2091 if (pdata->version != MCASP_VERSION_4)2092 return pdata->rx_dma_offset;2093 2094 for (i = 0; i < pdata->num_serializer; i++) {2095 if (pdata->serial_dir[i] == RX_MODE) {2096 if (!offset) {2097 offset = DAVINCI_MCASP_RXBUF_REG(i);2098 } else {2099 pr_err("%s: Only one serializer allowed!\n",2100 __func__);2101 break;2102 }2103 }2104 }2105 2106 return offset;2107}2108 2109#ifdef CONFIG_GPIOLIB2110static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)2111{2112 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2113 2114 if (mcasp->num_serializer && offset < mcasp->num_serializer &&2115 mcasp->serial_dir[offset] != INACTIVE_MODE) {2116 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);2117 return -EBUSY;2118 }2119 2120 /* Do not change the PIN yet */2121 return pm_runtime_resume_and_get(mcasp->dev);2122}2123 2124static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)2125{2126 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2127 2128 /* Set the direction to input */2129 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));2130 2131 /* Set the pin as McASP pin */2132 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));2133 2134 pm_runtime_put_sync(mcasp->dev);2135}2136 2137static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,2138 unsigned offset, int value)2139{2140 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2141 u32 val;2142 2143 if (value)2144 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));2145 else2146 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));2147 2148 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);2149 if (!(val & BIT(offset))) {2150 /* Set the pin as GPIO pin */2151 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));2152 2153 /* Set the direction to output */2154 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));2155 }2156 2157 return 0;2158}2159 2160static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,2161 int value)2162{2163 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2164 2165 if (value)2166 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));2167 else2168 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));2169}2170 2171static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,2172 unsigned offset)2173{2174 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2175 u32 val;2176 2177 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);2178 if (!(val & BIT(offset))) {2179 /* Set the direction to input */2180 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));2181 2182 /* Set the pin as GPIO pin */2183 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));2184 }2185 2186 return 0;2187}2188 2189static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)2190{2191 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2192 u32 val;2193 2194 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);2195 if (val & BIT(offset))2196 return 1;2197 2198 return 0;2199}2200 2201static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,2202 unsigned offset)2203{2204 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);2205 u32 val;2206 2207 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);2208 if (val & BIT(offset))2209 return 0;2210 2211 return 1;2212}2213 2214static const struct gpio_chip davinci_mcasp_template_chip = {2215 .owner = THIS_MODULE,2216 .request = davinci_mcasp_gpio_request,2217 .free = davinci_mcasp_gpio_free,2218 .direction_output = davinci_mcasp_gpio_direction_out,2219 .set = davinci_mcasp_gpio_set,2220 .direction_input = davinci_mcasp_gpio_direction_in,2221 .get = davinci_mcasp_gpio_get,2222 .get_direction = davinci_mcasp_gpio_get_direction,2223 .base = -1,2224 .ngpio = 32,2225};2226 2227static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)2228{2229 if (!davinci_mcasp_have_gpiochip(mcasp))2230 return 0;2231 2232 mcasp->gpio_chip = davinci_mcasp_template_chip;2233 mcasp->gpio_chip.label = dev_name(mcasp->dev);2234 mcasp->gpio_chip.parent = mcasp->dev;2235 2236 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);2237}2238 2239#else /* CONFIG_GPIOLIB */2240static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)2241{2242 return 0;2243}2244#endif /* CONFIG_GPIOLIB */2245 2246static int davinci_mcasp_probe(struct platform_device *pdev)2247{2248 struct snd_dmaengine_dai_dma_data *dma_data;2249 struct resource *mem, *dat;2250 struct davinci_mcasp *mcasp;2251 char *irq_name;2252 int irq;2253 int ret;2254 2255 if (!pdev->dev.platform_data && !pdev->dev.of_node) {2256 dev_err(&pdev->dev, "No platform data supplied\n");2257 return -EINVAL;2258 }2259 2260 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),2261 GFP_KERNEL);2262 if (!mcasp)2263 return -ENOMEM;2264 2265 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");2266 if (!mem) {2267 dev_warn(&pdev->dev,2268 "\"mpu\" mem resource not found, using index 0\n");2269 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);2270 if (!mem) {2271 dev_err(&pdev->dev, "no mem resource?\n");2272 return -ENODEV;2273 }2274 }2275 2276 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);2277 if (IS_ERR(mcasp->base))2278 return PTR_ERR(mcasp->base);2279 2280 dev_set_drvdata(&pdev->dev, mcasp);2281 pm_runtime_enable(&pdev->dev);2282 2283 mcasp->dev = &pdev->dev;2284 ret = davinci_mcasp_get_config(mcasp, pdev);2285 if (ret)2286 goto err;2287 2288 /* All PINS as McASP */2289 pm_runtime_get_sync(mcasp->dev);2290 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);2291 pm_runtime_put(mcasp->dev);2292 2293 /* Skip audio related setup code if the configuration is not adequat */2294 if (mcasp->missing_audio_param)2295 goto no_audio;2296 2297 irq = platform_get_irq_byname_optional(pdev, "common");2298 if (irq > 0) {2299 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",2300 dev_name(&pdev->dev));2301 if (!irq_name) {2302 ret = -ENOMEM;2303 goto err;2304 }2305 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,2306 davinci_mcasp_common_irq_handler,2307 IRQF_ONESHOT | IRQF_SHARED,2308 irq_name, mcasp);2309 if (ret) {2310 dev_err(&pdev->dev, "common IRQ request failed\n");2311 goto err;2312 }2313 2314 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;2315 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;2316 }2317 2318 irq = platform_get_irq_byname_optional(pdev, "rx");2319 if (irq > 0) {2320 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",2321 dev_name(&pdev->dev));2322 if (!irq_name) {2323 ret = -ENOMEM;2324 goto err;2325 }2326 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,2327 davinci_mcasp_rx_irq_handler,2328 IRQF_ONESHOT, irq_name, mcasp);2329 if (ret) {2330 dev_err(&pdev->dev, "RX IRQ request failed\n");2331 goto err;2332 }2333 2334 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;2335 }2336 2337 irq = platform_get_irq_byname_optional(pdev, "tx");2338 if (irq > 0) {2339 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",2340 dev_name(&pdev->dev));2341 if (!irq_name) {2342 ret = -ENOMEM;2343 goto err;2344 }2345 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,2346 davinci_mcasp_tx_irq_handler,2347 IRQF_ONESHOT, irq_name, mcasp);2348 if (ret) {2349 dev_err(&pdev->dev, "TX IRQ request failed\n");2350 goto err;2351 }2352 2353 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;2354 }2355 2356 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");2357 if (dat)2358 mcasp->dat_port = true;2359 2360 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];2361 dma_data->filter_data = "tx";2362 if (dat) {2363 dma_data->addr = dat->start;2364 /*2365 * According to the TRM there should be 0x200 offset added to2366 * the DAT port address2367 */2368 if (mcasp->version == MCASP_VERSION_OMAP)2369 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata);2370 } else {2371 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata);2372 }2373 2374 2375 /* RX is not valid in DIT mode */2376 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {2377 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];2378 dma_data->filter_data = "rx";2379 if (dat)2380 dma_data->addr = dat->start;2381 else2382 dma_data->addr =2383 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata);2384 }2385 2386 if (mcasp->version < MCASP_VERSION_3) {2387 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;2388 /* dma_params->dma_addr is pointing to the data port address */2389 mcasp->dat_port = true;2390 } else {2391 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;2392 }2393 2394 /* Allocate memory for long enough list for all possible2395 * scenarios. Maximum number tdm slots is 32 and there cannot2396 * be more serializers than given in the configuration. The2397 * serializer directions could be taken into account, but it2398 * would make code much more complex and save only couple of2399 * bytes.2400 */2401 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =2402 devm_kcalloc(mcasp->dev,2403 32 + mcasp->num_serializer - 1,2404 sizeof(unsigned int),2405 GFP_KERNEL);2406 2407 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =2408 devm_kcalloc(mcasp->dev,2409 32 + mcasp->num_serializer - 1,2410 sizeof(unsigned int),2411 GFP_KERNEL);2412 2413 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||2414 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {2415 ret = -ENOMEM;2416 goto err;2417 }2418 2419 ret = davinci_mcasp_set_ch_constraints(mcasp);2420 if (ret)2421 goto err;2422 2423 mcasp_reparent_fck(pdev);2424 2425 ret = davinci_mcasp_get_dma_type(mcasp);2426 switch (ret) {2427 case PCM_EDMA:2428 ret = edma_pcm_platform_register(&pdev->dev);2429 break;2430 case PCM_SDMA:2431 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)2432 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");2433 else2434 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL);2435 break;2436 case PCM_UDMA:2437 ret = udma_pcm_platform_register(&pdev->dev);2438 break;2439 default:2440 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);2441 fallthrough;2442 case -EPROBE_DEFER:2443 goto err;2444 }2445 2446 if (ret) {2447 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);2448 goto err;2449 }2450 2451 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,2452 &davinci_mcasp_dai[mcasp->op_mode], 1);2453 2454 if (ret != 0)2455 goto err;2456 2457no_audio:2458 ret = davinci_mcasp_init_gpiochip(mcasp);2459 if (ret) {2460 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret);2461 goto err;2462 }2463 2464 return 0;2465err:2466 pm_runtime_disable(&pdev->dev);2467 return ret;2468}2469 2470static void davinci_mcasp_remove(struct platform_device *pdev)2471{2472 pm_runtime_disable(&pdev->dev);2473}2474 2475#ifdef CONFIG_PM2476static int davinci_mcasp_runtime_suspend(struct device *dev)2477{2478 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);2479 struct davinci_mcasp_context *context = &mcasp->context;2480 u32 reg;2481 int i;2482 2483 for (i = 0; i < ARRAY_SIZE(context_regs); i++)2484 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);2485 2486 if (mcasp->txnumevt) {2487 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;2488 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);2489 }2490 if (mcasp->rxnumevt) {2491 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;2492 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);2493 }2494 2495 for (i = 0; i < mcasp->num_serializer; i++)2496 context->xrsr_regs[i] = mcasp_get_reg(mcasp,2497 DAVINCI_MCASP_XRSRCTL_REG(i));2498 2499 return 0;2500}2501 2502static int davinci_mcasp_runtime_resume(struct device *dev)2503{2504 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);2505 struct davinci_mcasp_context *context = &mcasp->context;2506 u32 reg;2507 int i;2508 2509 for (i = 0; i < ARRAY_SIZE(context_regs); i++)2510 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);2511 2512 if (mcasp->txnumevt) {2513 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;2514 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);2515 }2516 if (mcasp->rxnumevt) {2517 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;2518 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);2519 }2520 2521 for (i = 0; i < mcasp->num_serializer; i++)2522 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),2523 context->xrsr_regs[i]);2524 2525 return 0;2526}2527 2528#endif2529 2530static const struct dev_pm_ops davinci_mcasp_pm_ops = {2531 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,2532 davinci_mcasp_runtime_resume,2533 NULL)2534};2535 2536static struct platform_driver davinci_mcasp_driver = {2537 .probe = davinci_mcasp_probe,2538 .remove = davinci_mcasp_remove,2539 .driver = {2540 .name = "davinci-mcasp",2541 .pm = &davinci_mcasp_pm_ops,2542 .of_match_table = mcasp_dt_ids,2543 },2544};2545 2546module_platform_driver(davinci_mcasp_driver);2547 2548MODULE_AUTHOR("Steve Chen");2549MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");2550MODULE_LICENSE("GPL");2551