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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver4 *5 * Copyright (C) 2016 Intel Corp6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>7 * Ramesh Babu K V <ramesh.babu@intel.com>8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>9 * Jerome Anand <jerome.anand@intel.com>10 * Aravind Siddappaji <aravindx.siddappaji@intel.com>11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~12 *13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~14 */15#ifndef __INTEL_HDMI_LPE_AUDIO_H16#define __INTEL_HDMI_LPE_AUDIO_H17 18#define HAD_MIN_CHANNEL 219#define HAD_MAX_CHANNEL 820#define HAD_NUM_OF_RING_BUFS 421 22/* max 20bit address, aligned to 64 */23#define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f)24#define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */25#define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */26#define HAD_MIN_PERIODS 127#define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)28#define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */29#define HAD_FIFO_SIZE 0 /* fifo not being used */30#define MAX_SPEAKERS 831 32#define AUD_SAMPLE_RATE_32 3200033#define AUD_SAMPLE_RATE_44_1 4410034#define AUD_SAMPLE_RATE_48 4800035#define AUD_SAMPLE_RATE_88_2 8820036#define AUD_SAMPLE_RATE_96 9600037#define AUD_SAMPLE_RATE_176_4 17640038#define AUD_SAMPLE_RATE_192 19200039 40#define HAD_MIN_RATE AUD_SAMPLE_RATE_3241#define HAD_MAX_RATE AUD_SAMPLE_RATE_19242 43#define DIS_SAMPLE_RATE_25_2 2520044#define DIS_SAMPLE_RATE_27 2700045#define DIS_SAMPLE_RATE_54 5400046#define DIS_SAMPLE_RATE_74_25 7425047#define DIS_SAMPLE_RATE_148_5 14850048#define HAD_REG_WIDTH 0x0849#define HAD_MAX_DIP_WORDS 1650 51/* DP Link Rates */52#define DP_2_7_GHZ 27000053#define DP_1_62_GHZ 16200054 55/* Maud Values */56#define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 198857#define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 274058#define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 298259#define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 548060#define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 596561#define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 1096162#define HAD_MAX_RATE_DP_2_7_MAUD_VAL 1193063#define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 331464#define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 456765#define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 497166#define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 913467#define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 994268#define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 1826869#define HAD_MAX_RATE_DP_1_62_MAUD_VAL 1988470 71/* Naud Value */72#define DP_NAUD_VAL 3276873 74/* HDMI Controller register offsets - audio domain common */75/* Base address for below regs = 0x65000 */76enum hdmi_ctrl_reg_offset_common {77 AUDIO_HDMI_CONFIG_A = 0x000,78 AUDIO_HDMI_CONFIG_B = 0x800,79 AUDIO_HDMI_CONFIG_C = 0x900,80};81/* HDMI controller register offsets */82enum hdmi_ctrl_reg_offset {83 AUD_CONFIG = 0x0,84 AUD_CH_STATUS_0 = 0x08,85 AUD_CH_STATUS_1 = 0x0C,86 AUD_HDMI_CTS = 0x10,87 AUD_N_ENABLE = 0x14,88 AUD_SAMPLE_RATE = 0x18,89 AUD_BUF_CONFIG = 0x20,90 AUD_BUF_CH_SWAP = 0x24,91 AUD_BUF_A_ADDR = 0x40,92 AUD_BUF_A_LENGTH = 0x44,93 AUD_BUF_B_ADDR = 0x48,94 AUD_BUF_B_LENGTH = 0x4c,95 AUD_BUF_C_ADDR = 0x50,96 AUD_BUF_C_LENGTH = 0x54,97 AUD_BUF_D_ADDR = 0x58,98 AUD_BUF_D_LENGTH = 0x5c,99 AUD_CNTL_ST = 0x60,100 AUD_HDMI_STATUS = 0x64, /* v2 */101 AUD_HDMIW_INFOFR = 0x68, /* v2 */102};103 104/* Audio configuration */105union aud_cfg {106 struct {107 u32 aud_en:1;108 u32 layout:1; /* LAYOUT[01], see below */109 u32 fmt:2;110 u32 num_ch:3;111 u32 set:1;112 u32 flat:1;113 u32 val_bit:1;114 u32 user_bit:1;115 u32 underrun:1; /* 0: send null packets,116 * 1: send silence stream117 */118 u32 packet_mode:1; /* 0: 32bit container, 1: 16bit */119 u32 left_align:1; /* 0: MSB bits 0-23, 1: bits 8-31 */120 u32 bogus_sample:1; /* bogus sample for odd channels */121 u32 dp_modei:1; /* 0: HDMI, 1: DP */122 u32 rsvd:16;123 } regx;124 u32 regval;125};126 127#define AUD_CONFIG_VALID_BIT (1 << 9)128#define AUD_CONFIG_DP_MODE (1 << 15)129#define AUD_CONFIG_CH_MASK 0x70130#define LAYOUT0 0 /* interleaved stereo */131#define LAYOUT1 1 /* for channels > 2 */132 133/* Audio Channel Status 0 Attributes */134union aud_ch_status_0 {135 struct {136 u32 ch_status:1;137 u32 lpcm_id:1;138 u32 cp_info:1;139 u32 format:3;140 u32 mode:2;141 u32 ctg_code:8;142 u32 src_num:4;143 u32 ch_num:4;144 u32 samp_freq:4; /* CH_STATUS_MAP_XXX */145 u32 clk_acc:2;146 u32 rsvd:2;147 } regx;148 u32 regval;149};150 151/* samp_freq values - Sampling rate as per IEC60958 Ver 3 */152#define CH_STATUS_MAP_32KHZ 0x3153#define CH_STATUS_MAP_44KHZ 0x0154#define CH_STATUS_MAP_48KHZ 0x2155#define CH_STATUS_MAP_88KHZ 0x8156#define CH_STATUS_MAP_96KHZ 0xA157#define CH_STATUS_MAP_176KHZ 0xC158#define CH_STATUS_MAP_192KHZ 0xE159 160/* Audio Channel Status 1 Attributes */161union aud_ch_status_1 {162 struct {163 u32 max_wrd_len:1;164 u32 wrd_len:3;165 u32 rsvd:28;166 } regx;167 u32 regval;168};169 170#define MAX_SMPL_WIDTH_20 0x0171#define MAX_SMPL_WIDTH_24 0x1172#define SMPL_WIDTH_16BITS 0x1173#define SMPL_WIDTH_24BITS 0x5174 175/* CTS register */176union aud_hdmi_cts {177 struct {178 u32 cts_val:24;179 u32 en_cts_prog:1;180 u32 rsvd:7;181 } regx;182 u32 regval;183};184 185/* N register */186union aud_hdmi_n_enable {187 struct {188 u32 n_val:24;189 u32 en_n_prog:1;190 u32 rsvd:7;191 } regx;192 u32 regval;193};194 195/* Audio Buffer configurations */196union aud_buf_config {197 struct {198 u32 audio_fifo_watermark:8;199 u32 dma_fifo_watermark:3;200 u32 rsvd0:5;201 u32 aud_delay:8;202 u32 rsvd1:8;203 } regx;204 u32 regval;205};206 207#define FIFO_THRESHOLD 0xFE208#define DMA_FIFO_THRESHOLD 0x7209 210/* Audio Sample Swapping offset */211union aud_buf_ch_swap {212 struct {213 u32 first_0:3;214 u32 second_0:3;215 u32 first_1:3;216 u32 second_1:3;217 u32 first_2:3;218 u32 second_2:3;219 u32 first_3:3;220 u32 second_3:3;221 u32 rsvd:8;222 } regx;223 u32 regval;224};225 226#define SWAP_LFE_CENTER 0x00fac4c8 /* octal 76543210 */227 228/* Address for Audio Buffer */229union aud_buf_addr {230 struct {231 u32 valid:1;232 u32 intr_en:1;233 u32 rsvd:4;234 u32 addr:26;235 } regx;236 u32 regval;237};238 239#define AUD_BUF_VALID (1U << 0)240#define AUD_BUF_INTR_EN (1U << 1)241 242/* Length of Audio Buffer */243union aud_buf_len {244 struct {245 u32 buf_len:20;246 u32 rsvd:12;247 } regx;248 u32 regval;249};250 251/* Audio Control State Register offset */252union aud_ctrl_st {253 struct {254 u32 ram_addr:4;255 u32 eld_ack:1;256 u32 eld_addr:4;257 u32 eld_buf_size:5;258 u32 eld_valid:1;259 u32 cp_ready:1;260 u32 dip_freq:2;261 u32 dip_idx:3;262 u32 dip_en_sta:4;263 u32 rsvd:7;264 } regx;265 u32 regval;266};267 268/* Audio HDMI Widget Data Island Packet offset */269union aud_info_frame1 {270 struct {271 u32 pkt_type:8;272 u32 ver_num:8;273 u32 len:5;274 u32 rsvd:11;275 } regx;276 u32 regval;277};278 279#define HDMI_INFO_FRAME_WORD1 0x000a0184280#define DP_INFO_FRAME_WORD1 0x00441b84281 282/* DIP frame 2 */283union aud_info_frame2 {284 struct {285 u32 chksum:8;286 u32 chnl_cnt:3;287 u32 rsvd0:1;288 u32 coding_type:4;289 u32 smpl_size:2;290 u32 smpl_freq:3;291 u32 rsvd1:3;292 u32 format:8;293 } regx;294 u32 regval;295};296 297/* DIP frame 3 */298union aud_info_frame3 {299 struct {300 u32 chnl_alloc:8;301 u32 rsvd0:3;302 u32 lsv:4;303 u32 dm_inh:1;304 u32 rsvd1:16;305 } regx;306 u32 regval;307};308 309#define VALID_DIP_WORDS 3310 311/* AUD_HDMI_STATUS bits */312#define HDMI_AUDIO_UNDERRUN (1U << 31)313#define HDMI_AUDIO_BUFFER_DONE (1U << 29)314 315/* AUD_HDMI_STATUS register mask */316#define AUD_HDMI_STATUS_MASK_UNDERRUN 0xC0000000317#define AUD_HDMI_STATUS_MASK_SRDBG 0x00000002318#define AUD_HDMI_STATUSG_MASK_FUNCRST 0x00000001319 320#endif321