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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */2/*3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University4 * Author: Christoffer Dall <c.dall@virtualopensystems.com>5 *6 * This program is free software; you can redistribute it and/or modify7 * it under the terms of the GNU General Public License, version 2, as8 * published by the Free Software Foundation.9 *10 * This program is distributed in the hope that it will be useful,11 * but WITHOUT ANY WARRANTY; without even the implied warranty of12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13 * GNU General Public License for more details.14 *15 * You should have received a copy of the GNU General Public License16 * along with this program; if not, write to the Free Software17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.18 */19 20#ifndef __ARM_KVM_H__21#define __ARM_KVM_H__22 23#include <linux/types.h>24#include <linux/psci.h>25#include <asm/ptrace.h>26 27#define __KVM_HAVE_GUEST_DEBUG28#define __KVM_HAVE_IRQ_LINE29#define __KVM_HAVE_READONLY_MEM30#define __KVM_HAVE_VCPU_EVENTS31 32#define KVM_COALESCED_MMIO_PAGE_OFFSET 133 34#define KVM_REG_SIZE(id) \35 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))36 37/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */38#define KVM_ARM_SVC_sp svc_regs[0]39#define KVM_ARM_SVC_lr svc_regs[1]40#define KVM_ARM_SVC_spsr svc_regs[2]41#define KVM_ARM_ABT_sp abt_regs[0]42#define KVM_ARM_ABT_lr abt_regs[1]43#define KVM_ARM_ABT_spsr abt_regs[2]44#define KVM_ARM_UND_sp und_regs[0]45#define KVM_ARM_UND_lr und_regs[1]46#define KVM_ARM_UND_spsr und_regs[2]47#define KVM_ARM_IRQ_sp irq_regs[0]48#define KVM_ARM_IRQ_lr irq_regs[1]49#define KVM_ARM_IRQ_spsr irq_regs[2]50 51/* Valid only for fiq_regs in struct kvm_regs */52#define KVM_ARM_FIQ_r8 fiq_regs[0]53#define KVM_ARM_FIQ_r9 fiq_regs[1]54#define KVM_ARM_FIQ_r10 fiq_regs[2]55#define KVM_ARM_FIQ_fp fiq_regs[3]56#define KVM_ARM_FIQ_ip fiq_regs[4]57#define KVM_ARM_FIQ_sp fiq_regs[5]58#define KVM_ARM_FIQ_lr fiq_regs[6]59#define KVM_ARM_FIQ_spsr fiq_regs[7]60 61struct kvm_regs {62 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */63 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */64 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */65 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */66 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */67 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */68};69 70/* Supported Processor Types */71#define KVM_ARM_TARGET_CORTEX_A15 072#define KVM_ARM_TARGET_CORTEX_A7 173#define KVM_ARM_NUM_TARGETS 274 75/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */76#define KVM_ARM_DEVICE_TYPE_SHIFT 077#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)78#define KVM_ARM_DEVICE_ID_SHIFT 1679#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)80 81/* Supported device IDs */82#define KVM_ARM_DEVICE_VGIC_V2 083 84/* Supported VGIC address types */85#define KVM_VGIC_V2_ADDR_TYPE_DIST 086#define KVM_VGIC_V2_ADDR_TYPE_CPU 187 88#define KVM_VGIC_V2_DIST_SIZE 0x100089#define KVM_VGIC_V2_CPU_SIZE 0x200090 91/* Supported VGICv3 address types */92#define KVM_VGIC_V3_ADDR_TYPE_DIST 293#define KVM_VGIC_V3_ADDR_TYPE_REDIST 394#define KVM_VGIC_ITS_ADDR_TYPE 495#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 596 97#define KVM_VGIC_V3_DIST_SIZE SZ_64K98#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)99#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)100 101#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */102#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */103 104struct kvm_vcpu_init {105 __u32 target;106 __u32 features[7];107};108 109struct kvm_sregs {110};111 112struct kvm_fpu {113};114 115struct kvm_guest_debug_arch {116};117 118struct kvm_debug_exit_arch {119};120 121struct kvm_sync_regs {122 /* Used with KVM_CAP_ARM_USER_IRQ */123 __u64 device_irq_level;124};125 126struct kvm_arch_memory_slot {127};128 129/* for KVM_GET/SET_VCPU_EVENTS */130struct kvm_vcpu_events {131 struct {132 __u8 serror_pending;133 __u8 serror_has_esr;134 __u8 ext_dabt_pending;135 /* Align it to 8 bytes */136 __u8 pad[5];137 __u64 serror_esr;138 } exception;139 __u32 reserved[12];140};141 142/* If you need to interpret the index values, here is the key: */143#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000144#define KVM_REG_ARM_COPROC_SHIFT 16145#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007146#define KVM_REG_ARM_32_OPC2_SHIFT 0147#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078148#define KVM_REG_ARM_OPC1_SHIFT 3149#define KVM_REG_ARM_CRM_MASK 0x0000000000000780150#define KVM_REG_ARM_CRM_SHIFT 7151#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800152#define KVM_REG_ARM_32_CRN_SHIFT 11153/*154 * For KVM currently all guest registers are nonsecure, but we reserve a bit155 * in the encoding to distinguish secure from nonsecure for AArch32 system156 * registers that are banked by security. This is 1 for the secure banked157 * register, and 0 for the nonsecure banked register or if the register is158 * not banked by security.159 */160#define KVM_REG_ARM_SECURE_MASK 0x0000000010000000161#define KVM_REG_ARM_SECURE_SHIFT 28162 163#define ARM_CP15_REG_SHIFT_MASK(x,n) \164 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)165 166#define __ARM_CP15_REG(op1,crn,crm,op2) \167 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \168 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \169 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \171 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))172 173#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)174 175#define __ARM_CP15_REG64(op1,crm) \176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)177#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)178 179/* PL1 Physical Timer Registers */180#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)181#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)182#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)183 184/* Virtual Timer Registers */185#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)186#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)187#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)188 189/* Normal registers are mapped as coprocessor 16. */190#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)191#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)192 193/* Some registers need more space to represent values. */194#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)195#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00196#define KVM_REG_ARM_DEMUX_ID_SHIFT 8197#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)198#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF199#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0200 201/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */202#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)203#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF204#define KVM_REG_ARM_VFP_BASE_REG 0x0205#define KVM_REG_ARM_VFP_FPSID 0x1000206#define KVM_REG_ARM_VFP_FPSCR 0x1001207#define KVM_REG_ARM_VFP_MVFR1 0x1006208#define KVM_REG_ARM_VFP_MVFR0 0x1007209#define KVM_REG_ARM_VFP_FPEXC 0x1008210#define KVM_REG_ARM_VFP_FPINST 0x1009211#define KVM_REG_ARM_VFP_FPINST2 0x100A212 213/* KVM-as-firmware specific pseudo-registers */214#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)215#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \216 KVM_REG_ARM_FW | ((r) & 0xffff))217#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)218#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)219 /* Higher values mean better protection. */220#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0221#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1222#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2223#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)224 /* Higher values mean better protection. */225#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0226#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1227#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2228#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3229#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)230 231/* Device Control API: ARM VGIC */232#define KVM_DEV_ARM_VGIC_GRP_ADDR 0233#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1234#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2235#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32236#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)237#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32238#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \239 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)240#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0241#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)242#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)243#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3244#define KVM_DEV_ARM_VGIC_GRP_CTRL 4245#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5246#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6247#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7248#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8249#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10250#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \251 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)252#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff253#define VGIC_LEVEL_INFO_LINE_LEVEL 0254 255/* Device Control API on vcpu fd */256#define KVM_ARM_VCPU_PMU_V3_CTRL 0257#define KVM_ARM_VCPU_PMU_V3_IRQ 0258#define KVM_ARM_VCPU_PMU_V3_INIT 1259#define KVM_ARM_VCPU_TIMER_CTRL 1260#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0261#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1262 263#define KVM_DEV_ARM_VGIC_CTRL_INIT 0264#define KVM_DEV_ARM_ITS_SAVE_TABLES 1265#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2266#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3267#define KVM_DEV_ARM_ITS_CTRL_RESET 4268 269/* KVM_IRQ_LINE irq field index values */270#define KVM_ARM_IRQ_VCPU2_SHIFT 28271#define KVM_ARM_IRQ_VCPU2_MASK 0xf272#define KVM_ARM_IRQ_TYPE_SHIFT 24273#define KVM_ARM_IRQ_TYPE_MASK 0xf274#define KVM_ARM_IRQ_VCPU_SHIFT 16275#define KVM_ARM_IRQ_VCPU_MASK 0xff276#define KVM_ARM_IRQ_NUM_SHIFT 0277#define KVM_ARM_IRQ_NUM_MASK 0xffff278 279/* irq_type field */280#define KVM_ARM_IRQ_TYPE_CPU 0281#define KVM_ARM_IRQ_TYPE_SPI 1282#define KVM_ARM_IRQ_TYPE_PPI 2283 284/* out-of-kernel GIC cpu interrupt injection irq_number field */285#define KVM_ARM_IRQ_CPU_IRQ 0286#define KVM_ARM_IRQ_CPU_FIQ 1287 288/*289 * This used to hold the highest supported SPI, but it is now obsolete290 * and only here to provide source code level compatibility with older291 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.292 */293#ifndef __KERNEL__294#define KVM_ARM_IRQ_GIC_MAX 127295#endif296 297/* One single KVM irqchip, ie. the VGIC */298#define KVM_NR_IRQCHIPS 1299 300/* PSCI interface */301#define KVM_PSCI_FN_BASE 0x95c1ba5e302#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))303 304#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)305#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)306#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)307#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)308 309#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS310#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED311#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS312#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED313 314#endif /* __ARM_KVM_H__ */315