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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __TOOLS_LINUX_SPARC64_BARRIER_H3#define __TOOLS_LINUX_SPARC64_BARRIER_H4 5/* Copied from the kernel sources to tools/:6 *7 * These are here in an effort to more fully work around Spitfire Errata8 * #51. Essentially, if a memory barrier occurs soon after a mispredicted9 * branch, the chip can stop executing instructions until a trap occurs.10 * Therefore, if interrupts are disabled, the chip can hang forever.11 *12 * It used to be believed that the memory barrier had to be right in the13 * delay slot, but a case has been traced recently wherein the memory barrier14 * was one instruction after the branch delay slot and the chip still hung.15 * The offending sequence was the following in sym_wakeup_done() of the16 * sym53c8xx_2 driver:17 *18 * call sym_ccb_from_dsa, 019 * movge %icc, 0, %l020 * brz,pn %o0, .LL130321 * mov %o0, %l222 * membar #LoadLoad23 *24 * The branch has to be mispredicted for the bug to occur. Therefore, we put25 * the memory barrier explicitly into a "branch always, predicted taken"26 * delay slot to avoid the problem case.27 */28#define membar_safe(type) \29do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \30 " membar " type "\n" \31 "1:\n" \32 : : : "memory"); \33} while (0)34 35/* The kernel always executes in TSO memory model these days,36 * and furthermore most sparc64 chips implement more stringent37 * memory ordering than required by the specifications.38 */39#define mb() membar_safe("#StoreLoad")40#define rmb() __asm__ __volatile__("":::"memory")41#define wmb() __asm__ __volatile__("":::"memory")42 43#define smp_store_release(p, v) \44do { \45 barrier(); \46 WRITE_ONCE(*p, v); \47} while (0)48 49#define smp_load_acquire(p) \50({ \51 typeof(*p) ___p1 = READ_ONCE(*p); \52 barrier(); \53 ___p1; \54})55 56#endif /* !(__TOOLS_LINUX_SPARC64_BARRIER_H) */57