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1# SPDX-License-Identifier: CC0-1.02# Generator: x86-cpuid-db v1.03 4#5# Auto-generated file.6# Please submit all updates and bugfixes to https://x86-cpuid.org7#8 9# The basic row format is:10# LEAF, SUBLEAVES, reg, bits, short_name , long_description11 12# Leaf 0H13# Maximum standard leaf number + CPU vendor string14 15 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 317 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 1118 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 719 20# Leaf 1H21# CPU FMS (Family/Model/Stepping) + standard feature flags22 23 1, 0, eax, 3:0, stepping , Stepping ID24 1, 0, eax, 7:4, base_model , Base CPU model ID25 1, 0, eax, 11:8, base_family_id , Base CPU family ID26 1, 0, eax, 13:12, cpu_type , CPU type27 1, 0, eax, 19:16, ext_model , Extended CPU model ID28 1, 0, eax, 27:20, ext_family , Extended CPU family ID29 1, 0, ebx, 7:0, brand_id , Brand index30 1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size31 1, 0, ebx, 23:16, n_logical_cpu , Logical CPU (HW threads) count32 1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID33 1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)34 1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support35 1, 0, ecx, 2, dtes64 , 64-bit DS save area36 1, 0, ecx, 3, monitor , MONITOR/MWAIT support37 1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store38 1, 0, ecx, 5, vmx , Virtual Machine Extensions39 1, 0, ecx, 6, smx , Safer Mode Extensions40 1, 0, ecx, 7, est , Enhanced Intel SpeedStep41 1, 0, ecx, 8, tm2 , Thermal Monitor 242 1, 0, ecx, 9, ssse3 , Supplemental SSE343 1, 0, ecx, 10, cid , L1 Context ID44 1, 0, ecx, 11, sdbg , Sillicon Debug45 1, 0, ecx, 12, fma , FMA extensions using YMM state46 1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support47 1, 0, ecx, 14, xtpr , xTPR Update Control48 1, 0, ecx, 15, pdcm , Perfmon and Debug Capability49 1, 0, ecx, 17, pcid , Process-context identifiers50 1, 0, ecx, 18, dca , Direct Cache Access51 1, 0, ecx, 19, sse4_1 , SSE4.152 1, 0, ecx, 20, sse4_2 , SSE4.253 1, 0, ecx, 21, x2apic , X2APIC support54 1, 0, ecx, 22, movbe , MOVBE instruction support55 1, 0, ecx, 23, popcnt , POPCNT instruction support56 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation57 1, 0, ecx, 25, aes , AES instructions58 1, 0, ecx, 26, xsave , XSAVE (and related instructions) support59 1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS60 1, 0, ecx, 28, avx , AVX instructions support61 1, 0, ecx, 29, f16c , Half-precision floating-point conversion support62 1, 0, ecx, 30, rdrand , RDRAND instruction support63 1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system64 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)65 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions66 1, 0, edx, 2, de , Debugging Extensions67 1, 0, edx, 3, pse , Page Size Extension68 1, 0, edx, 4, tsc , Time Stamp Counter69 1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)70 1, 0, edx, 6, pae , Physical Address Extensions71 1, 0, edx, 7, mce , Machine Check Exception72 1, 0, edx, 8, cx8 , CMPXCHG8B instruction73 1, 0, edx, 9, apic , APIC on-chip74 1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs75 1, 0, edx, 12, mtrr , Memory Type Range Registers76 1, 0, edx, 13, pge , Page Global Extensions77 1, 0, edx, 14, mca , Machine Check Architecture78 1, 0, edx, 15, cmov , Conditional Move Instruction79 1, 0, edx, 16, pat , Page Attribute Table80 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)81 1, 0, edx, 18, pn , Processor Serial Number82 1, 0, edx, 19, clflush , CLFLUSH instruction83 1, 0, edx, 21, dts , Debug Store84 1, 0, edx, 22, acpi , Thermal monitor and clock control85 1, 0, edx, 23, mmx , MMX instructions86 1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions87 1, 0, edx, 25, sse , SSE instructions88 1, 0, edx, 26, sse2 , SSE2 instructions89 1, 0, edx, 27, ss , Self Snoop90 1, 0, edx, 28, ht , Hyper-threading91 1, 0, edx, 29, tm , Thermal Monitor92 1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now resreved93 1, 0, edx, 31, pbe , Pending Break Enable94 95# Leaf 2H96# Intel cache and TLB information one-byte descriptors97 98 2, 0, eax, 7:0, iteration_count , Number of times this CPUD leaf must be queried99 2, 0, eax, 15:8, desc1 , Descriptor #1100 2, 0, eax, 23:16, desc2 , Descriptor #2101 2, 0, eax, 30:24, desc3 , Descriptor #3102 2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set103 2, 0, ebx, 7:0, desc4 , Descriptor #4104 2, 0, ebx, 15:8, desc5 , Descriptor #5105 2, 0, ebx, 23:16, desc6 , Descriptor #6106 2, 0, ebx, 30:24, desc7 , Descriptor #7107 2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set108 2, 0, ecx, 7:0, desc8 , Descriptor #8109 2, 0, ecx, 15:8, desc9 , Descriptor #9110 2, 0, ecx, 23:16, desc10 , Descriptor #10111 2, 0, ecx, 30:24, desc11 , Descriptor #11112 2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set113 2, 0, edx, 7:0, desc12 , Descriptor #12114 2, 0, edx, 15:8, desc13 , Descriptor #13115 2, 0, edx, 23:16, desc14 , Descriptor #14116 2, 0, edx, 30:24, desc15 , Descriptor #15117 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set118 119# Leaf 4H120# Intel deterministic cache parameters121 122 4, 31:0, eax, 4:0, cache_type , Cache type field123 4, 31:0, eax, 7:5, cache_level , Cache level (1-based)124 4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level125 4, 31:0, eax, 9, fully_associative , Fully-associative cache126 4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache127 4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package128 4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)129 4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)130 4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)131 4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)132 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches133 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches134 4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)135 136# Leaf 5H137# MONITOR/MWAIT instructions enumeration138 139 5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes140 5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes141 5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported142 5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported143 5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT144 5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT145 5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT146 5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT147 5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT148 5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT149 5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT150 5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT151 152# Leaf 6H153# Thermal and Power Management enumeration154 155 6, 0, eax, 0, dtherm , Digital temprature sensor156 6, 0, eax, 1, turbo_boost , Intel Turbo Boost157 6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)158 6, 0, eax, 4, pln , Power Limit Notification (PLN) event159 6, 0, eax, 5, ecmd , Clock modulation duty cycle extension160 6, 0, eax, 6, pts , Package thermal management161 6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported162 6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR)163 6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported164 6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference165 6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request166 6, 0, eax, 13, hdc_base_regs , HDC base registers are supported167 6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0168 6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change169 6, 0, eax, 16, hwp_peci_override , HWP PECI override170 6, 0, eax, 17, hwp_flexible , Flexible HWP171 6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode172 6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported173 6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported174 6, 0, eax, 23, thread_director , Intel thread director support175 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported176 6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds177 6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)178 6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support179 6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director180 6, 0, edx, 0, perfcap_reporting , Performance capability reporting181 6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting182 6, 0, edx, 11:8, feedback_sz , HW feedback interface struct size, in 4K pages183 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based184 185# Leaf 7H186# Extended CPU features enumeration187 188 7, 0, eax, 31:0, leaf7_n_subleaves , Number of cpuid 0x7 subleaves189 7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support190 7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported191 7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions)192 7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1193 7, 0, ebx, 4, hle , Hardware Lock Elision194 7, 0, ebx, 5, avx2 , AVX2 instruction set195 7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions196 7, 0, ebx, 7, smep , Supervisor Mode Execution Protection197 7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2198 7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB199 7, 0, ebx, 10, invpcid , INVPCID instruction (Invalidate Processor Context ID)200 7, 0, ebx, 11, rtm , Intel restricted transactional memory201 7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache monitoring202 7, 0, ebx, 13, zero_fcs_fds , Deprecated FPU CS/DS (stored as zero)203 7, 0, ebx, 14, mpx , Intel memory protection extensions204 7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcemeent205 7, 0, ebx, 16, avx512f , AVX-512 foundation instructions206 7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions207 7, 0, ebx, 18, rdseed , RDSEED instruction208 7, 0, ebx, 19, adx , ADCX/ADOX instructions209 7, 0, ebx, 20, smap , Supervisor mode access prevention210 7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add211 7, 0, ebx, 23, clflushopt , CLFLUSHOPT instruction212 7, 0, ebx, 24, clwb , CLWB instruction213 7, 0, ebx, 25, intel_pt , Intel processor trace214 7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions215 7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instrs216 7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instrs217 7, 0, ebx, 29, sha_ni , SHA/SHA256 instructions218 7, 0, ebx, 30, avx512bw , AVX-512 BW (byte/word granular) instructions219 7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extensions220 7, 0, ecx, 0, prefetchwt1 , PREFETCHWT1 (Intel Xeon Phi only)221 7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instrs222 7, 0, ecx, 2, umip , User mode instruction protection223 7, 0, ecx, 3, pku , Protection keys for user-space224 7, 0, ecx, 4, ospke , OS protection keys enable225 7, 0, ecx, 5, waitpkg , WAITPKG instructions226 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instrs group 2227 7, 0, ecx, 7, cet_ss , CET shadow stack features228 7, 0, ecx, 8, gfni , Galois field new instructions229 7, 0, ecx, 9, vaes , Vector AES instrs230 7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support231 7, 0, ecx, 11, avx512_vnni , Vector neural network instructions232 7, 0, ecx, 12, avx512_bitalg , AVX-512 bit count/shiffle233 7, 0, ecx, 13, tme , Intel total memory encryption234 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DW/QW235 7, 0, ecx, 16, la57 , 57-bit linear addreses (five-level paging)236 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode237 7, 0, ecx, 22, rdpid , RDPID instruction238 7, 0, ecx, 23, key_locker , Intel key locker support239 7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection240 7, 0, ecx, 25, cldemote , CLDEMOTE instruction241 7, 0, ecx, 27, movdiri , MOVDIRI instruction242 7, 0, ecx, 28, movdir64b , MOVDIR64B instruction243 7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S})244 7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration245 7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages246 7, 0, edx, 1, sgx_keys , Intel SGX attestation services247 7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions248 7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision249 7, 0, edx, 4, fsrm , Fast short REP MOV250 7, 0, edx, 5, uintr , CPU supports user interrupts251 7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions252 7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available253 7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support254 7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts255 7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported256 7, 0, edx, 14, serialize , SERIALIZE instruction257 7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part'258 7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking259 7, 0, edx, 18, pconfig , PCONFIG instruction260 7, 0, edx, 19, arch_lbr , Intel architectural LBRs261 7, 0, edx, 20, ibt , CET indirect branch tracking262 7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support263 7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions264 7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support265 7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support266 7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions)267 7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors268 7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR269 7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR270 7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR271 7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable272 7, 1, eax, 4, avx_vnni , AVX-VNNI instructions273 7, 1, eax, 5, avx512_bf16 , AVX-512 bFloat16 instructions274 7, 1, eax, 6, lass , Linear address space separation275 7, 1, eax, 7, cmpccxadd , CMPccXADD instructions276 7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: CPUID leaf 0x23 is supported277 7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB278 7, 1, eax, 11, fsrs , Fast short REP STOSB279 7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB280 7, 1, eax, 17, fred , FRED: Flexible return and event delivery transitions281 7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS282 7, 1, eax, 19, wrmsrns , WRMSRNS instr (WRMSR-non-serializing)283 7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations284 7, 1, eax, 22, hreset , History reset support285 7, 1, eax, 23, avx_ifma , Integer fused multiply add286 7, 1, eax, 26, lam , Linear address masking287 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions288 7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPIN{,_CTL} MSRs)289 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions290 7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions291 7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from Granite Rapids)292 7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions293 7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use294 7, 2, edx, 0, intel_psfd , Intel predictive store forward disable295 7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}296 7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}297 7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U298 7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S299 7, 2, edx, 5, mcdt_no , MCDT mitigation not needed300 7, 2, edx, 6, uclock_disable , UC-lock disable is supported301 302# Leaf 9H303# Intel DCA (Direct Cache Access) enumeration304 305 9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS306 307# Leaf AH308# Intel PMU (Performance Monitoring Unit) enumeration309 310 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID311 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of general PMU counters per logical CPU312 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth of PMU general counters313 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of cpuid leaf 0xa EBX bit vector314 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available315 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available316 0xa, 0, ebx, 2, no_refcycle_evt , Reference cycles event not available317 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available318 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available319 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch instruction retired event not available320 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mispredict retired event not available321 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available322 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap323 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters324 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters325 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation326 327# Leaf BH328# CPUs v1 extended topology enumeration329 330 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)331 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain332 0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID)333 0xb, 1:0, ecx, 15:8, domain_type , This domain type334 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU335 336# Leaf DH337# Processor extended state enumeration338 339 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported340 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported341 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported342 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)343 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)344 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)345 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)346 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)347 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU reg)348 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0.CET_U (bit 11) supported (CET supervisor state)349 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0.CET_S (bit 12) support (CET user state)350 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)351 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)352 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRSTR area byte size, for XCR0 enabled features353 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTR area max byte size, all CPU features354 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)355 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction356 0xd, 1, eax, 1, xsavec , XSAVEC instruction357 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1358 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR)359 0xd, 1, eax, 4, xfd , Extended feature disable support360 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled361 0xd, 1, ecx, 8, xss_pt , PT state, supported362 0xd, 1, ecx, 10, xss_pasid , PASID state, supported363 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported364 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported365 0xd, 1, ecx, 13, xss_hdc , HDC state, supported366 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported367 0xd, 1, ecx, 15, xss_lbr , LBR state, supported368 0xd, 1, ecx, 16, xss_hwp , HWP state, supported369 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes370 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes371 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit, otherwise XCR0 bit372 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature xsave area is 64-byte aligned373 374# Leaf FH375# Intel RDT / AMD PQoS resource monitoring376 377 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based)378 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported379 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based)380 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit381 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes382 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID383 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported384 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring supported385 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring supported386 387# Leaf 10H388# Intel RDT / AMD PQoS allocation enumeration389 390 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology supported391 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology supported392 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation supported393 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation394 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units395 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent396 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritization)397 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supported398 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) supported399 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation400 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported401 0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear402 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service supported403 404# Leaf 12H405# Intel Software Guard Extensions (SGX) enumeration406 407 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions supported408 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported409 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported410 0x12, 0, eax, 6, encls_leaves , ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported411 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported412 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN supported413 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA supported414 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: reporting #PF and #GP exceptions inside enclave supported415 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptions inside enclave supported416 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2)417 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2)418 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave initialized by EINIT)419 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave permits debugger read/write)420 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)421 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (provisioning key available)422 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available)423 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET attributes)424 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separation and Sharing enabled)425 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications426 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported427 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported428 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported429 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)430 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)431 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)432 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)433 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)434 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU reg)435 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)436 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA)437 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type (dictates output layout)438 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base addr, bits[12:31]439 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base addr, bits[32:51]440 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding441 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC section size, bits[12:31]442 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51]443 444# Leaf 14H445# Intel Processor Trace enumeration446 447 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpuid 0x14 subleaf448 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible449 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode450 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation451 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression452 0x14, 0, ebx, 4, ptwrite , PTWRITE support453 0x14, 0, ebx, 5, power_event_trace , Power Event Trace support454 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation support455 0x14, 0, ebx, 7, event_trace , Event Trace packet generation through IA32_RTIT_CTL.EventEn456 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable through IA32_RTIT_CTL.DisTNT457 0x14, 0, ecx, 0, topa_output , ToPA output scheme support458 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries459 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported460 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output support461 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)462 0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Address Ranges463 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodings464 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold encodings465 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB frequency encodings466 467# Leaf 15H468# Intel TSC (Time Stamp Counter) enumeration469 470 0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio471 0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio472 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz473 474# Leaf 16H475# Intel processor fequency enumeration476 477 0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz478 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz479 0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz480 481# Leaf 17H482# Intel SoC vendor attributes enumeration483 484 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpuid leaf 0x17 subleaf485 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID486 0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumaeratoion scheme (not Intel)487 0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor488 0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by vendor489 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)490 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)491 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)492 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)493 494# Leaf 18H495# Intel determenestic address translation (TLB) parameters496 497 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpuid 0x18 subleaf498 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported499 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported500 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported501 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported502 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/Soft) partitioning between logical CPUs sharing this struct503 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity504 0x18, 31:0, ecx, 31:0, n_sets , Number of sets505 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)506 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)507 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure508 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num of addressible IDs for logical CPUs sharing this TLB - 1509 510# Leaf 19H511# Intel Key Locker enumeration512 513 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction supported514 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supported515 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supported516 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions supported517 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions supported518 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups supported519 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter supported520 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encoding 1) supported521 522# Leaf 1AH523# Intel hybrid CPUs identification (e.g. Atom, Core)524 525 0x1a, 0, eax, 23:0, core_native_model , This core's native model ID526 0x1a, 0, eax, 31:24, core_type , This core's type527 528# Leaf 1BH529# Intel PCONFIG (Platform configuration) enumeration530 531 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type532 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID533 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supported PCONFIG target ID534 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID535 536# Leaf 1CH537# Intel LBR (Last Branch Record) enumeration538 539 0x1c, 0, eax, 0, lbr_depth_8 , Max stack depth (number of LBR entries) = 8540 0x1c, 0, eax, 1, lbr_depth_16 , Max stack depth (number of LBR entries) = 16541 0x1c, 0, eax, 2, lbr_depth_24 , Max stack depth (number of LBR entries) = 24542 0x1c, 0, eax, 3, lbr_depth_32 , Max stack depth (number of LBR entries) = 32543 0x1c, 0, eax, 4, lbr_depth_40 , Max stack depth (number of LBR entries) = 40544 0x1c, 0, eax, 5, lbr_depth_48 , Max stack depth (number of LBR entries) = 48545 0x1c, 0, eax, 6, lbr_depth_56 , Max stack depth (number of LBR entries) = 56546 0x1c, 0, eax, 7, lbr_depth_64 , Max stack depth (number of LBR entries) = 64547 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1548 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP, otherwise effective IP549 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported550 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported551 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) supported552 0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit supported (IA32_LBR_x_INFO[63])553 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) supported554 0x1c, 0, ecx, 2, lbr_branch_type , Branch type field (IA32_LBR_INFO_x[59:56]) supported555 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters556 557# Leaf 1DH558# Intel AMX (Advanced Matrix Extensions) tile information559 560 0x1d, 0, eax, 31:0, amx_max_palette , Highest palette ID / subleaf ID561 0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes562 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes563 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes564 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles565 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows566 567# Leaf 1EH568# Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration569 570 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns)571 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maxiumum SIMD dimension, N (column bytes)572 573# Leaf 1FH574# Intel extended topology enumeration v2575 576 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)577 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain578 0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID)579 0x1f, 5:0, ecx, 15:8, domain_type , This domain type580 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU581 582# Leaf 20H583# Intel HRESET (History Reset) enumeration584 585 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1586 0x20, 0, ebx, 0, hreset_thread_director , HRESET of Intel thread director is supported587 588# Leaf 21H589# Intel TD (Trust Domain) guest execution environment enumeration590 591 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3592 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11593 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7594 595# Leaf 23H596# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)597 598 0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1, PMU counters bitmaps, is valid599 0x23, 0, eax, 3, subleaf_3_events , Subleaf 3, PMU events bitmaps, is valid600 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 is supported601 0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is supported602 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap603 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU counters bitmap604 0x23, 3, eax, 0, core_cycles_evt , Core cycles event supported605 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event supported606 0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event supported607 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supported608 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported609 0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event supported610 0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event supported611 0x23, 3, eax, 7, td_slots_evt , Topdown slots event supported612 0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event supported613 0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event supported614 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event supported615 0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event support616 617# Leaf 40000000H618# Maximum hypervisor standard leaf + hypervisor vendor string619 6200x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor standard leaf number6210x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 36220x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 76230x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11624 625# Leaf 80000000H626# Maximum extended leaf number + CPU vendor string (AMD)627 6280x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended cpuid leaf supported6290x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 36300x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 116310x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7632 633# Leaf 80000001H634# Extended CPU feature identifiers635 6360x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID6370x80000001, 0, eax, 7:4, e_base_model , Base processor model6380x80000001, 0, eax, 11:8, e_base_family , Base processor family6390x80000001, 0, eax, 19:16, e_ext_model , Extended processor model6400x80000001, 0, eax, 27:20, e_ext_family , Extended processor family6410x80000001, 0, ebx, 15:0, brand_id , Brand ID6420x80000001, 0, ebx, 31:28, pkg_type , Package type6430x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode6440x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No HT)6450x80000001, 0, ecx, 2, svm , Secure Virtual Machine6460x80000001, 0, ecx, 3, extapic , Extended APIC space6470x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV CR0 means MOV CR86480x80000001, 0, ecx, 5, abm , LZCNT advanced bit manipulation6490x80000001, 0, ecx, 6, sse4a , SSE4A support6500x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode6510x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PREFETCH/PREFETCHW support6520x80000001, 0, ecx, 9, osvw , OS visible workaround6530x80000001, 0, ecx, 10, ibs , Instruction based sampling6540x80000001, 0, ecx, 11, xop , XOP: extended operation (AVX instructions)6550x80000001, 0, ecx, 12, skinit , SKINIT/STGI support6560x80000001, 0, ecx, 13, wdt , Watchdog timer support6570x80000001, 0, ecx, 15, lwp , Lightweight profiling6580x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction6590x80000001, 0, ecx, 17, tce , Translation cache extension6600x80000001, 0, ecx, 19, nodeid_msr , NodeId MSR (0xc001100c)6610x80000001, 0, ecx, 21, tbm , Trailing bit manipulations6620x80000001, 0, ecx, 22, topoext , Topology Extensions (cpuid leaf 0x8000001d)6630x80000001, 0, ecx, 23, perfctr_core , Core performance counter extensions6640x80000001, 0, ecx, 24, perfctr_nb , NB/DF performance counter extensions6650x80000001, 0, ecx, 26, bpext , Data access breakpoint extension6660x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter6670x80000001, 0, ecx, 28, perfctr_llc , LLC (L3) performance counter extensions6680x80000001, 0, ecx, 29, mwaitx , MWAITX/MONITORX support6690x80000001, 0, ecx, 30, addr_mask_ext , Breakpoint address mask extension (to bit 31)6700x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)6710x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions6720x80000001, 0, edx, 2, e_de , Debugging Extensions6730x80000001, 0, edx, 3, e_pse , Page Size Extension6740x80000001, 0, edx, 4, e_tsc , Time Stamp Counter6750x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR and WRMSR support)6760x80000001, 0, edx, 6, pae , Physical Address Extensions6770x80000001, 0, edx, 7, mce , Machine Check Exception6780x80000001, 0, edx, 8, cx8 , CMPXCHG8B instruction6790x80000001, 0, edx, 9, apic , APIC on-chip6800x80000001, 0, edx, 11, syscall , SYSCALL and SYSRET instructions6810x80000001, 0, edx, 12, mtrr , Memory Type Range Registers6820x80000001, 0, edx, 13, pge , Page Global Extensions6830x80000001, 0, edx, 14, mca , Machine Check Architecture6840x80000001, 0, edx, 15, cmov , Conditional Move Instruction6850x80000001, 0, edx, 16, pat , Page Attribute Table6860x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)6870x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit6880x80000001, 0, edx, 20, nx , No-execute page protection6890x80000001, 0, edx, 22, mmxext , AMD MMX extensions6900x80000001, 0, edx, 24, e_fxsr , FXSAVE and FXRSTOR instructions6910x80000001, 0, edx, 25, fxsr_opt , FXSAVE and FXRSTOR optimizations6920x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support6930x80000001, 0, edx, 27, rdtscp , RDTSCP instruction6940x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)6950x80000001, 0, edx, 30, 3dnowext , AMD 3DNow extensions6960x80000001, 0, edx, 31, 3dnow , 3DNow instructions697 698# Leaf 80000002H699# CPU brand ID string, bytes 0 - 15700 7010x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 37020x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 77030x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 117040x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15705 706# Leaf 80000003H707# CPU brand ID string, bytes 16 - 31708 7090x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 197100x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 237110x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 277120x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31713 714# Leaf 80000004H715# CPU brand ID string, bytes 32 - 47716 7170x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 357180x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 397190x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 437200x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47721 722# Leaf 80000005H723# AMD L1 cache and L1 TLB enumeration724 7250x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entires, 2M and 4M pages7260x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB associativity, 2M and 4M pages7270x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB #entires, 2M and 4M pages7280x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB associativity, 2M and 4M pages7290x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages7300x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB associativity, 4K pages7310x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB #entries, 4K pages7320x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB associativity, 4K pages7330x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes7340x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcache lines per tag7350x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcache associativity7360x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcache size, in KB7370x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes7380x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache lines per tag7390x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache associativity7400x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB741 742# Leaf 80000006H743# (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration744 7450x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #entries, 2M and 4M pages7460x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB associativity, 2M and 4M pages7470x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB #entries, 2M and 4M pages7480x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB associativity, 2M and 4M pages7490x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB #entries, 4K pages7500x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB associativity, 4K pages7510x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB #entries, 4K pages7520x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB associativity, 4K pages7530x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes7540x80000006, 0, ecx, 11:8, l2_nlines , L2 cache number of lines per tag7550x80000006, 0, ecx, 15:12, l2_assoc , L2 cache associativity7560x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache size, in KB7570x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes7580x80000006, 0, edx, 11:8, l3_nlines , L3 cache number of lines per tag7590x80000006, 0, edx, 15:12, l3_assoc , L3 cache associativity7600x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range761 762# Leaf 80000007H763# CPU power management (mostly AMD) and AMD RAS enumeration764 7650x80000007, 0, ebx, 0, overflow_recov , MCA overflow conditions not fatal7660x80000007, 0, ebx, 1, succor , Software containment of UnCORRectable errors7670x80000007, 0, ebx, 2, hw_assert , Hardware assert MSRs7680x80000007, 0, ebx, 3, smca , Scalable MCA (MCAX MSRs)7690x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU power sample time ratio7700x80000007, 0, edx, 0, digital_temp , Digital temprature sensor7710x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling7720x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! voltage scaling7730x80000007, 0, edx, 3, thermal_trip , THERMTRIP (Thermal Trip)7740x80000007, 0, edx, 4, hw_thermal_control , Hardware thermal control7750x80000007, 0, edx, 5, sw_thermal_control , Software thermal control7760x80000007, 0, edx, 6, 100mhz_steps , 100 MHz multiplier control7770x80000007, 0, edx, 7, hw_pstate , Hardware P-state control7780x80000007, 0, edx, 8, constant_tsc , TSC ticks at constant rate across all P and C states7790x80000007, 0, edx, 9, cpb , Core performance boost7800x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency interface7810x80000007, 0, edx, 11, proc_feedback , Processor feedback interface (deprecated)7820x80000007, 0, edx, 12, acc_power , Processor power reporting interface7830x80000007, 0, edx, 13, connected_standby , CPU Connected Standby support7840x80000007, 0, edx, 14, rapl , Runtime Average Power Limit interface785 786# Leaf 80000008H787# CPU capacity parameters and extended feature flags (mostly AMD)788 7890x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits7900x80000008, 0, eax, 15:8, virt_addr_bits , Max virtual address bits7910x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits7920x80000008, 0, ebx, 0, clzero , CLZERO supported7930x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR7940x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRSTOR always saves/restores FPU error pointers7950x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate to all threads7960x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level) supported7970x80000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit)7980x80000008, 0, ebx, 8, mcommit , MCOMMIT (Memory commit) supported7990x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD supported8000x80000008, 0, ebx, 12, amd_ibpb , Indirect Branch Prediction Barrier8010x80000008, 0, ebx, 13, wbinvd_int , Interruptible WBINVD/WBNOINVD8020x80000008, 0, ebx, 14, amd_ibrs , Indirect Branch Restricted Speculation8030x80000008, 0, ebx, 15, amd_stibp , Single Thread Indirect Branch Prediction mode8040x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred8050x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred8060x80000008, 0, ebx, 18, ibrs_fast , IBRS is preferred over software solution8070x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provides same mode protection8080x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segment Limit Enable) unsupported8090x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set (nested translations)8100x80000008, 0, ebx, 23, amd_ppin , Protected Processor Inventory Number8110x80000008, 0, ebx, 24, amd_ssbd , Speculative Store Bypass Disable8120x80000008, 0, ebx, 25, virt_ssbd , virtualized SSBD (Speculative Store Bypass Disable)8130x80000008, 0, ebx, 26, amd_ssb_no , SSBD not needed (fixed in HW)8140x80000008, 0, ebx, 27, cppc , Collaborative Processor Performance Control8150x80000008, 0, ebx, 28, amd_psfd , Predictive Store Forward Disable8160x80000008, 0, ebx, 29, btc_no , CPU not affected by Branch Type Confusion8170x80000008, 0, ebx, 30, ibpb_ret , IBPB clears RSB/RAS too8180x80000008, 0, ebx, 31, brs , Branch Sampling supported8190x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 18200x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of thread core ID bits (shift) in APIC ID8210x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size8220x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB maximum page count8230x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input)824 825# Leaf 8000000AH826# AMD SVM (Secure Virtual Machine) enumeration827 8280x8000000a, 0, eax, 7:0, svm_version , SVM revision number8290x8000000a, 0, ebx, 31:0, svm_nasid , Number of address space identifiers (ASID)8300x8000000a, 0, edx, 0, npt , Nested paging8310x8000000a, 0, edx, 1, lbrv , LBR virtualization8320x8000000a, 0, edx, 2, svm_lock , SVM lock8330x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT8340x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control8350x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support8360x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control8370x8000000a, 0, edx, 7, decodeassists , Decode Assists support8380x8000000a, 0, edx, 10, pausefilter , Pause intercept filter8390x8000000a, 0, edx, 12, pfthreshold , Pause filter threshold8400x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller8410x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VMSAVE/VMLOAD (nested virt)8420x8000000a, 0, edx, 16, vgif , Virtualize the Global Interrupt Flag8430x8000000a, 0, edx, 17, gmet , Guest mode execution trap8440x8000000a, 0, edx, 18, x2avic , Virtual x2APIC8450x8000000a, 0, edx, 19, sss_check , Supervisor Shadow Stack restrictions8460x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SPEC_CTRL8470x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support8480x8000000a, 0, edx, 23, h_mce_override , Host MCE override8490x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB8500x8000000a, 0, edx, 25, vnmi , NMI virtualization8510x8000000a, 0, edx, 26, ibs_virt , IBS Virtualization8520x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended LVT offset fault change8530x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME addr check854 855# Leaf 80000019H856# AMD TLB 1G-pages enumeration857 8580x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages8590x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages8600x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages8610x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages8620x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages8630x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages8640x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages8650x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages866 867# Leaf 8000001AH868# AMD instruction optimizations enumeration869 8700x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide8710x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*8720x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide873 874# Leaf 8000001BH875# AMD IBS (Instruction-Based Sampling) enumeration876 8770x8000001b, 0, eax, 0, ibs_flags_valid , IBS feature flags valid8780x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling supported8790x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling supported8800x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter supported8810x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode supported8820x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting supported8830x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits8840x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication supported8850x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication supported8860x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR (0xc001103c) supported8870x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR supported8880x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (Zen4+)889 890# Leaf 8000001CH891# AMD LWP (Lightweight Profiling)892 8930x8000001c, 0, eax, 0, os_lwp_avail , LWP is available to application programs (supported by OS)8940x8000001c, 0, eax, 1, os_lpwval , LWPVAL instruction (EventId=1) is supported by OS8950x8000001c, 0, eax, 2, os_lwp_ire , Instructions Retired Event (EventId=2) is supported by OS8960x8000001c, 0, eax, 3, os_lwp_bre , Branch Retired Event (EventId=3) is supported by OS8970x8000001c, 0, eax, 4, os_lwp_dme , DCache Miss Event (EventId=4) is supported by OS8980x8000001c, 0, eax, 5, os_lwp_cnh , CPU Clocks Not Halted event (EventId=5) is supported by OS8990x8000001c, 0, eax, 6, os_lwp_rnh , CPU Reference clocks Not Halted event (EventId=6) is supported by OS9000x8000001c, 0, eax, 29, os_lwp_cont , LWP sampling in continuous mode is supported by OS9010x8000001c, 0, eax, 30, os_lwp_ptsc , Performance Time Stamp Counter in event records is supported by OS9020x8000001c, 0, eax, 31, os_lwp_int , Interrupt on threshold overflow is supported by OS9030x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Control Block size, in quadwords9040x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP event record size, in bytes9050x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max supported EventId value (EventID 255 not included)9060x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP events area offset in the LWP Control Block9070x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of bits in cache latency counters (10 to 31)9080x8000001c, 0, ecx, 5, lwp_data_adddr , Cache miss events report the data address of the reference9090x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount by which cache latency is rounded9100x8000001c, 0, ecx, 15:9, lwp_version , LWP implementation version9110x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, in units of 32 event records9120x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered9130x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported9140x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filtered by cache level9150x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filtered by latency9160x8000001c, 0, edx, 0, hw_lwp_avail , LWP is available in Hardware9170x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction (EventId=1) is available in HW9180x8000001c, 0, edx, 2, hw_lwp_ire , Instructions Retired Event (EventId=2) is available in HW9190x8000001c, 0, edx, 3, hw_lwp_bre , Branch Retired Event (EventId=3) is available in HW9200x8000001c, 0, edx, 4, hw_lwp_dme , DCache Miss Event (EventId=4) is available in HW9210x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Clocks Not Halted event (EventId=5) is available in HW9220x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Reference clocks Not Halted event (EventId=6) is available in HW9230x8000001c, 0, edx, 29, hw_lwp_cont , LWP sampling in continuous mode is available in HW9240x8000001c, 0, edx, 30, hw_lwp_ptsc , Performance Time Stamp Counter in event records is available in HW9250x8000001c, 0, edx, 31, hw_lwp_int , Interrupt on threshold overflow is available in HW926 927# Leaf 8000001DH928# AMD deterministic cache parameters929 9300x8000001d, 31:0, eax, 4:0, cache_type , Cache type field9310x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)9320x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level9330x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache9340x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number of logical CPUs sharing cache9350x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)9360x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)9370x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)9380x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)9390x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches9400x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches941 942# Leaf 8000001EH943# AMD CPU topology enumeration944 9450x8000001e, 0, eax, 31:0, ext_apic_id , Extended APIC ID9460x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID9470x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based)9480x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU9490x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in invoking logical CPU's package/socket950 951# Leaf 8000001FH952# AMD encrypted memory capabilities enumeration (SME/SEV)953 9540x8000001f, 0, eax, 0, sme , Secure Memory Encryption supported9550x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization supported9560x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR (0xc001011e) available9570x8000001f, 0, eax, 3, sev_es , SEV Encrypted State supported9580x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging supported9590x8000001f, 0, eax, 5, vm_permission_levels , VMPL supported9600x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction supported9610x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadwo stack supported9620x8000001f, 0, eax, 8, secure_tsc , Secure TSC supported9630x8000001f, 0, eax, 9, v_tsc_aux , Hardware virtualizes TSC_AUX9640x8000001f, 0, eax, 10, sme_coherent , HW enforces cache coherency across encryption domains9650x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor9660x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported9670x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported9680x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is supported9690x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host is supported9700x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption9710x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitParameter is supported in SEV_FEATURES9720x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR is supported9730x8000001f, 0, eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests9740x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection is supported9750x8000001f, 0, eax, 25, smt_protection , SMT protection is supported9760x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR (0xc001f000h) is supported9770x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs are supported9780x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number used to enable memory encryption9790x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space when encryption is enabled, in bits9800x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL) supported9810x8000001f, 0, ecx, 31:0, enc_guests_max , Max supported number of simultaneous encrypted guests9820x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-ES-disabled guest983 984# Leaf 80000020H985# AMD Platform QoS extended feature IDs986 9870x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support9880x80000020, 0, ebx, 2, smba , Slow Memory Bandwidth Allocation support9890x80000020, 0, ebx, 3, bmec , Bandwidth Monitoring Event Configuration support9900x80000020, 0, ebx, 4, l3rr , L3 Range Reservation support9910x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size9920x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)9930x80000020, 2, eax, 31:0, smba_limit_len , SMBA enforcement limit size9940x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)9950x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events available9960x80000020, 3, ecx, 0, bmec_local_reads , Local NUMA reads can be tracked9970x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked9980x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes can be tracked9990x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes can be tracked10000x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can be tracked10010x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can be tracked10020x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS victims to all types of memory can be tracked1003 1004# Leaf 80000021H1005# AMD extended features enumeration 21006 10070x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints10080x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing10090x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC10100x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock is supported10110x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base10120x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore Enable bit supported10130x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS enable bit supported10140x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not present10150x80000021, 0, eax, 10, fsrs_supported , Fast Short Rep Stosb (FSRS) is supported10160x80000021, 0, eax, 11, fsrc_supported , Fast Short Repe Cmpsb (FSRC) is supported10170x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is supported10180x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 is supported10190x80000021, 0, eax, 18, epsf_supported , Enhanced Predictive Store Forwarding (EPSF) is supported10200x80000021, 0, ebx, 11:0, microcode_patch_size , Size of microcode patch, in 16-byte units1021 1022# Leaf 80000022H1023# AMD Performance Monitoring v2 enumeration1024 10250x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2 supported10260x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack)10270x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack supported10280x80000022, 0, ebx, 3:0, n_pmc_core , Number of core perfomance counters10290x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of available LBR stack entries10300x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of available northbridge (data fabric) performance counters10310x80000022, 0, ebx, 21:16, n_pmc_umc , Number of available UMC performance counters10320x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMCs bitmask1033 1034# Leaf 80000023H1035# AMD Secure Multi-key Encryption enumeration1036 10370x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is supported10380x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total num of available encryption keys1039 1040# Leaf 80000026H1041# AMD extended topology enumeration v21042 10430x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)10440x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core has a power efficiency ranking10450x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domain level has hybrid (E, P) cores10460x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Core' domain has asymmetric cores count10470x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number of logical CPUs at this domain instance10480x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This core's static power efficiency ranking10490x80000026, 3:0, ebx, 27:24, core_native_model_id , This core's native model ID10500x80000026, 3:0, ebx, 31:28, core_type , This core's type10510x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID)10520x80000026, 3:0, ecx, 15:8, domain_type , This domain type10530x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU1054