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1perf-c2c(1)2===========3 4NAME5----6perf-c2c - Shared Data C2C/HITM Analyzer.7 8SYNOPSIS9--------10[verse]11'perf c2c record' [<options>] <command>12'perf c2c record' [<options>] \-- [<record command options>] <command>13'perf c2c report' [<options>]14 15DESCRIPTION16-----------17C2C stands for Cache To Cache.18 19The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows20you to track down the cacheline contentions.21 22On Intel, the tool is based on load latency and precise store facility events23provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling24with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware25limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to26sample load and store operations, therefore hardware and kernel support is27required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the28statistical nature of Arm SPE sampling, not every memory operation will be29sampled.30 31These events provide:32 - memory address of the access33 - type of the access (load and store details)34 - latency (in cycles) of the load access35 36The c2c tool provide means to record this data and report back access details37for cachelines with highest contention - highest number of HITM accesses.38 39The basic workflow with this tool follows the standard record/report phase.40User uses the record command to record events data and report command to41display it.42 43 44RECORD OPTIONS45--------------46-e::47--event=::48 Select the PMU event. Use 'perf c2c record -e list'49 to list available events.50 51-v::52--verbose::53 Be more verbose (show counter open errors, etc).54 55-l::56--ldlat::57 Configure mem-loads latency. Supported on Intel and Arm64 processors58 only. Ignored on other archs.59 60-k::61--all-kernel::62 Configure all used events to run in kernel space.63 64-u::65--all-user::66 Configure all used events to run in user space.67 68REPORT OPTIONS69--------------70-k::71--vmlinux=<file>::72 vmlinux pathname73 74-v::75--verbose::76 Be more verbose (show counter open errors, etc).77 78-i::79--input::80 Specify the input file to process.81 82-N::83--node-info::84 Show extra node info in report (see NODE INFO section)85 86-c::87--coalesce::88 Specify sorting fields for single cacheline display.89 Following fields are available: tid,pid,iaddr,dso90 (see COALESCE)91 92-g::93--call-graph::94 Setup callchains parameters.95 Please refer to perf-report man page for details.96 97--stdio::98 Force the stdio output (see STDIO OUTPUT)99 100--stats::101 Display only statistic tables and force stdio mode.102 103--full-symbols::104 Display full length of symbols.105 106--no-source::107 Do not display Source:Line column.108 109--show-all::110 Show all captured HITM lines, with no regard to HITM % 0.0005 limit.111 112-f::113--force::114 Don't do ownership validation.115 116-d::117--display::118 Switch to HITM type (rmt, lcl) or peer snooping type (peer) to display119 and sort on. Total HITMs (tot) as default, except Arm64 uses peer mode120 as default.121 122--stitch-lbr::123 Show callgraph with stitched LBRs, which may have more complete124 callgraph. The perf.data file must have been obtained using125 perf c2c record --call-graph lbr.126 Disabled by default. In common cases with call stack overflows,127 it can recreate better call stacks than the default lbr call stack128 output. But this approach is not foolproof. There can be cases129 where it creates incorrect call stacks from incorrect matches.130 The known limitations include exception handing such as131 setjmp/longjmp will have calls/returns not match.132 133--double-cl::134 Group the detection of shared cacheline events into double cacheline135 granularity. Some architectures have an Adjacent Cacheline Prefetch136 feature, which causes cacheline sharing to behave like the cacheline137 size is doubled.138 139C2C RECORD140----------141The perf c2c record command setup options related to HITM cacheline analysis142and calls standard perf record command.143 144Following perf record options are configured by default:145(check perf record man page for details)146 147 -W,-d,--phys-data,--sample-cpu148 149Unless specified otherwise with '-e' option, following events are monitored by150default on Intel:151 152 cpu/mem-loads,ldlat=30/P153 cpu/mem-stores/P154 155following on AMD:156 157 ibs_op//158 159and following on PowerPC:160 161 cpu/mem-loads/162 cpu/mem-stores/163 164User can pass any 'perf record' option behind '--' mark, like (to enable165callchains and system wide monitoring):166 167 $ perf c2c record -- -g -a168 169Please check RECORD OPTIONS section for specific c2c record options.170 171C2C REPORT172----------173The perf c2c report command displays shared data analysis. It comes in two174display modes: stdio and tui (default).175 176The report command workflow is following:177 - sort all the data based on the cacheline address178 - store access details for each cacheline179 - sort all cachelines based on user settings180 - display data181 182In general perf report output consist of 2 basic views:183 1) most expensive cachelines list184 2) offsets details for each cacheline185 186For each cacheline in the 1) list we display following data:187(Both stdio and TUI modes follow the same fields output)188 189 Index190 - zero based index to identify the cacheline191 192 Cacheline193 - cacheline address (hex number)194 195 Rmt/Lcl Hitm (Display with HITM types)196 - cacheline percentage of all Remote/Local HITM accesses197 198 Peer Snoop (Display with peer type)199 - cacheline percentage of all peer accesses200 201 LLC Load Hitm - Total, LclHitm, RmtHitm (For display with HITM types)202 - count of Total/Local/Remote load HITMs203 204 Load Peer - Total, Local, Remote (For display with peer type)205 - count of Total/Local/Remote load from peer cache or DRAM206 207 Total records208 - sum of all cachelines accesses209 210 Total loads211 - sum of all load accesses212 213 Total stores214 - sum of all store accesses215 216 Store Reference - L1Hit, L1Miss, N/A217 L1Hit - store accesses that hit L1218 L1Miss - store accesses that missed L1219 N/A - store accesses with memory level is not available220 221 Core Load Hit - FB, L1, L2222 - count of load hits in FB (Fill Buffer), L1 and L2 cache223 224 LLC Load Hit - LlcHit, LclHitm225 - count of LLC load accesses, includes LLC hits and LLC HITMs226 227 RMT Load Hit - RmtHit, RmtHitm228 - count of remote load accesses, includes remote hits and remote HITMs;229 on Arm neoverse cores, RmtHit is used to account remote accesses,230 includes remote DRAM or any upward cache level in remote node231 232 Load Dram - Lcl, Rmt233 - count of local and remote DRAM accesses234 235For each offset in the 2) list we display following data:236 237 HITM - Rmt, Lcl (Display with HITM types)238 - % of Remote/Local HITM accesses for given offset within cacheline239 240 Peer Snoop - Rmt, Lcl (Display with peer type)241 - % of Remote/Local peer accesses for given offset within cacheline242 243 Store Refs - L1 Hit, L1 Miss, N/A244 - % of store accesses that hit L1, missed L1 and N/A (no available) memory245 level for given offset within cacheline246 247 Data address - Offset248 - offset address249 250 Pid251 - pid of the process responsible for the accesses252 253 Tid254 - tid of the process responsible for the accesses255 256 Code address257 - code address responsible for the accesses258 259 cycles - rmt hitm, lcl hitm, load (Display with HITM types)260 - sum of cycles for given accesses - Remote/Local HITM and generic load261 262 cycles - rmt peer, lcl peer, load (Display with peer type)263 - sum of cycles for given accesses - Remote/Local peer load and generic load264 265 cpu cnt266 - number of cpus that participated on the access267 268 Symbol269 - code symbol related to the 'Code address' value270 271 Shared Object272 - shared object name related to the 'Code address' value273 274 Source:Line275 - source information related to the 'Code address' value276 277 Node278 - nodes participating on the access (see NODE INFO section)279 280NODE INFO281---------282The 'Node' field displays nodes that accesses given cacheline283offset. Its output comes in 3 flavors:284 - node IDs separated by ','285 - node IDs with stats for each ID, in following format:286 Node{cpus %hitms %stores} (Display with HITM types)287 Node{cpus %peers %stores} (Display with peer type)288 - node IDs with list of affected CPUs in following format:289 Node{cpu list}290 291User can switch between above flavors with -N option or292use 'n' key to interactively switch in TUI mode.293 294COALESCE295--------296User can specify how to sort offsets for cacheline.297 298Following fields are available and governs the final299output fields set for cacheline offsets output:300 301 tid - coalesced by process TIDs302 pid - coalesced by process PIDs303 iaddr - coalesced by code address, following fields are displayed:304 Code address, Code symbol, Shared Object, Source line305 dso - coalesced by shared object306 307By default the coalescing is setup with 'pid,iaddr'.308 309STDIO OUTPUT310------------311The stdio output displays data on standard output.312 313Following tables are displayed:314 Trace Event Information315 - overall statistics of memory accesses316 317 Global Shared Cache Line Event Information318 - overall statistics on shared cachelines319 320 Shared Data Cache Line Table321 - list of most expensive cachelines322 323 Shared Cache Line Distribution Pareto324 - list of all accessed offsets for each cacheline325 326TUI OUTPUT327----------328The TUI output provides interactive interface to navigate329through cachelines list and to display offset details.330 331For details please refer to the help window by pressing '?' key.332 333CREDITS334-------335Although Don Zickus, Dick Fowles and Joe Mario worked together336to get this implemented, we got lots of early help from Arnaldo337Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.338 339C2C BLOG340--------341Check Joe's blog on c2c tool for detailed use case explanation:342 https://joemario.github.io/blog/2016/09/01/c2c-blog/343 344SEE ALSO345--------346linkperf:perf-record[1], linkperf:perf-mem[1], linkperf:perf-arm-spe[1]347