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1perf-list(1)2============3 4NAME5----6perf-list - List all symbolic event types7 8SYNOPSIS9--------10[verse]11'perf list' [--no-desc] [--long-desc]12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]13 14DESCRIPTION15-----------16This command displays the symbolic event types which can be selected in the17various perf commands with the -e option.18 19OPTIONS20-------21-d::22--desc::23Print extra event descriptions. (default)24 25--no-desc::26Don't print descriptions.27 28-v::29--long-desc::30Print longer event descriptions.31 32--debug::33Enable debugging output.34 35--details::36Print how named events are resolved internally into perf events, and also37any extra expressions computed by perf stat.38 39--deprecated::40Print deprecated events. By default the deprecated events are hidden.41 42--unit::43Print PMU events and metrics limited to the specific PMU name.44(e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom)45 46-j::47--json::48Output in JSON format.49 50-o::51--output=::52 Output file name. By default output is written to stdout.53 54[[EVENT_MODIFIERS]]55EVENT MODIFIERS56---------------57 58Events can optionally have a modifier by appending a colon and one or59more modifiers. Modifiers allow the user to restrict the events to be60counted. The following modifiers exist:61 62 u - user-space counting63 k - kernel counting64 h - hypervisor counting65 I - non idle counting66 G - guest counting (in KVM guests)67 H - host counting (not in KVM guests)68 p - precise level69 P - use maximum detected precise level70 S - read sample value (PERF_SAMPLE_READ)71 D - pin the event to the PMU72 W - group is weak and will fallback to non-group if not schedulable,73 e - group or event are exclusive and do not share the PMU74 b - use BPF aggregration (see perf stat --bpf-counters)75 R - retire latency value of the event76 77The 'p' modifier can be used for specifying how precise the instruction78address should be. The 'p' modifier can be specified multiple times:79 80 0 - SAMPLE_IP can have arbitrary skid81 1 - SAMPLE_IP must have constant skid82 2 - SAMPLE_IP requested to have 0 skid83 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid84 sample shadowing effects.85 86For Intel systems precise event sampling is implemented with PEBS87which supports up to precise-level 2, and precise level 3 for88some special cases89 90On AMD systems it is implemented using IBS OP (up to precise-level 2).91Unlike Intel PEBS which provides levels of precision, AMD core pmu is92inherently non-precise and IBS is inherently precise. (i.e. ibs_op//,93ibs_op//p, ibs_op//pp and ibs_op//ppp are all same). The precise modifier94works with event types 0x76 (cpu-cycles, CPU clocks not halted) and 0xC195(micro-ops retired). Both events map to IBS execution sampling (IBS op)96with the IBS Op Counter Control bit (IbsOpCntCtl) set respectively (see the97Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS)98section of the [AMD Processor Programming Reference (PPR)] relevant to the99family, model and stepping of the processor being used).100 101Manual Volume 2: System Programming, 13.3 Instruction-Based102Sampling). Examples to use IBS:103 104 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles105 perf record -a -e r076:p ... # same as -e cpu-cycles:p106 perf record -a -e r0C1:p ... # use ibs op counting micro-ops107 108RAW HARDWARE EVENT DESCRIPTOR109-----------------------------110Even when an event is not available in a symbolic form within perf right now,111it can be encoded in a per processor specific way.112 113For instance on x86 CPUs, N is a hexadecimal value that represents the raw register encoding with the114layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout115of IA32_PERFEVTSELx MSRs) or AMD's PERF_CTL MSRs (see the116Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the117[AMD Processor Programming Reference (PPR)] relevant to the family, model118and stepping of the processor being used).119 120Note: Only the following bit fields can be set in x86 counter121registers: event, umask, edge, inv, cmask. Esp. guest/host only and122OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT123MODIFIERS>>.124 125Example:126 127If the Intel docs for a QM720 Core i7 describe an event as:128 129 Event Umask Event Mask130 Num. Value Mnemonic Description Comment131 132 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and133 delivered by loop stream detector invert to count134 cycles135 136raw encoding of 0x1A8 can be used:137 138 perf stat -e r1a8 -a sleep 1139 perf record -e r1a8 ...140 141It's also possible to use pmu syntax:142 143 perf record -e r1a8 -a sleep 1144 perf record -e cpu/r1a8/ ...145 perf record -e cpu/r0x1a8/ ...146 147Some processors, like those from AMD, support event codes and unit masks148larger than a byte. In such cases, the bits corresponding to the event149configuration parameters can be seen with:150 151 cat /sys/bus/event_source/devices/<pmu>/format/<config>152 153Example:154 155If the AMD docs for an EPYC 7713 processor describe an event as:156 157 Event Umask Event Mask158 Num. Value Mnemonic Description159 160 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag161 hit events.162 163raw encoding of 0x0328F cannot be used since the upper nibble of the164EventSelect bits have to be specified via bits 32-35 as can be seen with:165 166 cat /sys/bus/event_source/devices/cpu/format/event167 168raw encoding of 0x20000038F should be used instead:169 170 perf stat -e r20000038f -a sleep 1171 perf record -e r20000038f ...172 173It's also possible to use pmu syntax:174 175 perf record -e r20000038f -a sleep 1176 perf record -e cpu/r20000038f/ ...177 perf record -e cpu/r0x20000038f/ ...178 179You should refer to the processor specific documentation for getting these180details. Some of them are referenced in the SEE ALSO section below.181 182ARBITRARY PMUS183--------------184 185perf also supports an extended syntax for specifying raw parameters186to PMUs. Using this typically requires looking up the specific event187in the CPU vendor specific documentation.188 189The available PMUs and their raw parameters can be listed with190 191 ls /sys/devices/*/format192 193For example the raw event "LSD.UOPS" core pmu event above could194be specified as195 196 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...197 198 or using extended name syntax199 200 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...201 202PER SOCKET PMUS203---------------204 205Some PMUs are not associated with a core, but with a whole CPU socket.206Events on these PMUs generally cannot be sampled, but only counted globally207with perf stat -a. They can be bound to one logical CPU, but will measure208all the CPUs in the same socket.209 210This example measures memory bandwidth every second211on the first memory controller on socket 0 of a Intel Xeon system212 213 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...214 215Each memory controller has its own PMU. Measuring the complete system216bandwidth would require specifying all imc PMUs (see perf list output),217and adding the values together. To simplify creation of multiple events,218prefix and glob matching is supported in the PMU name, and the prefix219'uncore_' is also ignored when performing the match. So the command above220can be expanded to all memory controllers by using the syntaxes:221 222 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...223 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...224 225This example measures the combined core power every second226 227 perf stat -I 1000 -e power/energy-cores/ -a228 229ACCESS RESTRICTIONS230-------------------231 232For non root users generally only context switched PMU events are available.233This is normally only the events in the cpu PMU, the predefined events234like cycles and instructions and some software events.235 236Other PMUs and global measurements are normally root only.237Some event qualifiers, such as "any", are also root only.238 239This can be overridden by setting the kernel.perf_event_paranoid240sysctl to -1, which allows non root to use these events.241 242For accessing trace point events perf needs to have read access to243/sys/kernel/tracing, even when perf_event_paranoid is in a relaxed244setting.245 246TRACING247-------248 249Some PMUs control advanced hardware tracing capabilities, such as Intel PT,250that allows low overhead execution tracing. These are described in a separate251intel-pt.txt document.252 253PARAMETERIZED EVENTS254--------------------255 256Some pmu events listed by 'perf-list' will be displayed with '?' in them. For257example:258 259 hv_gpci/dtbp_ptitc,phys_processor_idx=?/260 261This means that when provided as an event, a value for '?' must262also be supplied. For example:263 264 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...265 266EVENT QUALIFIERS:267 268It is also possible to add extra qualifiers to an event:269 270percore:271 272Sums up the event counts for all hardware threads in a core, e.g.:273 274 275 perf stat -e cpu/event=0,umask=0x3,percore=1/276 277 278EVENT GROUPS279------------280 281Perf supports time based multiplexing of events, when the number of events282active exceeds the number of hardware performance counters. Multiplexing283can cause measurement errors when the workload changes its execution284profile.285 286When metrics are computed using formulas from event counts, it is useful to287ensure some events are always measured together as a group to minimize multiplexing288errors. Event groups can be specified using { }.289 290 perf stat -e '{instructions,cycles}' ...291 292The number of available performance counters depend on the CPU. A group293cannot contain more events than available counters.294For example Intel Core CPUs typically have four generic performance counters295for the core, plus three fixed counters for instructions, cycles and296ref-cycles. Some special events have restrictions on which counter they297can schedule, and may not support multiple instances in a single group.298When too many events are specified in the group some of them will not299be measured.300 301Globally pinned events can limit the number of counters available for302other groups. On x86 systems, the NMI watchdog pins a counter by default.303The nmi watchdog can be disabled as root with304 305 echo 0 > /proc/sys/kernel/nmi_watchdog306 307Events from multiple different PMUs cannot be mixed in a group, with308some exceptions for software events.309 310LEADER SAMPLING311---------------312 313perf also supports group leader sampling using the :S specifier.314 315 perf record -e '{cycles,instructions}:S' ...316 perf report --group317 318Normally all events in an event group sample, but with :S only319the first event (the leader) samples, and it only reads the values of the320other events in the group.321 322However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX323area event must be the leader, so then the second event samples, not the first.324 325OPTIONS326-------327 328Without options all known events will be listed.329 330To limit the list use:331 332. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.333 334. 'sw' or 'software' to list software events such as context switches, etc.335 336. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.337 338. 'tracepoint' to list all tracepoint events, alternatively use339 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,340 block, etc.341 342. 'pmu' to print the kernel supplied PMU events.343 344. 'sdt' to list all Statically Defined Tracepoint events.345 346. 'metric' to list metrics347 348. 'metricgroup' to list metricgroups with metrics.349 350. If none of the above is matched, it will apply the supplied glob to all351 events, printing the ones that match.352 353. As a last resort, it will do a substring search in all event names.354 355One or more types can be used at the same time, listing the events for the356types specified.357 358Support raw format:359 360. '--raw-dump', shows the raw-dump of all the events.361. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of362 a certain kind of events.363 364SEE ALSO365--------366linkperf:perf-stat[1], linkperf:perf-top[1],367linkperf:perf-record[1],368http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],369https://bugzilla.kernel.org/show_bug.cgi?id=206537[AMD Processor Programming Reference (PPR)]370