374 lines · json
1[2 {3 "BriefDescription": "A Write or Read Op at HIF interface. The unit is 64B.",4 "ConfigCode": "0x0",5 "EventName": "hif_rd_or_wr",6 "Unit": "ali_drw",7 "Compat": "ali_drw_pmu"8 },9 {10 "BriefDescription": "A Write Op at HIF interface. The unit is 64B.",11 "ConfigCode": "0x1",12 "EventName": "hif_wr",13 "Unit": "ali_drw",14 "Compat": "ali_drw_pmu"15 },16 {17 "BriefDescription": "A Read Op at HIF interface. The unit is 64B.",18 "ConfigCode": "0x2",19 "EventName": "hif_rd",20 "Unit": "ali_drw",21 "Compat": "ali_drw_pmu"22 },23 {24 "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",25 "ConfigCode": "0x3",26 "EventName": "hif_rmw",27 "Unit": "ali_drw",28 "Compat": "ali_drw_pmu"29 },30 {31 "BriefDescription": "A high priority Read at HIF interface. The unit is 64B.",32 "ConfigCode": "0x4",33 "EventName": "hif_hi_pri_rd",34 "Unit": "ali_drw",35 "Compat": "ali_drw_pmu"36 },37 {38 "BriefDescription": "A write data cycle at DFI interface (to DRAM).",39 "ConfigCode": "0x7",40 "EventName": "dfi_wr_data_cycles",41 "Unit": "ali_drw",42 "Compat": "ali_drw_pmu"43 },44 {45 "BriefDescription": "A read data cycle at DFI interface (to DRAM).",46 "ConfigCode": "0x8",47 "EventName": "dfi_rd_data_cycles",48 "Unit": "ali_drw",49 "Compat": "ali_drw_pmu"50 },51 {52 "BriefDescription": "A high priority read becomes critical.",53 "ConfigCode": "0x9",54 "EventName": "hpr_xact_when_critical",55 "Unit": "ali_drw",56 "Compat": "ali_drw_pmu"57 },58 {59 "BriefDescription": "A low priority read becomes critical.",60 "ConfigCode": "0xA",61 "EventName": "lpr_xact_when_critical",62 "Unit": "ali_drw",63 "Compat": "ali_drw_pmu"64 },65 {66 "BriefDescription": "A write becomes critical.",67 "ConfigCode": "0xB",68 "EventName": "wr_xact_when_critical",69 "Unit": "ali_drw",70 "Compat": "ali_drw_pmu"71 },72 {73 "BriefDescription": "An Activate(ACT) command to DRAM.",74 "ConfigCode": "0xC",75 "EventName": "op_is_activate",76 "Unit": "ali_drw",77 "Compat": "ali_drw_pmu"78 },79 {80 "BriefDescription": "A Read or Write CAS command to DRAM.",81 "ConfigCode": "0xD",82 "EventName": "op_is_rd_or_wr",83 "Unit": "ali_drw",84 "Compat": "ali_drw_pmu"85 },86 {87 "BriefDescription": "An Activate(ACT) command for read to DRAM.",88 "ConfigCode": "0xE",89 "EventName": "op_is_rd_activate",90 "Unit": "ali_drw",91 "Compat": "ali_drw_pmu"92 },93 {94 "BriefDescription": "A Read CAS command to DRAM.",95 "ConfigCode": "0xF",96 "EventName": "op_is_rd",97 "Unit": "ali_drw",98 "Compat": "ali_drw_pmu"99 },100 {101 "BriefDescription": "A Write CAS command to DRAM.",102 "ConfigCode": "0x10",103 "EventName": "op_is_wr",104 "Unit": "ali_drw",105 "Compat": "ali_drw_pmu"106 },107 {108 "BriefDescription": "A Masked Write command to DRAM.",109 "ConfigCode": "0x11",110 "EventName": "op_is_mwr",111 "Unit": "ali_drw",112 "Compat": "ali_drw_pmu"113 },114 {115 "BriefDescription": "A Precharge(PRE) command to DRAM.",116 "ConfigCode": "0x12",117 "EventName": "op_is_precharge",118 "Unit": "ali_drw",119 "Compat": "ali_drw_pmu"120 },121 {122 "BriefDescription": "A Precharge(PRE) required by read or write.",123 "ConfigCode": "0x13",124 "EventName": "precharge_for_rdwr",125 "Unit": "ali_drw",126 "Compat": "ali_drw_pmu"127 },128 {129 "BriefDescription": "A Precharge(PRE) required by other conditions.",130 "ConfigCode": "0x14",131 "EventName": "precharge_for_other",132 "Unit": "ali_drw",133 "Compat": "ali_drw_pmu"134 },135 {136 "BriefDescription": "A read-write turnaround.",137 "ConfigCode": "0x15",138 "EventName": "rdwr_transitions",139 "Unit": "ali_drw",140 "Compat": "ali_drw_pmu"141 },142 {143 "BriefDescription": "A write combine(merge) in write data buffer.",144 "ConfigCode": "0x16",145 "EventName": "write_combine",146 "Unit": "ali_drw",147 "Compat": "ali_drw_pmu"148 },149 {150 "BriefDescription": "A Write-After-Read hazard.",151 "ConfigCode": "0x17",152 "EventName": "war_hazard",153 "Unit": "ali_drw",154 "Compat": "ali_drw_pmu"155 },156 {157 "BriefDescription": "A Read-After-Write hazard.",158 "ConfigCode": "0x18",159 "EventName": "raw_hazard",160 "Unit": "ali_drw",161 "Compat": "ali_drw_pmu"162 },163 {164 "BriefDescription": "A Write-After-Write hazard.",165 "ConfigCode": "0x19",166 "EventName": "waw_hazard",167 "Unit": "ali_drw",168 "Compat": "ali_drw_pmu"169 },170 {171 "BriefDescription": "Rank0 enters self-refresh(SRE).",172 "ConfigCode": "0x1A",173 "EventName": "op_is_enter_selfref_rk0",174 "Unit": "ali_drw",175 "Compat": "ali_drw_pmu"176 },177 {178 "BriefDescription": "Rank1 enters self-refresh(SRE).",179 "ConfigCode": "0x1B",180 "EventName": "op_is_enter_selfref_rk1",181 "Unit": "ali_drw",182 "Compat": "ali_drw_pmu"183 },184 {185 "BriefDescription": "Rank2 enters self-refresh(SRE).",186 "ConfigCode": "0x1C",187 "EventName": "op_is_enter_selfref_rk2",188 "Unit": "ali_drw",189 "Compat": "ali_drw_pmu"190 },191 {192 "BriefDescription": "Rank3 enters self-refresh(SRE).",193 "ConfigCode": "0x1D",194 "EventName": "op_is_enter_selfref_rk3",195 "Unit": "ali_drw",196 "Compat": "ali_drw_pmu"197 },198 {199 "BriefDescription": "Rank0 enters power-down(PDE).",200 "ConfigCode": "0x1E",201 "EventName": "op_is_enter_powerdown_rk0",202 "Unit": "ali_drw",203 "Compat": "ali_drw_pmu"204 },205 {206 "BriefDescription": "Rank1 enters power-down(PDE).",207 "ConfigCode": "0x1F",208 "EventName": "op_is_enter_powerdown_rk1",209 "Unit": "ali_drw",210 "Compat": "ali_drw_pmu"211 },212 {213 "BriefDescription": "Rank2 enters power-down(PDE).",214 "ConfigCode": "0x20",215 "EventName": "op_is_enter_powerdown_rk2",216 "Unit": "ali_drw",217 "Compat": "ali_drw_pmu"218 },219 {220 "BriefDescription": "Rank3 enters power-down(PDE).",221 "ConfigCode": "0x21",222 "EventName": "op_is_enter_powerdown_rk3",223 "Unit": "ali_drw",224 "Compat": "ali_drw_pmu"225 },226 {227 "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",228 "ConfigCode": "0x26",229 "EventName": "selfref_mode_rk0",230 "Unit": "ali_drw",231 "Compat": "ali_drw_pmu"232 },233 {234 "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",235 "ConfigCode": "0x27",236 "EventName": "selfref_mode_rk1",237 "Unit": "ali_drw",238 "Compat": "ali_drw_pmu"239 },240 {241 "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",242 "ConfigCode": "0x28",243 "EventName": "selfref_mode_rk2",244 "Unit": "ali_drw",245 "Compat": "ali_drw_pmu"246 },247 {248 "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",249 "ConfigCode": "0x29",250 "EventName": "selfref_mode_rk3",251 "Unit": "ali_drw",252 "Compat": "ali_drw_pmu"253 },254 {255 "BriefDescription": "An auto-refresh(REF) command to DRAM.",256 "ConfigCode": "0x2A",257 "EventName": "op_is_refresh",258 "Unit": "ali_drw",259 "Compat": "ali_drw_pmu"260 },261 {262 "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",263 "ConfigCode": "0x2B",264 "EventName": "op_is_crit_ref",265 "Unit": "ali_drw",266 "Compat": "ali_drw_pmu"267 },268 {269 "BriefDescription": "An MRR or MRW command to DRAM.",270 "ConfigCode": "0x2D",271 "EventName": "op_is_load_mode",272 "Unit": "ali_drw",273 "Compat": "ali_drw_pmu"274 },275 {276 "BriefDescription": "A ZQCal command to DRAM.",277 "ConfigCode": "0x2E",278 "EventName": "op_is_zqcl",279 "Unit": "ali_drw",280 "Compat": "ali_drw_pmu"281 },282 {283 "BriefDescription": "At least one entry in read queue reaches the visible window limit.",284 "ConfigCode": "0x30",285 "EventName": "visible_window_limit_reached_rd",286 "Unit": "ali_drw",287 "Compat": "ali_drw_pmu"288 },289 {290 "BriefDescription": "At least one entry in write queue reaches the visible window limit.",291 "ConfigCode": "0x31",292 "EventName": "visible_window_limit_reached_wr",293 "Unit": "ali_drw",294 "Compat": "ali_drw_pmu"295 },296 {297 "BriefDescription": "A DQS Oscillator MPC command to DRAM.",298 "ConfigCode": "0x34",299 "EventName": "op_is_dqsosc_mpc",300 "Unit": "ali_drw",301 "Compat": "ali_drw_pmu"302 },303 {304 "BriefDescription": "A DQS Oscillator MRR command to DRAM.",305 "ConfigCode": "0x35",306 "EventName": "op_is_dqsosc_mrr",307 "Unit": "ali_drw",308 "Compat": "ali_drw_pmu"309 },310 {311 "BriefDescription": "A Temperature Compensated Refresh(TCR) MRR command to DRAM.",312 "ConfigCode": "0x36",313 "EventName": "op_is_tcr_mrr",314 "Unit": "ali_drw",315 "Compat": "ali_drw_pmu"316 },317 {318 "BriefDescription": "A ZQCal Start command to DRAM.",319 "ConfigCode": "0x37",320 "EventName": "op_is_zqstart",321 "Unit": "ali_drw",322 "Compat": "ali_drw_pmu"323 },324 {325 "BriefDescription": "A ZQCal Latch command to DRAM.",326 "ConfigCode": "0x38",327 "EventName": "op_is_zqlatch",328 "Unit": "ali_drw",329 "Compat": "ali_drw_pmu"330 },331 {332 "BriefDescription": "A packet at CHI TXREQ interface (request).",333 "ConfigCode": "0x39",334 "EventName": "chi_txreq",335 "Unit": "ali_drw",336 "Compat": "ali_drw_pmu"337 },338 {339 "BriefDescription": "A packet at CHI TXDAT interface (read data).",340 "ConfigCode": "0x3A",341 "EventName": "chi_txdat",342 "Unit": "ali_drw",343 "Compat": "ali_drw_pmu"344 },345 {346 "BriefDescription": "A packet at CHI RXDAT interface (write data).",347 "ConfigCode": "0x3B",348 "EventName": "chi_rxdat",349 "Unit": "ali_drw",350 "Compat": "ali_drw_pmu"351 },352 {353 "BriefDescription": "A packet at CHI RXRSP interface.",354 "ConfigCode": "0x3C",355 "EventName": "chi_rxrsp",356 "Unit": "ali_drw",357 "Compat": "ali_drw_pmu"358 },359 {360 "BriefDescription": "A violation detected in TZC.",361 "ConfigCode": "0x3D",362 "EventName": "tsz_vio",363 "Unit": "ali_drw",364 "Compat": "ali_drw_pmu"365 },366 {367 "BriefDescription": "The ddr cycles.",368 "ConfigCode": "0x80",369 "EventName": "ddr_cycles",370 "Unit": "ali_drw",371 "Compat": "ali_drw_pmu"372 }373]374