143 lines · json
1[2 {3 "EventCode": "0x1C040",4 "EventName": "PM_XFER_FROM_SRC_PMC1",5 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."6 },7 {8 "EventCode": "0x1C056",9 "EventName": "PM_DERAT_MISS_4K",10 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."11 },12 {13 "EventCode": "0x1C058",14 "EventName": "PM_DTLB_MISS_16G",15 "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."16 },17 {18 "EventCode": "0x1C05C",19 "EventName": "PM_DTLB_MISS_2M",20 "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."21 },22 {23 "EventCode": "0x10062",24 "EventName": "PM_LD_L3MISS_PEND_CYC",25 "BriefDescription": "Cycles in which an L3 miss was pending for this thread."26 },27 {28 "EventCode": "0x2001A",29 "EventName": "PM_ITLB_HIT",30 "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."31 },32 {33 "EventCode": "0x2003E",34 "EventName": "PM_PTESYNC_FIN",35 "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."36 },37 {38 "EventCode": "0x2C040",39 "EventName": "PM_XFER_FROM_SRC_PMC2",40 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."41 },42 {43 "EventCode": "0x2C054",44 "EventName": "PM_DERAT_MISS_64K",45 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."46 },47 {48 "EventCode": "0x2C056",49 "EventName": "PM_DTLB_MISS_4K",50 "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."51 },52 {53 "EventCode": "0x2C05A",54 "EventName": "PM_DERAT_MISS_1G",55 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."56 },57 {58 "EventCode": "0x200F6",59 "EventName": "PM_DERAT_MISS",60 "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."61 },62 {63 "EventCode": "0x34044",64 "EventName": "PM_DERAT_MISS_PREF",65 "BriefDescription": "DERAT miss (TLB access) while servicing a data prefetch."66 },67 {68 "EventCode": "0x3C040",69 "EventName": "PM_XFER_FROM_SRC_PMC3",70 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."71 },72 {73 "EventCode": "0x3F04A",74 "EventName": "PM_LSU_ST5_FIN",75 "BriefDescription": "LSU Finished an internal operation in ST2 port."76 },77 {78 "EventCode": "0x3C054",79 "EventName": "PM_DERAT_MISS_16M",80 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."81 },82 {83 "EventCode": "0x3C056",84 "EventName": "PM_DTLB_MISS_64K",85 "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."86 },87 {88 "EventCode": "0x3C058",89 "EventName": "PM_LARX_FIN",90 "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."91 },92 {93 "EventCode": "0x300FC",94 "EventName": "PM_DTLB_MISS",95 "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."96 },97 {98 "EventCode": "0x4003E",99 "EventName": "PM_LD_CMPL",100 "BriefDescription": "Load instruction completed."101 },102 {103 "EventCode": "0x4C040",104 "EventName": "PM_XFER_FROM_SRC_PMC4",105 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."106 },107 {108 "EventCode": "0x4C056",109 "EventName": "PM_DTLB_MISS_16M",110 "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."111 },112 {113 "EventCode": "0x4C05A",114 "EventName": "PM_DTLB_MISS_1G",115 "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."116 },117 {118 "EventCode": "0x000000F880",119 "EventName": "PM_SNOOP_TLBIE_CYC",120 "BriefDescription": "Cycles in which TLBIE snoops are executed in the LSU."121 },122 {123 "EventCode": "0x000000F084",124 "EventName": "PM_SNOOP_TLBIE_CACHE_WALK_CYC",125 "BriefDescription": "TLBIE snoop cycles in which the data cache is being walked."126 },127 {128 "EventCode": "0x000000F884",129 "EventName": "PM_SNOOP_TLBIE_WAIT_ST_CYC",130 "BriefDescription": "TLBIE snoop cycles in which older stores are still draining."131 },132 {133 "EventCode": "0x000000F088",134 "EventName": "PM_SNOOP_TLBIE_WAIT_LD_CYC",135 "BriefDescription": "TLBIE snoop cycles in which older loads are still draining."136 },137 {138 "EventCode": "0x000000F08C",139 "EventName": "PM_SNOOP_TLBIE_WAIT_MMU_CYC",140 "BriefDescription": "TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation."141 }142]143