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1[2 {3 "BriefDescription": "Percentage of cycles that are run cycles",4 "MetricExpr": "PM_RUN_CYC / PM_CYC * 100",5 "MetricGroup": "General",6 "MetricName": "RUN_CYCLES_RATE",7 "ScaleUnit": "1%"8 },9 {10 "BriefDescription": "Average cycles per completed instruction",11 "MetricExpr": "PM_CYC / PM_INST_CMPL",12 "MetricGroup": "CPI",13 "MetricName": "CYCLES_PER_INSTRUCTION"14 },15 {16 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled for any reason",17 "MetricExpr": "PM_DISP_STALL_CYC / PM_RUN_INST_CMPL",18 "MetricGroup": "CPI;CPI_STALL_RATIO",19 "MetricName": "DISPATCH_STALL_CPI"20 },21 {22 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled because there was a flush",23 "MetricExpr": "PM_DISP_STALL_FLUSH / PM_RUN_INST_CMPL",24 "MetricGroup": "CPI",25 "MetricName": "DISPATCH_STALL_FLUSH_CPI"26 },27 {28 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled because Fetch was being held, so there was nothing in the pipeline for this thread",29 "MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",30 "MetricGroup": "CPI",31 "MetricName": "DISPATCH_STALL_FETCH_CPI"32 },33 {34 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled because the MMU was handling a translation miss",35 "MetricExpr": "PM_DISP_STALL_TRANSLATION / PM_RUN_INST_CMPL",36 "MetricGroup": "CPI",37 "MetricName": "DISPATCH_STALL_TRANSLATION_CPI"38 },39 {40 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve an instruction ERAT miss",41 "MetricExpr": "PM_DISP_STALL_IERAT_ONLY_MISS / PM_RUN_INST_CMPL",42 "MetricGroup": "CPI",43 "MetricName": "DISPATCH_STALL_IERAT_ONLY_MISS_CPI"44 },45 {46 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled waiting to resolve an instruction TLB miss",47 "MetricExpr": "PM_DISP_STALL_ITLB_MISS / PM_RUN_INST_CMPL",48 "MetricGroup": "CPI",49 "MetricName": "DISPATCH_STALL_ITLB_MISS_CPI"50 },51 {52 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an icache miss",53 "MetricExpr": "PM_DISP_STALL_IC_MISS / PM_RUN_INST_CMPL",54 "MetricGroup": "CPI",55 "MetricName": "DISPATCH_STALL_IC_MISS_CPI"56 },57 {58 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from the local L2",59 "MetricExpr": "PM_DISP_STALL_IC_L2 / PM_RUN_INST_CMPL",60 "MetricGroup": "CPI",61 "MetricName": "DISPATCH_STALL_IC_L2_CPI"62 },63 {64 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from the local L3",65 "MetricExpr": "PM_DISP_STALL_IC_L3 / PM_RUN_INST_CMPL",66 "MetricGroup": "CPI",67 "MetricName": "DISPATCH_STALL_IC_L3_CPI"68 },69 {70 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while the instruction was fetched from any source beyond the local L3",71 "MetricExpr": "PM_DISP_STALL_IC_L3MISS / PM_RUN_INST_CMPL",72 "MetricGroup": "CPI",73 "MetricName": "DISPATCH_STALL_IC_L3MISS_CPI"74 },75 {76 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to an icache miss after a branch mispredict",77 "MetricExpr": "PM_DISP_STALL_BR_MPRED_ICMISS / PM_RUN_INST_CMPL",78 "MetricGroup": "CPI",79 "MetricName": "DISPATCH_STALL_BR_MPRED_ICMISS_CPI"80 },81 {82 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from the local L2 after suffering a branch mispredict",83 "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L2 / PM_RUN_INST_CMPL",84 "MetricGroup": "CPI",85 "MetricName": "DISPATCH_STALL_BR_MPRED_IC_L2_CPI"86 },87 {88 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from the local L3 after suffering a branch mispredict",89 "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3 / PM_RUN_INST_CMPL",90 "MetricGroup": "CPI",91 "MetricName": "DISPATCH_STALL_BR_MPRED_IC_L3_CPI"92 },93 {94 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled while instruction was fetched from any source beyond the local L3 after suffering a branch mispredict",95 "MetricExpr": "PM_DISP_STALL_BR_MPRED_IC_L3MISS / PM_RUN_INST_CMPL",96 "MetricGroup": "CPI",97 "MetricName": "DISPATCH_STALL_BR_MPRED_IC_L3MISS_CPI"98 },99 {100 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled due to a branch mispredict",101 "MetricExpr": "PM_DISP_STALL_BR_MPRED / PM_RUN_INST_CMPL",102 "MetricGroup": "CPI",103 "MetricName": "DISPATCH_STALL_BR_MPRED_CPI"104 },105 {106 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch for any reason",107 "MetricExpr": "PM_DISP_STALL_HELD_CYC / PM_RUN_INST_CMPL",108 "MetricGroup": "CPI",109 "MetricName": "DISPATCH_STALL_HELD_CPI"110 },111 {112 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch",113 "MetricExpr": "PM_DISP_STALL_HELD_SYNC_CYC / PM_RUN_INST_CMPL",114 "MetricGroup": "CPI",115 "MetricName": "DISPATCH_STALL_HELD_SYNC_CPI"116 },117 {118 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch while waiting on the scoreboard",119 "MetricExpr": "PM_DISP_STALL_HELD_SCOREBOARD_CYC / PM_RUN_INST_CMPL",120 "MetricGroup": "CPI",121 "MetricName": "DISPATCH_STALL_HELD_SCOREBOARD_CPI"122 },123 {124 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch due to issue queue full",125 "MetricExpr": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC / PM_RUN_INST_CMPL",126 "MetricGroup": "CPI",127 "MetricName": "DISPATCH_STALL_HELD_ISSQ_FULL_CPI"128 },129 {130 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the mapper/SRB was full",131 "MetricExpr": "PM_DISP_STALL_HELD_RENAME_CYC / PM_RUN_INST_CMPL",132 "MetricGroup": "CPI",133 "MetricName": "DISPATCH_STALL_HELD_RENAME_CPI"134 },135 {136 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the STF mapper/SRB was full",137 "MetricExpr": "PM_DISP_STALL_HELD_STF_MAPPER_CYC / PM_RUN_INST_CMPL",138 "MetricGroup": "CPI",139 "MetricName": "DISPATCH_STALL_HELD_STF_MAPPER_CPI"140 },141 {142 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because the XVFC mapper/SRB was full",143 "MetricExpr": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC / PM_RUN_INST_CMPL",144 "MetricGroup": "CPI",145 "MetricName": "DISPATCH_STALL_HELD_XVFC_MAPPER_CPI"146 },147 {148 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch for any other reason",149 "MetricExpr": "PM_DISP_STALL_HELD_OTHER_CYC / PM_RUN_INST_CMPL",150 "MetricGroup": "CPI",151 "MetricName": "DISPATCH_STALL_HELD_OTHER_CPI"152 },153 {154 "BriefDescription": "Average cycles per completed instruction when the NTC instruction has been dispatched but not issued for any reason",155 "MetricExpr": "PM_ISSUE_STALL / PM_RUN_INST_CMPL",156 "MetricGroup": "CPI;CPI_STALL_RATIO",157 "MetricName": "ISSUE_STALL_CPI"158 },159 {160 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting to be finished in one of the execution units",161 "MetricExpr": "PM_EXEC_STALL / PM_RUN_INST_CMPL",162 "MetricGroup": "CPI;CPI_STALL_RATIO",163 "MetricName": "EXECUTION_STALL_CPI"164 },165 {166 "BriefDescription": "Average cycles per completed instruction spent executing an NTC instruction that gets flushed some time after dispatch",167 "MetricExpr": "PM_EXEC_STALL_NTC_FLUSH / PM_RUN_INST_CMPL",168 "MetricGroup": "CPI",169 "MetricName": "NTC_FLUSH_STALL_CPI"170 },171 {172 "BriefDescription": "Average cycles per completed instruction when the NTF instruction finishes at dispatch",173 "MetricExpr": "PM_EXEC_STALL_FIN_AT_DISP / PM_RUN_INST_CMPL",174 "MetricGroup": "CPI",175 "MetricName": "FIN_AT_DISP_STALL_CPI"176 },177 {178 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the branch unit",179 "MetricExpr": "PM_EXEC_STALL_BRU / PM_RUN_INST_CMPL",180 "MetricGroup": "CPI",181 "MetricName": "BRU_STALL_CPI"182 },183 {184 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a simple fixed point instruction that is executing in the LSU",185 "MetricExpr": "PM_EXEC_STALL_SIMPLE_FX / PM_RUN_INST_CMPL",186 "MetricGroup": "CPI",187 "MetricName": "SIMPLE_FX_STALL_CPI"188 },189 {190 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the VSU",191 "MetricExpr": "PM_EXEC_STALL_VSU / PM_RUN_INST_CMPL",192 "MetricGroup": "CPI",193 "MetricName": "VSU_STALL_CPI"194 },195 {196 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting to be finished in one of the execution units",197 "MetricExpr": "PM_EXEC_STALL_TRANSLATION / PM_RUN_INST_CMPL",198 "MetricGroup": "CPI",199 "MetricName": "TRANSLATION_STALL_CPI"200 },201 {202 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a load or store that suffered a translation miss",203 "MetricExpr": "PM_EXEC_STALL_DERAT_ONLY_MISS / PM_RUN_INST_CMPL",204 "MetricGroup": "CPI",205 "MetricName": "DERAT_ONLY_MISS_STALL_CPI"206 },207 {208 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is recovering from a TLB miss",209 "MetricExpr": "PM_EXEC_STALL_DERAT_DTLB_MISS / PM_RUN_INST_CMPL",210 "MetricGroup": "CPI",211 "MetricName": "DERAT_DTLB_MISS_STALL_CPI"212 },213 {214 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing in the LSU",215 "MetricExpr": "PM_EXEC_STALL_LSU / PM_RUN_INST_CMPL",216 "MetricGroup": "CPI",217 "MetricName": "LSU_STALL_CPI"218 },219 {220 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a load that is executing in the LSU",221 "MetricExpr": "PM_EXEC_STALL_LOAD / PM_RUN_INST_CMPL",222 "MetricGroup": "CPI",223 "MetricName": "LOAD_STALL_CPI"224 },225 {226 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3",227 "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3 / PM_RUN_INST_CMPL",228 "MetricGroup": "CPI",229 "MetricName": "DMISS_L2L3_STALL_CPI"230 },231 {232 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, with an RC dispatch conflict",233 "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT / PM_RUN_INST_CMPL",234 "MetricGroup": "CPI",235 "MetricName": "DMISS_L2L3_CONFLICT_STALL_CPI"236 },237 {238 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from either the local L2 or local L3, without an RC dispatch conflict",239 "MetricExpr": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT / PM_RUN_INST_CMPL",240 "MetricGroup": "CPI",241 "MetricName": "DMISS_L2L3_NOCONFLICT_STALL_CPI"242 },243 {244 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a source beyond the local L2 and local L3",245 "MetricExpr": "PM_EXEC_STALL_DMISS_L3MISS / PM_RUN_INST_CMPL",246 "MetricGroup": "CPI",247 "MetricName": "DMISS_L3MISS_STALL_CPI"248 },249 {250 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a neighbor chiplet's L2 or L3 in the same chip",251 "MetricExpr": "PM_EXEC_STALL_DMISS_L21_L31 / PM_RUN_INST_CMPL",252 "MetricGroup": "CPI",253 "MetricName": "DMISS_L21_L31_STALL_CPI"254 },255 {256 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from L4, local memory or OpenCAPI chip",257 "MetricExpr": "PM_EXEC_STALL_DMISS_LMEM / PM_RUN_INST_CMPL",258 "MetricGroup": "CPI",259 "MetricName": "DMISS_LMEM_STALL_CPI"260 },261 {262 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a remote chip (cache, L4, memory or OpenCAPI) in the same group",263 "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_CHIP / PM_RUN_INST_CMPL",264 "MetricGroup": "CPI",265 "MetricName": "DMISS_OFF_CHIP_STALL_CPI"266 },267 {268 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is waiting for a load miss to resolve from a distant chip (cache, L4, memory or OpenCAPI chip)",269 "MetricExpr": "PM_EXEC_STALL_DMISS_OFF_NODE / PM_RUN_INST_CMPL",270 "MetricGroup": "CPI",271 "MetricName": "DMISS_OFF_NODE_STALL_CPI"272 },273 {274 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing a TLBIEL instruction",275 "MetricExpr": "PM_EXEC_STALL_TLBIEL / PM_RUN_INST_CMPL",276 "MetricGroup": "CPI",277 "MetricName": "TLBIEL_STALL_CPI"278 },279 {280 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is finishing a load after its data has been reloaded from a data source beyond the local L1, OR when the LSU is processing an L1-hit, OR when the NTF instruction merged with another load in the LMQ",281 "MetricExpr": "PM_EXEC_STALL_LOAD_FINISH / PM_RUN_INST_CMPL",282 "MetricGroup": "CPI",283 "MetricName": "LOAD_FINISH_STALL_CPI"284 },285 {286 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a store that is executing in the LSU",287 "MetricExpr": "PM_EXEC_STALL_STORE / PM_RUN_INST_CMPL",288 "MetricGroup": "CPI",289 "MetricName": "STORE_STALL_CPI"290 },291 {292 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is in the store unit outside of handling store misses or other special store operations",293 "MetricExpr": "PM_EXEC_STALL_STORE_PIPE / PM_RUN_INST_CMPL",294 "MetricGroup": "CPI",295 "MetricName": "STORE_PIPE_STALL_CPI"296 },297 {298 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a store whose cache line was not resident in the L1 and had to wait for allocation of the missing line into the L1",299 "MetricExpr": "PM_EXEC_STALL_STORE_MISS / PM_RUN_INST_CMPL",300 "MetricGroup": "CPI",301 "MetricName": "STORE_MISS_STALL_CPI"302 },303 {304 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a TLBIE instruction waiting for a response from the L2",305 "MetricExpr": "PM_EXEC_STALL_TLBIE / PM_RUN_INST_CMPL",306 "MetricGroup": "CPI",307 "MetricName": "TLBIE_STALL_CPI"308 },309 {310 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is executing a PTESYNC instruction",311 "MetricExpr": "PM_EXEC_STALL_PTESYNC / PM_RUN_INST_CMPL",312 "MetricGroup": "CPI",313 "MetricName": "PTESYNC_STALL_CPI"314 },315 {316 "BriefDescription": "Average cycles per completed instruction when the NTC instruction cannot complete because the thread was blocked",317 "MetricExpr": "PM_CMPL_STALL / PM_RUN_INST_CMPL",318 "MetricGroup": "CPI;CPI_STALL_RATIO",319 "MetricName": "COMPLETION_STALL_CPI"320 },321 {322 "BriefDescription": "Average cycles per completed instruction when the NTC instruction cannot complete because it was interrupted by ANY exception",323 "MetricExpr": "PM_CMPL_STALL_EXCEPTION / PM_RUN_INST_CMPL",324 "MetricGroup": "CPI",325 "MetricName": "EXCEPTION_COMPLETION_STALL_CPI"326 },327 {328 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is stuck at finish waiting for the non-speculative finish of either a STCX instruction waiting for its result or a load waiting for non-critical sectors of data and ECC",329 "MetricExpr": "PM_CMPL_STALL_MEM_ECC / PM_RUN_INST_CMPL",330 "MetricGroup": "CPI",331 "MetricName": "MEM_ECC_COMPLETION_STALL_CPI"332 },333 {334 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a STCX instruction waiting for resolution from the nest",335 "MetricExpr": "PM_CMPL_STALL_STCX / PM_RUN_INST_CMPL",336 "MetricGroup": "CPI",337 "MetricName": "STCX_COMPLETION_STALL_CPI"338 },339 {340 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a LWSYNC instruction waiting to complete",341 "MetricExpr": "PM_CMPL_STALL_LWSYNC / PM_RUN_INST_CMPL",342 "MetricGroup": "CPI",343 "MetricName": "LWSYNC_COMPLETION_STALL_CPI"344 },345 {346 "BriefDescription": "Average cycles per completed instruction when the NTC instruction is a HWSYNC instruction stuck at finish waiting for a response from the L2",347 "MetricExpr": "PM_CMPL_STALL_HWSYNC / PM_RUN_INST_CMPL",348 "MetricGroup": "CPI",349 "MetricName": "HWSYNC_COMPLETION_STALL_CPI"350 },351 {352 "BriefDescription": "Average cycles per completed instruction when the NTC instruction required special handling before completion",353 "MetricExpr": "PM_CMPL_STALL_SPECIAL / PM_RUN_INST_CMPL",354 "MetricGroup": "CPI",355 "MetricName": "SPECIAL_COMPLETION_STALL_CPI"356 },357 {358 "BriefDescription": "Average cycles per completed instruction when dispatch was stalled because fetch was being held, so there was nothing in the pipeline for this thread",359 "MetricExpr": "PM_DISP_STALL_FETCH / PM_RUN_INST_CMPL",360 "MetricGroup": "CPI",361 "MetricName": "DISPATCH_STALL_FETCH_CPI"362 },363 {364 "BriefDescription": "Average cycles per completed instruction when the NTC instruction was held at dispatch because of power management",365 "MetricExpr": "PM_DISP_STALL_HELD_HALT_CYC / PM_RUN_INST_CMPL",366 "MetricGroup": "CPI",367 "MetricName": "DISPATCH_STALL_HELD_HALT_CPI"368 },369 {370 "BriefDescription": "Percentage of flushes per completed instruction",371 "MetricExpr": "PM_FLUSH / PM_RUN_INST_CMPL * 100",372 "MetricGroup": "Others",373 "MetricName": "FLUSH_RATE",374 "ScaleUnit": "1%"375 },376 {377 "BriefDescription": "Percentage of flushes due to a branch mispredict per completed instruction",378 "MetricExpr": "PM_FLUSH_MPRED / PM_RUN_INST_CMPL * 100",379 "MetricGroup": "Others",380 "MetricName": "BR_MPRED_FLUSH_RATE",381 "ScaleUnit": "1%"382 },383 {384 "BriefDescription": "Percentage of branch mispredictions per completed instruction",385 "MetricExpr": "PM_BR_MPRED_CMPL / PM_RUN_INST_CMPL",386 "MetricGroup": "Others",387 "MetricName": "BRANCH_MISPREDICTION_RATE"388 },389 {390 "BriefDescription": "Percentage of finished loads that missed in the L1",391 "MetricExpr": "PM_LD_MISS_L1 / PM_LD_REF_L1 * 100",392 "MetricGroup": "Others",393 "MetricName": "L1_LD_MISS_RATIO",394 "ScaleUnit": "1%"395 },396 {397 "BriefDescription": "Percentage of completed instructions that were loads that missed the L1",398 "MetricExpr": "PM_LD_MISS_L1 / PM_RUN_INST_CMPL * 100",399 "MetricGroup": "Others",400 "MetricName": "L1_LD_MISS_RATE",401 "ScaleUnit": "1%"402 },403 {404 "BriefDescription": "Percentage of completed instructions that were stores that missed the L1",405 "MetricExpr": "PM_ST_MISS_L1 * 100 / PM_RUN_INST_CMPL",406 "MetricGroup": "Others",407 "MetricName": "L1_ST_MISS_RATE",408 "ScaleUnit": "1%"409 },410 {411 "BriefDescription": "Percentage of completed instructions when the DPTEG required for the load/store instruction in execution was missing from the TLB",412 "MetricExpr": "PM_DTLB_MISS / PM_RUN_INST_CMPL * 100",413 "MetricGroup": "Others",414 "MetricName": "DTLB_MISS_RATE",415 "ScaleUnit": "1%"416 },417 {418 "BriefDescription": "Average number of completed instructions dispatched per instruction completed",419 "MetricExpr": "PM_INST_DISP / PM_RUN_INST_CMPL",420 "MetricGroup": "General",421 "MetricName": "DISPATCH_PER_INST_CMPL"422 },423 {424 "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1 or L2",425 "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",426 "MetricGroup": "General",427 "MetricName": "L2_LD_MISS_RATE",428 "ScaleUnit": "1%"429 },430 {431 "BriefDescription": "Percentage of completed instructions that were demand fetches that missed the L1 icache",432 "MetricExpr": "PM_L1_ICACHE_MISS / PM_RUN_INST_CMPL * 100",433 "MetricGroup": "Instruction_Misses",434 "MetricName": "L1_INST_MISS_RATE",435 "ScaleUnit": "1%"436 },437 {438 "BriefDescription": "Percentage of completed instructions that were demand fetches that missed the L1 and L2 instruction cache",439 "MetricExpr": "PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",440 "MetricGroup": "General",441 "MetricName": "L2_INST_MISS_RATE",442 "ScaleUnit": "1%"443 },444 {445 "BriefDescription": "Percentage of completed instructions that were demand fetches that reloaded from beyond the L3 icache",446 "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",447 "MetricGroup": "General",448 "MetricName": "L3_INST_MISS_RATE",449 "ScaleUnit": "1%"450 },451 {452 "BriefDescription": "Average number of completed instructions per cycle",453 "MetricExpr": "PM_INST_CMPL / PM_CYC",454 "MetricGroup": "General",455 "MetricName": "IPC"456 },457 {458 "BriefDescription": "Average number of cycles per completed instruction group",459 "MetricExpr": "PM_CYC / PM_1PLUS_PPC_CMPL",460 "MetricGroup": "General",461 "MetricName": "CYCLES_PER_COMPLETED_INSTRUCTIONS_SET"462 },463 {464 "BriefDescription": "Percentage of cycles when at least 1 instruction dispatched",465 "MetricExpr": "PM_1PLUS_PPC_DISP / PM_RUN_CYC * 100",466 "MetricGroup": "General",467 "MetricName": "CYCLES_ATLEAST_ONE_INST_DISPATCHED",468 "ScaleUnit": "1%"469 },470 {471 "BriefDescription": "Average number of finished loads per completed instruction",472 "MetricExpr": "PM_LD_REF_L1 / PM_RUN_INST_CMPL",473 "MetricGroup": "General",474 "MetricName": "LOADS_PER_INST"475 },476 {477 "BriefDescription": "Percentage of demand loads that reloaded from the L2 per completed instruction",478 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_RUN_INST_CMPL",479 "MetricGroup": "dL1_Reloads",480 "MetricName": "DL1_RELOAD_FROM_L2_RATE",481 "ScaleUnit": "1%"482 },483 {484 "BriefDescription": "Percentage of demand loads that reloaded from beyond the L2 per completed instruction",485 "MetricExpr": "PM_DATA_FROM_L2MISS / PM_RUN_INST_CMPL * 100",486 "MetricGroup": "dL1_Reloads",487 "MetricName": "DL1_RELOAD_FROM_L2_MISS_RATE",488 "ScaleUnit": "1%"489 },490 {491 "BriefDescription": "Percentage of demand loads that reloaded using modified data from another core's L2 or L3 on a remote chip, per completed instruction",492 "MetricExpr": "PM_DATA_FROM_RL2L3_MOD * 100 / PM_RUN_INST_CMPL",493 "MetricGroup": "dL1_Reloads",494 "MetricName": "DL1_RELOAD_FROM_RL2L3_MOD_RATE",495 "ScaleUnit": "1%"496 },497 {498 "BriefDescription": "Percentage of demand loads that reloaded using shared data from another core's L2 or L3 on a remote chip, per completed instruction",499 "MetricExpr": "PM_DATA_FROM_RL2L3_SHR * 100 / PM_RUN_INST_CMPL",500 "MetricGroup": "dL1_Reloads",501 "MetricName": "DL1_RELOAD_FROM_RL2L3_SHR_RATE",502 "ScaleUnit": "1%"503 },504 {505 "BriefDescription": "Percentage of demand loads that reloaded from the L3 per completed instruction",506 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_RUN_INST_CMPL",507 "MetricGroup": "dL1_Reloads",508 "MetricName": "DL1_RELOAD_FROM_L3_RATE",509 "ScaleUnit": "1%"510 },511 {512 "BriefDescription": "Percentage of demand loads that reloaded with data brought into the L3 by prefetch per completed instruction",513 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_RUN_INST_CMPL",514 "MetricGroup": "dL1_Reloads",515 "MetricName": "DL1_RELOAD_FROM_L3_MEPF_RATE",516 "ScaleUnit": "1%"517 },518 {519 "BriefDescription": "Percentage of demand loads that reloaded from beyond the L3 per completed instruction",520 "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",521 "MetricGroup": "dL1_Reloads",522 "MetricName": "DL1_RELOAD_FROM_L3_MISS_RATE",523 "ScaleUnit": "1%"524 },525 {526 "BriefDescription": "Percentage of demand loads that reloaded using modified data from another core's L2 or L3 on a distant chip, per completed instruction",527 "MetricExpr": "PM_DATA_FROM_DL2L3_MOD * 100 / PM_RUN_INST_CMPL",528 "MetricGroup": "dL1_Reloads",529 "MetricName": "DL1_RELOAD_FROM_DL2L3_MOD_RATE",530 "ScaleUnit": "1%"531 },532 {533 "BriefDescription": "Percentage of demand loads that reloaded using shared data from another core's L2 or L3 on a distant chip, per completed instruction",534 "MetricExpr": "PM_DATA_FROM_DL2L3_SHR * 100 / PM_RUN_INST_CMPL",535 "MetricGroup": "dL1_Reloads",536 "MetricName": "DL1_RELOAD_FROM_DL2L3_SHR_RATE",537 "ScaleUnit": "1%"538 },539 {540 "BriefDescription": "Percentage of demand loads that reloaded from local memory per completed instruction",541 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_RUN_INST_CMPL",542 "MetricGroup": "dL1_Reloads",543 "MetricName": "DL1_RELOAD_FROM_LMEM_RATE",544 "ScaleUnit": "1%"545 },546 {547 "BriefDescription": "Percentage of demand loads that reloaded from remote memory per completed instruction",548 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_RUN_INST_CMPL",549 "MetricGroup": "dL1_Reloads",550 "MetricName": "DL1_RELOAD_FROM_RMEM_RATE",551 "ScaleUnit": "1%"552 },553 {554 "BriefDescription": "Percentage of demand loads that reloaded from distant memory per completed instruction",555 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_RUN_INST_CMPL",556 "MetricGroup": "dL1_Reloads",557 "MetricName": "DL1_RELOAD_FROM_DMEM_RATE",558 "ScaleUnit": "1%"559 },560 {561 "BriefDescription": "Percentage of data reloads from local memory per data reloads from any memory",562 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / (PM_DATA_FROM_LMEM + PM_DATA_FROM_RMEM + PM_DATA_FROM_DMEM)",563 "MetricGroup": "Memory",564 "MetricName": "MEM_LOCALITY",565 "ScaleUnit": "1%"566 },567 {568 "BriefDescription": "Number of data reloads from local memory per data reloads from remote memory",569 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_RMEM",570 "MetricGroup": "Memory",571 "MetricName": "LD_LMEM_PER_LD_RMEM"572 },573 {574 "BriefDescription": "Number of data reloads from local memory per data reloads from distant memory",575 "MetricExpr": "PM_DATA_FROM_LMEM / PM_DATA_FROM_DMEM",576 "MetricGroup": "Memory",577 "MetricName": "LD_LMEM_PER_LD_DMEM"578 },579 {580 "BriefDescription": "Number of data reloads from local memory per data reloads from distant and remote memory",581 "MetricExpr": "PM_DATA_FROM_LMEM / (PM_DATA_FROM_DMEM + PM_DATA_FROM_RMEM)",582 "MetricGroup": "Memory",583 "MetricName": "LD_LMEM_PER_LD_MEM"584 },585 {586 "BriefDescription": "Percentage of ITLB misses per completed run instruction",587 "MetricExpr": "PM_ITLB_MISS / PM_RUN_INST_CMPL * 100",588 "MetricGroup": "General",589 "MetricName": "ITLB_MISS_RATE",590 "ScaleUnit": "1%"591 },592 {593 "BriefDescription": "Number of data reloads from remote memory per data reloads from distant memory",594 "MetricExpr": "PM_DATA_FROM_RMEM / PM_DATA_FROM_DMEM",595 "MetricGroup": "Memory",596 "MetricName": "LD_RMEM_PER_LD_DMEM"597 },598 {599 "BriefDescription": "Percentage of DERAT misses with 4k page size per completed instruction",600 "MetricExpr": "PM_DERAT_MISS_4K / PM_RUN_INST_CMPL * 100",601 "MetricGroup": "Translation",602 "MetricName": "DERAT_4K_MISS_RATE",603 "ScaleUnit": "1%"604 },605 {606 "BriefDescription": "Percentage of DERAT misses with 64k page size per completed instruction",607 "MetricExpr": "PM_DERAT_MISS_64K / PM_RUN_INST_CMPL * 100",608 "MetricGroup": "Translation",609 "MetricName": "DERAT_64K_MISS_RATE",610 "ScaleUnit": "1%"611 },612 {613 "BriefDescription": "Percentage of ICache misses that were reloaded from the L2",614 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_L1_ICACHE_MISS",615 "MetricGroup": "Instruction_Stats",616 "MetricName": "INST_FROM_L2",617 "ScaleUnit": "1%"618 },619 {620 "BriefDescription": "Percentage of ICache misses that were reloaded from the L3",621 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_L1_ICACHE_MISS",622 "MetricGroup": "Instruction_Stats",623 "MetricName": "INST_FROM_L3",624 "ScaleUnit": "1%"625 },626 {627 "BriefDescription": "Percentage of ICache misses that were reloaded from local memory",628 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_L1_ICACHE_MISS",629 "MetricGroup": "Instruction_Stats",630 "MetricName": "INST_FROM_LMEM",631 "ScaleUnit": "1%"632 },633 {634 "BriefDescription": "Percentage of ICache misses that were reloaded from remote memory",635 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_L1_ICACHE_MISS",636 "MetricGroup": "Instruction_Stats",637 "MetricName": "INST_FROM_RMEM",638 "ScaleUnit": "1%"639 },640 {641 "BriefDescription": "Percentage of ICache misses that were reloaded from distant memory",642 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_L1_ICACHE_MISS",643 "MetricGroup": "Instruction_Stats",644 "MetricName": "INST_FROM_DMEM",645 "ScaleUnit": "1%"646 },647 {648 "BriefDescription": "Percentage of ICache reloads from the L2 per completed instruction",649 "MetricExpr": "PM_INST_FROM_L2 * 100 / PM_RUN_INST_CMPL",650 "MetricGroup": "Instruction_Misses",651 "MetricName": "INST_FROM_L2_RATE",652 "ScaleUnit": "1%"653 },654 {655 "BriefDescription": "Percentage of ICache reloads from the L3 per completed instruction",656 "MetricExpr": "PM_INST_FROM_L3 * 100 / PM_RUN_INST_CMPL",657 "MetricGroup": "Instruction_Misses",658 "MetricName": "INST_FROM_L3_RATE",659 "ScaleUnit": "1%"660 },661 {662 "BriefDescription": "Percentage of ICache reloads from local memory per completed instruction",663 "MetricExpr": "PM_INST_FROM_LMEM * 100 / PM_RUN_INST_CMPL",664 "MetricGroup": "Instruction_Misses",665 "MetricName": "INST_FROM_LMEM_RATE",666 "ScaleUnit": "1%"667 },668 {669 "BriefDescription": "Percentage of ICache reloads from remote memory per completed instruction",670 "MetricExpr": "PM_INST_FROM_RMEM * 100 / PM_RUN_INST_CMPL",671 "MetricGroup": "Instruction_Misses",672 "MetricName": "INST_FROM_RMEM_RATE",673 "ScaleUnit": "1%"674 },675 {676 "BriefDescription": "Percentage of ICache reloads from distant memory per completed instruction",677 "MetricExpr": "PM_INST_FROM_DMEM * 100 / PM_RUN_INST_CMPL",678 "MetricGroup": "Instruction_Misses",679 "MetricName": "INST_FROM_DMEM_RATE",680 "ScaleUnit": "1%"681 },682 {683 "BriefDescription": "Average number of run cycles per completed instruction",684 "MetricExpr": "PM_RUN_CYC / PM_RUN_INST_CMPL",685 "MetricGroup": "General",686 "MetricName": "RUN_CPI"687 },688 {689 "BriefDescription": "Percentage of DERAT misses per completed instruction",690 "MetricExpr": "PM_DERAT_MISS / PM_RUN_INST_CMPL * 100",691 "MetricGroup": "Translation",692 "MetricName": "DERAT_MISS_RATE",693 "ScaleUnit": "1%"694 },695 {696 "BriefDescription": "Average number of completed instructions per run cycle",697 "MetricExpr": "PM_RUN_INST_CMPL / PM_RUN_CYC",698 "MetricGroup": "General",699 "MetricName": "RUN_IPC"700 },701 {702 "BriefDescription": "Average number of completed instructions per instruction group",703 "MetricExpr": "PM_RUN_INST_CMPL / PM_1PLUS_PPC_CMPL",704 "MetricGroup": "General",705 "MetricName": "AVERAGE_COMPLETED_INSTRUCTION_SET_SIZE"706 },707 {708 "BriefDescription": "Average number of finished instructions per completed instructions",709 "MetricExpr": "PM_INST_FIN / PM_RUN_INST_CMPL",710 "MetricGroup": "General",711 "MetricName": "INST_FIN_PER_CMPL"712 },713 {714 "BriefDescription": "Average cycles per completed instruction when the NTF instruction is completing and the finish was overlooked",715 "MetricExpr": "PM_EXEC_STALL_UNKNOWN / PM_RUN_INST_CMPL",716 "MetricGroup": "General",717 "MetricName": "EXEC_STALL_UNKOWN_CPI"718 },719 {720 "BriefDescription": "Percentage of finished branches that were taken",721 "MetricExpr": "PM_BR_TAKEN_CMPL / PM_BR_FIN * 100",722 "MetricGroup": "General",723 "MetricName": "TAKEN_BRANCHES",724 "ScaleUnit": "1%"725 },726 {727 "BriefDescription": "Percentage of completed instructions that were a demand load that did not hit in the L1, L2, or the L3",728 "MetricExpr": "PM_DATA_FROM_L3MISS / PM_RUN_INST_CMPL * 100",729 "MetricGroup": "General",730 "MetricName": "L3_LD_MISS_RATE",731 "ScaleUnit": "1%"732 },733 {734 "BriefDescription": "Average number of finished branches per completed instruction",735 "MetricExpr": "PM_BR_FIN / PM_RUN_INST_CMPL",736 "MetricGroup": "General",737 "MetricName": "BRANCHES_PER_INST"738 },739 {740 "BriefDescription": "Average number of instructions finished in the LSU per completed instruction",741 "MetricExpr": "PM_LSU_FIN / PM_RUN_INST_CMPL",742 "MetricGroup": "General",743 "MetricName": "LSU_PER_INST"744 },745 {746 "BriefDescription": "Average number of instructions finished in the VSU per completed instruction",747 "MetricExpr": "PM_VSU_FIN / PM_RUN_INST_CMPL",748 "MetricGroup": "General",749 "MetricName": "VSU_PER_INST"750 },751 {752 "BriefDescription": "Average number of TLBIE instructions finished in the LSU per completed instruction",753 "MetricExpr": "PM_TLBIE_FIN / PM_RUN_INST_CMPL",754 "MetricGroup": "General",755 "MetricName": "TLBIE_PER_INST"756 },757 {758 "BriefDescription": "Average number of STCX instructions finshed per completed instruction",759 "MetricExpr": "PM_STCX_FIN / PM_RUN_INST_CMPL",760 "MetricGroup": "General",761 "MetricName": "STCX_PER_INST"762 },763 {764 "BriefDescription": "Average number of LARX instructions finshed per completed instruction",765 "MetricExpr": "PM_LARX_FIN / PM_RUN_INST_CMPL",766 "MetricGroup": "General",767 "MetricName": "LARX_PER_INST"768 },769 {770 "BriefDescription": "Average number of PTESYNC instructions finshed per completed instruction",771 "MetricExpr": "PM_PTESYNC_FIN / PM_RUN_INST_CMPL",772 "MetricGroup": "General",773 "MetricName": "PTESYNC_PER_INST"774 },775 {776 "BriefDescription": "Average number of simple fixed-point instructions finshed in the store unit per completed instruction",777 "MetricExpr": "PM_FX_LSU_FIN / PM_RUN_INST_CMPL",778 "MetricGroup": "General",779 "MetricName": "FX_PER_INST"780 },781 {782 "BriefDescription": "Percentage of demand load misses that reloaded the L1 cache",783 "MetricExpr": "PM_LD_DEMAND_MISS_L1 / PM_LD_MISS_L1 * 100",784 "MetricGroup": "General",785 "MetricName": "DL1_MISS_RELOADS",786 "ScaleUnit": "1%"787 },788 {789 "BriefDescription": "Percentage of demand load misses that reloaded from the local L2",790 "MetricExpr": "PM_DATA_FROM_L2 * 100 / PM_LD_DEMAND_MISS_L1",791 "MetricGroup": "dL1_Reloads",792 "MetricName": "DL1_RELOAD_FROM_L2",793 "ScaleUnit": "1%"794 },795 {796 "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L2",797 "MetricExpr": "PM_DATA_FROM_L2MISS / PM_LD_DEMAND_MISS_L1 * 100",798 "MetricGroup": "dL1_Reloads",799 "MetricName": "DL1_RELOAD_FROM_L2_MISS",800 "ScaleUnit": "1%"801 },802 {803 "BriefDescription": "Percentage of demand load misses that reloaded from the local L3",804 "MetricExpr": "PM_DATA_FROM_L3 * 100 / PM_LD_DEMAND_MISS_L1",805 "MetricGroup": "dL1_Reloads",806 "MetricName": "DL1_RELOAD_FROM_L3",807 "ScaleUnit": "1%"808 },809 {810 "BriefDescription": "Percentage of demand load misses that reloaded from beyond the local L3",811 "MetricExpr": "PM_DATA_FROM_L3MISS / PM_LD_DEMAND_MISS_L1 * 100",812 "MetricGroup": "dL1_Reloads",813 "MetricName": "DL1_RELOAD_FROM_L3_MISS",814 "ScaleUnit": "1%"815 },816 {817 "BriefDescription": "Percentage of demand load misses that reloaded from the local L3 with modified data",818 "MetricExpr": "PM_DATA_FROM_L3_MEPF * 100 / PM_LD_DEMAND_MISS_L1",819 "MetricGroup": "dL1_Reloads",820 "MetricName": "DL1_RELOAD_FROM_L3_MEPF",821 "ScaleUnit": "1%"822 },823 {824 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the same regent with modified data",825 "MetricExpr": "PM_DATA_FROM_L21_REGENT_MOD * 100 / PM_LD_DEMAND_MISS_L1",826 "MetricGroup": "dL1_Reloads",827 "MetricName": "DL1_RELOAD_FROM_L21_REGENT_MOD",828 "ScaleUnit": "1%"829 },830 {831 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the same regent with shared data",832 "MetricExpr": "PM_DATA_FROM_L21_REGENT_SHR * 100 / PM_LD_DEMAND_MISS_L1",833 "MetricGroup": "dL1_Reloads",834 "MetricName": "DL1_RELOAD_FROM_L21_REGENT_SHR",835 "ScaleUnit": "1%"836 },837 {838 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the same chip in a different regent with modified data",839 "MetricExpr": "PM_DATA_FROM_L21_NON_REGENT_MOD * 100 / PM_LD_DEMAND_MISS_L1",840 "MetricGroup": "dL1_Reloads",841 "MetricName": "DL1_RELOAD_FROM_L21_NON_REGENT_MOD",842 "ScaleUnit": "1%"843 },844 {845 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on the same chip in a different regent with shared data",846 "MetricExpr": "PM_DATA_FROM_L21_NON_REGENT_SHR * 100 / PM_LD_DEMAND_MISS_L1",847 "MetricGroup": "dL1_Reloads",848 "MetricName": "DL1_RELOAD_FROM_L21_NON_REGENT_SHR",849 "ScaleUnit": "1%"850 },851 {852 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on the same regent with modified data",853 "MetricExpr": "PM_DATA_FROM_L31_REGENT_MOD * 100 / PM_LD_DEMAND_MISS_L1",854 "MetricGroup": "dL1_Reloads",855 "MetricName": "DL1_RELOAD_FROM_L31_REGENT_MOD",856 "ScaleUnit": "1%"857 },858 {859 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on the same regent with shared data",860 "MetricExpr": "PM_DATA_FROM_L31_REGENT_SHR * 100 / PM_LD_DEMAND_MISS_L1",861 "MetricGroup": "dL1_Reloads",862 "MetricName": "DL1_RELOAD_FROM_L31_REGENT_SHR",863 "ScaleUnit": "1%"864 },865 {866 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on the same chip in a different regent with modified data",867 "MetricExpr": "PM_DATA_FROM_L31_NON_REGENT_MOD * 100 / PM_LD_DEMAND_MISS_L1",868 "MetricGroup": "dL1_Reloads",869 "MetricName": "DL1_RELOAD_FROM_L31_NON_REGENT_MOD",870 "ScaleUnit": "1%"871 },872 {873 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on the same chip in a different regent with shared data",874 "MetricExpr": "PM_DATA_FROM_L31_NON_REGENT_SHR * 100 / PM_LD_DEMAND_MISS_L1",875 "MetricGroup": "dL1_Reloads",876 "MetricName": "DL1_RELOAD_FROM_L31_NON_REGENT_SHR",877 "ScaleUnit": "1%"878 },879 {880 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on a remote chip with modified data",881 "MetricExpr": "PM_DATA_FROM_RL2_MOD * 100 / PM_LD_DEMAND_MISS_L1",882 "MetricGroup": "dL1_Reloads",883 "MetricName": "DL1_RELOAD_FROM_RL2_MOD",884 "ScaleUnit": "1%"885 },886 {887 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on a remote chip with shared data",888 "MetricExpr": "PM_DATA_FROM_RL2_SHR * 100 / PM_LD_DEMAND_MISS_L1",889 "MetricGroup": "dL1_Reloads",890 "MetricName": "DL1_RELOAD_FROM_RL2_SHR",891 "ScaleUnit": "1%"892 },893 {894 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on a remote chip with modified data",895 "MetricExpr": "PM_DATA_FROM_RL3_MOD * 100 / PM_LD_DEMAND_MISS_L1",896 "MetricGroup": "dL1_Reloads",897 "MetricName": "DL1_RELOAD_FROM_RL3_MOD",898 "ScaleUnit": "1%"899 },900 {901 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on a remote chip with shared data",902 "MetricExpr": "PM_DATA_FROM_RL3_SHR * 100 / PM_LD_DEMAND_MISS_L1",903 "MetricGroup": "dL1_Reloads",904 "MetricName": "DL1_RELOAD_FROM_RL3_SHR",905 "ScaleUnit": "1%"906 },907 {908 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on a distant chip with modified data",909 "MetricExpr": "PM_DATA_FROM_DL2_MOD * 100 / PM_LD_DEMAND_MISS_L1",910 "MetricGroup": "dL1_Reloads",911 "MetricName": "DL1_RELOAD_FROM_DL2_MOD",912 "ScaleUnit": "1%"913 },914 {915 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L2 on a distant chip with shared data",916 "MetricExpr": "PM_DATA_FROM_DL2_SHR * 100 / PM_LD_DEMAND_MISS_L1",917 "MetricGroup": "dL1_Reloads",918 "MetricName": "DL1_RELOAD_FROM_DL2_SHR",919 "ScaleUnit": "1%"920 },921 {922 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on a distant chip with modified data",923 "MetricExpr": "PM_DATA_FROM_DL3_MOD * 100 / PM_LD_DEMAND_MISS_L1",924 "MetricGroup": "dL1_Reloads",925 "MetricName": "DL1_RELOAD_FROM_DL3_MOD",926 "ScaleUnit": "1%"927 },928 {929 "BriefDescription": "Percentage of demand load misses that reloaded from another core's L3 on a distant chip with shared data",930 "MetricExpr": "PM_DATA_FROM_DL3_SHR * 100 / PM_LD_DEMAND_MISS_L1",931 "MetricGroup": "dL1_Reloads",932 "MetricName": "DL1_RELOAD_FROM_DL3_SHR",933 "ScaleUnit": "1%"934 },935 {936 "BriefDescription": "Percentage of demand load misses that reloaded from the local chip's memory",937 "MetricExpr": "PM_DATA_FROM_LMEM * 100 / PM_LD_DEMAND_MISS_L1",938 "MetricGroup": "dL1_Reloads",939 "MetricName": "DL1_RELOAD_FROM_LMEM",940 "ScaleUnit": "1%"941 },942 {943 "BriefDescription": "Percentage of demand load misses that reloaded from the local chip's OpenCAPI Cache",944 "MetricExpr": "PM_DATA_FROM_L_OC_CACHE * 100 / PM_LD_DEMAND_MISS_L1",945 "MetricGroup": "dL1_Reloads",946 "MetricName": "DL1_RELOAD_FROM_L_OC_CACHE",947 "ScaleUnit": "1%"948 },949 {950 "BriefDescription": "Percentage of demand load misses that reloaded from the local chip's OpenCAPI memory",951 "MetricExpr": "PM_DATA_FROM_L_OC_MEM * 100 / PM_LD_DEMAND_MISS_L1",952 "MetricGroup": "dL1_Reloads",953 "MetricName": "DL1_RELOAD_FROM_L_OC_MEM",954 "ScaleUnit": "1%"955 },956 {957 "BriefDescription": "Percentage of demand load misses that reloaded from a remote chip's memory",958 "MetricExpr": "PM_DATA_FROM_RMEM * 100 / PM_LD_DEMAND_MISS_L1",959 "MetricGroup": "dL1_Reloads",960 "MetricName": "DL1_RELOAD_FROM_RMEM",961 "ScaleUnit": "1%"962 },963 {964 "BriefDescription": "Percentage of demand load misses that reloaded from a remote chip's OpenCAPI Cache",965 "MetricExpr": "PM_DATA_FROM_R_OC_CACHE * 100 / PM_LD_DEMAND_MISS_L1",966 "MetricGroup": "dL1_Reloads",967 "MetricName": "DL1_RELOAD_FROM_R_OC_CACHE",968 "ScaleUnit": "1%"969 },970 {971 "BriefDescription": "Percentage of demand load misses that reloaded from a remote chip's OpenCAPI memory",972 "MetricExpr": "PM_DATA_FROM_R_OC_MEM * 100 / PM_LD_DEMAND_MISS_L1",973 "MetricGroup": "dL1_Reloads",974 "MetricName": "DL1_RELOAD_FROM_R_OC_MEM",975 "ScaleUnit": "1%"976 },977 {978 "BriefDescription": "Percentage of demand load misses that reloaded from a distant chip's memory",979 "MetricExpr": "PM_DATA_FROM_DMEM * 100 / PM_LD_DEMAND_MISS_L1",980 "MetricGroup": "dL1_Reloads",981 "MetricName": "DL1_RELOAD_FROM_DMEM",982 "ScaleUnit": "1%"983 },984 {985 "BriefDescription": "Percentage of demand load misses that reloaded from a distant chip's OpenCAPI Cache",986 "MetricExpr": "PM_DATA_FROM_D_OC_CACHE * 100 / PM_LD_DEMAND_MISS_L1",987 "MetricGroup": "dL1_Reloads",988 "MetricName": "DL1_RELOAD_FROM_D_OC_CACHE",989 "ScaleUnit": "1%"990 },991 {992 "BriefDescription": "Percentage of demand load misses that reloaded from a distant chip's OpenCAPI memory",993 "MetricExpr": "PM_DATA_FROM_D_OC_MEM * 100 / PM_LD_DEMAND_MISS_L1",994 "MetricGroup": "dL1_Reloads",995 "MetricName": "DL1_RELOAD_FROM_D_OC_MEM",996 "ScaleUnit": "1%"997 },998 {999 "BriefDescription": "Percentage of cycles stalled due to the NTC instruction waiting for a load miss to resolve from a source beyond the local L2 and local L3",1000 "MetricExpr": "DMISS_L3MISS_STALL_CPI / RUN_CPI * 100",1001 "MetricGroup": "General",1002 "MetricName": "DCACHE_MISS_CPI",1003 "ScaleUnit": "1%"1004 },1005 {1006 "BriefDescription": "Percentage of DERAT misses with 2M page size per completed instruction",1007 "MetricExpr": "PM_DERAT_MISS_2M / PM_RUN_INST_CMPL * 100",1008 "MetricGroup": "Translation",1009 "MetricName": "DERAT_2M_MISS_RATE",1010 "ScaleUnit": "1%"1011 },1012 {1013 "BriefDescription": "Percentage of DERAT misses with 16M page size per completed instruction",1014 "MetricExpr": "PM_DERAT_MISS_16M / PM_RUN_INST_CMPL * 100",1015 "MetricGroup": "Translation",1016 "MetricName": "DERAT_16M_MISS_RATE",1017 "ScaleUnit": "1%"1018 },1019 {1020 "BriefDescription": "Percentage of DERAT misses with 1G page size per completed run instruction",1021 "MetricExpr": "PM_DERAT_MISS_1G * 100 / PM_RUN_INST_CMPL",1022 "MetricGroup": "Translation",1023 "MetricName": "DERAT_1G_MISS_RATE",1024 "ScaleUnit": "1%"1025 },1026 {1027 "BriefDescription": "DERAT miss ratio for 4K page size",1028 "MetricExpr": "PM_DERAT_MISS_4K / PM_DERAT_MISS",1029 "MetricGroup": "Translation",1030 "MetricName": "DERAT_4K_MISS_RATIO"1031 },1032 {1033 "BriefDescription": "DERAT miss ratio for 2M page size",1034 "MetricExpr": "PM_DERAT_MISS_2M / PM_DERAT_MISS",1035 "MetricGroup": "Translation",1036 "MetricName": "DERAT_2M_MISS_RATIO"1037 },1038 {1039 "BriefDescription": "DERAT miss ratio for 16M page size",1040 "MetricExpr": "PM_DERAT_MISS_16M / PM_DERAT_MISS",1041 "MetricGroup": "Translation",1042 "MetricName": "DERAT_16M_MISS_RATIO"1043 },1044 {1045 "BriefDescription": "DERAT miss ratio for 1G page size",1046 "MetricExpr": "PM_DERAT_MISS_1G / PM_DERAT_MISS",1047 "MetricGroup": "Translation",1048 "MetricName": "DERAT_1G_MISS_RATIO"1049 },1050 {1051 "BriefDescription": "DERAT miss ratio for 64K page size",1052 "MetricExpr": "PM_DERAT_MISS_64K / PM_DERAT_MISS",1053 "MetricGroup": "Translation",1054 "MetricName": "DERAT_64K_MISS_RATIO"1055 },1056 {1057 "BriefDescription": "Percentage of DERAT misses that resulted in TLB reloads",1058 "MetricExpr": "PM_DTLB_MISS / PM_DERAT_MISS * 100",1059 "MetricGroup": "Translation",1060 "MetricName": "DERAT_MISS_RELOAD",1061 "ScaleUnit": "1%"1062 },1063 {1064 "BriefDescription": "Percentage of ICache misses that were reloaded from beyond the local L2",1065 "MetricExpr": "PM_INST_FROM_L2MISS * 100 / PM_L1_ICACHE_MISS",1066 "MetricGroup": "Instruction_Misses",1067 "MetricName": "INST_FROM_L2_MISS",1068 "ScaleUnit": "1%"1069 },1070 {1071 "BriefDescription": "Percentage of icache misses that were reloaded from beyond the local L3",1072 "MetricExpr": "PM_INST_FROM_L3MISS / PM_L1_ICACHE_MISS * 100",1073 "MetricGroup": "Instruction_Misses",1074 "MetricName": "INST_FROM_L3_MISS",1075 "ScaleUnit": "1%"1076 },1077 {1078 "BriefDescription": "Percentage of ICache reloads from beyond the L2 per completed instruction",1079 "MetricExpr": "PM_INST_FROM_L2MISS * 100 / PM_RUN_INST_CMPL",1080 "MetricGroup": "Instruction_Misses",1081 "MetricName": "INST_FROM_L2_MISS_RATE",1082 "ScaleUnit": "1%"1083 },1084 {1085 "BriefDescription": "Percentage of icache reloads from the beyond the L3 per completed instruction",1086 "MetricExpr": "PM_INST_FROM_L3MISS / PM_RUN_INST_CMPL * 100",1087 "MetricGroup": "Instruction_Misses",1088 "MetricName": "INST_FROM_L3_MISS_RATE",1089 "ScaleUnit": "1%"1090 }1091]1092