351 lines · json
1[2 {3 "EventCode": "0x100f2",4 "EventName": "PM_1PLUS_PPC_CMPL",5 "BriefDescription": "1 or more ppc insts finished",6 "PublicDescription": "1 or more ppc insts finished (completed)"7 },8 {9 "EventCode": "0x400f2",10 "EventName": "PM_1PLUS_PPC_DISP",11 "BriefDescription": "Cycles at least one Instr Dispatched",12 "PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521"13 },14 {15 "EventCode": "0x100fa",16 "EventName": "PM_ANY_THRD_RUN_CYC",17 "BriefDescription": "One of threads in run_cycles",18 "PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)"19 },20 {21 "EventCode": "0x4000a",22 "EventName": "PM_CMPLU_STALL",23 "BriefDescription": "Completion stall",24 "PublicDescription": ""25 },26 {27 "EventCode": "0x4d018",28 "EventName": "PM_CMPLU_STALL_BRU",29 "BriefDescription": "Completion stall due to a Branch Unit",30 "PublicDescription": ""31 },32 {33 "EventCode": "0x2c012",34 "EventName": "PM_CMPLU_STALL_DCACHE_MISS",35 "BriefDescription": "Completion stall by Dcache miss",36 "PublicDescription": ""37 },38 {39 "EventCode": "0x2c018",40 "EventName": "PM_CMPLU_STALL_DMISS_L21_L31",41 "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",42 "PublicDescription": ""43 },44 {45 "EventCode": "0x2c016",46 "EventName": "PM_CMPLU_STALL_DMISS_L2L3",47 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",48 "PublicDescription": ""49 },50 {51 "EventCode": "0x4c016",52 "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",53 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",54 "PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict"55 },56 {57 "EventCode": "0x4c01a",58 "EventName": "PM_CMPLU_STALL_DMISS_L3MISS",59 "BriefDescription": "Completion stall due to cache miss resolving missed the L3",60 "PublicDescription": ""61 },62 {63 "EventCode": "0x4c018",64 "EventName": "PM_CMPLU_STALL_DMISS_LMEM",65 "BriefDescription": "Completion stall due to cache miss that resolves in local memory",66 "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory"67 },68 {69 "EventCode": "0x2c01c",70 "EventName": "PM_CMPLU_STALL_DMISS_REMOTE",71 "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",72 "PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"73 },74 {75 "EventCode": "0x4c012",76 "EventName": "PM_CMPLU_STALL_ERAT_MISS",77 "BriefDescription": "Completion stall due to LSU reject ERAT miss",78 "PublicDescription": ""79 },80 {81 "EventCode": "0x4d016",82 "EventName": "PM_CMPLU_STALL_FXLONG",83 "BriefDescription": "Completion stall due to a long latency fixed point instruction",84 "PublicDescription": ""85 },86 {87 "EventCode": "0x2d016",88 "EventName": "PM_CMPLU_STALL_FXU",89 "BriefDescription": "Completion stall due to FXU",90 "PublicDescription": ""91 },92 {93 "EventCode": "0x30036",94 "EventName": "PM_CMPLU_STALL_HWSYNC",95 "BriefDescription": "completion stall due to hwsync",96 "PublicDescription": ""97 },98 {99 "EventCode": "0x4d014",100 "EventName": "PM_CMPLU_STALL_LOAD_FINISH",101 "BriefDescription": "Completion stall due to a Load finish",102 "PublicDescription": ""103 },104 {105 "EventCode": "0x2c010",106 "EventName": "PM_CMPLU_STALL_LSU",107 "BriefDescription": "Completion stall by LSU instruction",108 "PublicDescription": ""109 },110 {111 "EventCode": "0x10036",112 "EventName": "PM_CMPLU_STALL_LWSYNC",113 "BriefDescription": "completion stall due to isync/lwsync",114 "PublicDescription": ""115 },116 {117 "EventCode": "0x30006",118 "EventName": "PM_CMPLU_STALL_OTHER_CMPL",119 "BriefDescription": "Instructions core completed while this tread was stalled",120 "PublicDescription": "Instructions core completed while this thread was stalled"121 },122 {123 "EventCode": "0x4c01c",124 "EventName": "PM_CMPLU_STALL_ST_FWD",125 "BriefDescription": "Completion stall due to store forward",126 "PublicDescription": ""127 },128 {129 "EventCode": "0x1001c",130 "EventName": "PM_CMPLU_STALL_THRD",131 "BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",132 "PublicDescription": "Completion stall due to thread conflict"133 },134 {135 "EventCode": "0x1e",136 "EventName": "PM_CYC",137 "BriefDescription": "Cycles",138 "PublicDescription": ""139 },140 {141 "EventCode": "0x10006",142 "EventName": "PM_DISP_HELD",143 "BriefDescription": "Dispatch Held",144 "PublicDescription": ""145 },146 {147 "EventCode": "0x4003c",148 "EventName": "PM_DISP_HELD_SYNC_HOLD",149 "BriefDescription": "Dispatch held due to SYNC hold",150 "PublicDescription": ""151 },152 {153 "EventCode": "0x200f8",154 "EventName": "PM_EXT_INT",155 "BriefDescription": "external interrupt",156 "PublicDescription": ""157 },158 {159 "EventCode": "0x400f8",160 "EventName": "PM_FLUSH",161 "BriefDescription": "Flush (any type)",162 "PublicDescription": ""163 },164 {165 "EventCode": "0x30012",166 "EventName": "PM_FLUSH_COMPLETION",167 "BriefDescription": "Completion Flush",168 "PublicDescription": ""169 },170 {171 "EventCode": "0x3000c",172 "EventName": "PM_FREQ_DOWN",173 "BriefDescription": "Power Management: Below Threshold B",174 "PublicDescription": "Frequency is being slewed down due to Power Management"175 },176 {177 "EventCode": "0x4000c",178 "EventName": "PM_FREQ_UP",179 "BriefDescription": "Power Management: Above Threshold A",180 "PublicDescription": "Frequency is being slewed up due to Power Management"181 },182 {183 "EventCode": "0x2000a",184 "EventName": "PM_HV_CYC",185 "BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",186 "PublicDescription": "cycles in hypervisor mode"187 },188 {189 "EventCode": "0x3405e",190 "EventName": "PM_IFETCH_THROTTLE",191 "BriefDescription": "Cycles in which Instruction fetch throttle was active",192 "PublicDescription": "Cycles instruction fecth was throttled in IFU"193 },194 {195 "EventCode": "0x10014",196 "EventName": "PM_IOPS_CMPL",197 "BriefDescription": "Internal Operations completed",198 "PublicDescription": "IOPS Completed"199 },200 {201 "EventCode": "0x3c058",202 "EventName": "PM_LARX_FIN",203 "BriefDescription": "Larx finished",204 "PublicDescription": ""205 },206 {207 "EventCode": "0x1002e",208 "EventName": "PM_LD_CMPL",209 "BriefDescription": "count of Loads completed",210 "PublicDescription": ""211 },212 {213 "EventCode": "0x10062",214 "EventName": "PM_LD_L3MISS_PEND_CYC",215 "BriefDescription": "Cycles L3 miss was pending for this thread",216 "PublicDescription": ""217 },218 {219 "EventCode": "0x30066",220 "EventName": "PM_LSU_FIN",221 "BriefDescription": "LSU Finished an instruction (up to 2 per cycle)",222 "PublicDescription": ""223 },224 {225 "EventCode": "0x2003e",226 "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",227 "BriefDescription": "LSU empty (lmq and srq empty)",228 "PublicDescription": ""229 },230 {231 "EventCode": "0x2e05c",232 "EventName": "PM_LSU_REJECT_ERAT_MISS",233 "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",234 "PublicDescription": ""235 },236 {237 "EventCode": "0x4e05c",238 "EventName": "PM_LSU_REJECT_LHS",239 "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",240 "PublicDescription": ""241 },242 {243 "EventCode": "0x1e05c",244 "EventName": "PM_LSU_REJECT_LMQ_FULL",245 "BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)",246 "PublicDescription": ""247 },248 {249 "EventCode": "0x1001a",250 "EventName": "PM_LSU_SRQ_FULL_CYC",251 "BriefDescription": "Storage Queue is full and is blocking dispatch",252 "PublicDescription": "SRQ is Full"253 },254 {255 "EventCode": "0x40014",256 "EventName": "PM_PROBE_NOP_DISP",257 "BriefDescription": "ProbeNops dispatched",258 "PublicDescription": ""259 },260 {261 "EventCode": "0x600f4",262 "EventName": "PM_RUN_CYC",263 "BriefDescription": "Run_cycles",264 "PublicDescription": ""265 },266 {267 "EventCode": "0x3006c",268 "EventName": "PM_RUN_CYC_SMT2_MODE",269 "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",270 "PublicDescription": ""271 },272 {273 "EventCode": "0x2006c",274 "EventName": "PM_RUN_CYC_SMT4_MODE",275 "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",276 "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"277 },278 {279 "EventCode": "0x1006c",280 "EventName": "PM_RUN_CYC_ST_MODE",281 "BriefDescription": "Cycles run latch is set and core is in ST mode",282 "PublicDescription": ""283 },284 {285 "EventCode": "0x500fa",286 "EventName": "PM_RUN_INST_CMPL",287 "BriefDescription": "Run_Instructions",288 "PublicDescription": ""289 },290 {291 "EventCode": "0x1e058",292 "EventName": "PM_STCX_FAIL",293 "BriefDescription": "stcx failed",294 "PublicDescription": ""295 },296 {297 "EventCode": "0x20016",298 "EventName": "PM_ST_CMPL",299 "BriefDescription": "Store completion count",300 "PublicDescription": ""301 },302 {303 "EventCode": "0x200f0",304 "EventName": "PM_ST_FIN",305 "BriefDescription": "Store Instructions Finished",306 "PublicDescription": "Store Instructions Finished (store sent to nest)"307 },308 {309 "EventCode": "0x20018",310 "EventName": "PM_ST_FWD",311 "BriefDescription": "Store forwards that finished",312 "PublicDescription": ""313 },314 {315 "EventCode": "0x10026",316 "EventName": "PM_TABLEWALK_CYC",317 "BriefDescription": "Cycles when a tablewalk (I or D) is active",318 "PublicDescription": "Tablewalk Active"319 },320 {321 "EventCode": "0x300f8",322 "EventName": "PM_TB_BIT_TRANS",323 "BriefDescription": "timebase event",324 "PublicDescription": ""325 },326 {327 "EventCode": "0x2000c",328 "EventName": "PM_THRD_ALL_RUN_CYC",329 "BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)",330 "PublicDescription": ""331 },332 {333 "EventCode": "0x30058",334 "EventName": "PM_TLBIE_FIN",335 "BriefDescription": "tlbie finished",336 "PublicDescription": ""337 },338 {339 "EventCode": "0x10060",340 "EventName": "PM_TM_TRANS_RUN_CYC",341 "BriefDescription": "run cycles in transactional state",342 "PublicDescription": ""343 },344 {345 "EventCode": "0x2e012",346 "EventName": "PM_TM_TX_PASS_RUN_CYC",347 "BriefDescription": "cycles spent in successful transactions",348 "PublicDescription": "run cycles spent in successful transactions"349 }350]351