173 lines · json
1[2 {3 "EventName": "ACCESS_MMU_STLB",4 "EventCode": "0x1",5 "BriefDescription": "access MMU STLB"6 },7 {8 "EventName": "MISS_MMU_STLB",9 "EventCode": "0x2",10 "BriefDescription": "miss MMU STLB"11 },12 {13 "EventName": "ACCESS_MMU_PTE_C",14 "EventCode": "0x3",15 "BriefDescription": "access MMU PTE-Cache"16 },17 {18 "EventName": "MISS_MMU_PTE_C",19 "EventCode": "0x4",20 "BriefDescription": "miss MMU PTE-Cache"21 },22 {23 "EventName": "ROB_FLUSH",24 "EventCode": "0x5",25 "BriefDescription": "ROB flush (all kinds of exceptions)"26 },27 {28 "EventName": "BTB_PREDICTION_MISS",29 "EventCode": "0x6",30 "BriefDescription": "BTB prediction miss"31 },32 {33 "EventName": "ITLB_MISS",34 "EventCode": "0x7",35 "BriefDescription": "ITLB miss"36 },37 {38 "EventName": "SYNC_DEL_FETCH_G",39 "EventCode": "0x8",40 "BriefDescription": "SYNC delivery a fetch-group"41 },42 {43 "EventName": "ICACHE_MISS",44 "EventCode": "0x9",45 "BriefDescription": "ICache miss"46 },47 {48 "EventName": "BPU_BR_RETIRE",49 "EventCode": "0xA",50 "BriefDescription": "condition branch instruction retire"51 },52 {53 "EventName": "BPU_BR_MISS",54 "EventCode": "0xB",55 "BriefDescription": "condition branch instruction miss"56 },57 {58 "EventName": "RET_INS_RETIRE",59 "EventCode": "0xC",60 "BriefDescription": "return instruction retire"61 },62 {63 "EventName": "RET_INS_MISS",64 "EventCode": "0xD",65 "BriefDescription": "return instruction miss"66 },67 {68 "EventName": "INDIRECT_JR_MISS",69 "EventCode": "0xE",70 "BriefDescription": "indirect JR instruction miss (inlcude without target)"71 },72 {73 "EventName": "IBUF_VAL_ID_NORDY",74 "EventCode": "0xF",75 "BriefDescription": "IBUF valid while ID not ready"76 },77 {78 "EventName": "IBUF_NOVAL_ID_RDY",79 "EventCode": "0x10",80 "BriefDescription": "IBUF not valid while ID ready"81 },82 {83 "EventName": "REN_INT_PHY_REG_NORDY",84 "EventCode": "0x11",85 "BriefDescription": "REN integer physical register file is not ready"86 },87 {88 "EventName": "REN_FP_PHY_REG_NORDY",89 "EventCode": "0x12",90 "BriefDescription": "REN floating point physical register file is not ready"91 },92 {93 "EventName": "REN_CP_NORDY",94 "EventCode": "0x13",95 "BriefDescription": "REN checkpoint is not ready"96 },97 {98 "EventName": "DEC_VAL_ROB_NORDY",99 "EventCode": "0x14",100 "BriefDescription": "DEC is valid and ROB is not ready"101 },102 {103 "EventName": "OOD_FLUSH_LS_DEP",104 "EventCode": "0x15",105 "BriefDescription": "out of order flush due to load/store dependency"106 },107 {108 "EventName": "BRU_RET_IJR_INS",109 "EventCode": "0x16",110 "BriefDescription": "BRU retire an IJR instruction"111 },112 {113 "EventName": "ACCESS_DTLB",114 "EventCode": "0x17",115 "BriefDescription": "access DTLB"116 },117 {118 "EventName": "MISS_DTLB",119 "EventCode": "0x18",120 "BriefDescription": "miss DTLB"121 },122 {123 "EventName": "LOAD_INS_DCACHE",124 "EventCode": "0x19",125 "BriefDescription": "load instruction access DCache"126 },127 {128 "EventName": "LOAD_INS_MISS_DCACHE",129 "EventCode": "0x1A",130 "BriefDescription": "load instruction miss DCache"131 },132 {133 "EventName": "STORE_INS_DCACHE",134 "EventCode": "0x1B",135 "BriefDescription": "store/amo instruction access DCache"136 },137 {138 "EventName": "STORE_INS_MISS_DCACHE",139 "EventCode": "0x1C",140 "BriefDescription": "store/amo instruction miss DCache"141 },142 {143 "EventName": "LOAD_SCACHE",144 "EventCode": "0x1D",145 "BriefDescription": "load access SCache"146 },147 {148 "EventName": "STORE_SCACHE",149 "EventCode": "0x1E",150 "BriefDescription": "store access SCache"151 },152 {153 "EventName": "LOAD_MISS_SCACHE",154 "EventCode": "0x1F",155 "BriefDescription": "load miss SCache"156 },157 {158 "EventName": "STORE_MISS_SCACHE",159 "EventCode": "0x20",160 "BriefDescription": "store miss SCache"161 },162 {163 "EventName": "L2C_PF_REQ",164 "EventCode": "0x21",165 "BriefDescription": "L2C data-prefetcher request"166 },167 {168 "EventName": "L2C_PF_HIT",169 "EventCode": "0x22",170 "BriefDescription": "L2C data-prefetcher hit"171 }172]173