73 lines · json
1[2 {3 "BriefDescription": "Transaction count",4 "MetricName": "transaction",5 "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"6 },7 {8 "BriefDescription": "Cycles per Instruction",9 "MetricName": "cpi",10 "MetricExpr": "CPU_CYCLES / INSTRUCTIONS"11 },12 {13 "BriefDescription": "Problem State Instruction Ratio",14 "MetricName": "prbstate",15 "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100"16 },17 {18 "BriefDescription": "Level One Miss per 100 Instructions",19 "MetricName": "l1mp",20 "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"21 },22 {23 "BriefDescription": "Percentage sourced from Level 2 cache",24 "MetricName": "l2p",25 "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"26 },27 {28 "BriefDescription": "Percentage sourced from Level 3 on same chip cache",29 "MetricName": "l3p",30 "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"31 },32 {33 "BriefDescription": "Percentage sourced from Level 4 Local cache on same book",34 "MetricName": "l4lp",35 "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"36 },37 {38 "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",39 "MetricName": "l4rp",40 "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"41 },42 {43 "BriefDescription": "Percentage sourced from memory",44 "MetricName": "memp",45 "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"46 },47 {48 "BriefDescription": "Cycles per Instructions from Finite cache/memory",49 "MetricName": "finite_cpi",50 "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"51 },52 {53 "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",54 "MetricName": "est_cpi",55 "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"56 },57 {58 "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",59 "MetricName": "scpl1m",60 "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"61 },62 {63 "BriefDescription": "Estimated TLB CPU percentage of Total CPU",64 "MetricName": "tlb_percent",65 "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"66 },67 {68 "BriefDescription": "Estimated Cycles per TLB Miss",69 "MetricName": "tlb_miss",70 "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"71 }72]73