196 lines · json
1[2 {3 "BriefDescription": "ARITH.FPDIV_ACTIVE",4 "Counter": "0,1,2,3,4,5,6,7",5 "CounterMask": "1",6 "EventCode": "0xb0",7 "EventName": "ARITH.FPDIV_ACTIVE",8 "SampleAfterValue": "1000003",9 "UMask": "0x1",10 "Unit": "cpu_core"11 },12 {13 "BriefDescription": "Counts all microcode FP assists.",14 "Counter": "0,1,2,3,4,5,6,7",15 "EventCode": "0xc1",16 "EventName": "ASSISTS.FP",17 "PublicDescription": "Counts all microcode Floating Point assists.",18 "SampleAfterValue": "100003",19 "UMask": "0x2",20 "Unit": "cpu_core"21 },22 {23 "BriefDescription": "ASSISTS.SSE_AVX_MIX",24 "Counter": "0,1,2,3,4,5,6,7",25 "EventCode": "0xc1",26 "EventName": "ASSISTS.SSE_AVX_MIX",27 "SampleAfterValue": "1000003",28 "UMask": "0x10",29 "Unit": "cpu_core"30 },31 {32 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",33 "Counter": "0,1,2,3,4,5,6,7",34 "EventCode": "0xb3",35 "EventName": "FP_ARITH_DISPATCHED.PORT_0",36 "SampleAfterValue": "2000003",37 "UMask": "0x1",38 "Unit": "cpu_core"39 },40 {41 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",42 "Counter": "0,1,2,3,4,5,6,7",43 "EventCode": "0xb3",44 "EventName": "FP_ARITH_DISPATCHED.PORT_1",45 "SampleAfterValue": "2000003",46 "UMask": "0x2",47 "Unit": "cpu_core"48 },49 {50 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",51 "Counter": "0,1,2,3,4,5,6,7",52 "EventCode": "0xb3",53 "EventName": "FP_ARITH_DISPATCHED.PORT_5",54 "SampleAfterValue": "2000003",55 "UMask": "0x4",56 "Unit": "cpu_core"57 },58 {59 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",60 "Counter": "0,1,2,3,4,5,6,7",61 "EventCode": "0xb3",62 "EventName": "FP_ARITH_DISPATCHED.V0",63 "SampleAfterValue": "2000003",64 "UMask": "0x1",65 "Unit": "cpu_core"66 },67 {68 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",69 "Counter": "0,1,2,3,4,5,6,7",70 "EventCode": "0xb3",71 "EventName": "FP_ARITH_DISPATCHED.V1",72 "SampleAfterValue": "2000003",73 "UMask": "0x2",74 "Unit": "cpu_core"75 },76 {77 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",78 "Counter": "0,1,2,3,4,5,6,7",79 "EventCode": "0xb3",80 "EventName": "FP_ARITH_DISPATCHED.V2",81 "SampleAfterValue": "2000003",82 "UMask": "0x4",83 "Unit": "cpu_core"84 },85 {86 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",87 "Counter": "0,1,2,3,4,5,6,7",88 "EventCode": "0xc7",89 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",90 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",91 "SampleAfterValue": "100003",92 "UMask": "0x4",93 "Unit": "cpu_core"94 },95 {96 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",97 "Counter": "0,1,2,3,4,5,6,7",98 "EventCode": "0xc7",99 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",100 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",101 "SampleAfterValue": "100003",102 "UMask": "0x8",103 "Unit": "cpu_core"104 },105 {106 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",107 "Counter": "0,1,2,3,4,5,6,7",108 "EventCode": "0xc7",109 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",110 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",111 "SampleAfterValue": "100003",112 "UMask": "0x10",113 "Unit": "cpu_core"114 },115 {116 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",117 "Counter": "0,1,2,3,4,5,6,7",118 "EventCode": "0xc7",119 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",120 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",121 "SampleAfterValue": "100003",122 "UMask": "0x20",123 "Unit": "cpu_core"124 },125 {126 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",127 "Counter": "0,1,2,3,4,5,6,7",128 "EventCode": "0xc7",129 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",130 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",131 "SampleAfterValue": "100003",132 "UMask": "0x18",133 "Unit": "cpu_core"134 },135 {136 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",137 "Counter": "0,1,2,3,4,5,6,7",138 "EventCode": "0xc7",139 "EventName": "FP_ARITH_INST_RETIRED.SCALAR",140 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",141 "SampleAfterValue": "1000003",142 "UMask": "0x3",143 "Unit": "cpu_core"144 },145 {146 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",147 "Counter": "0,1,2,3,4,5,6,7",148 "EventCode": "0xc7",149 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",150 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",151 "SampleAfterValue": "100003",152 "UMask": "0x1",153 "Unit": "cpu_core"154 },155 {156 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",157 "Counter": "0,1,2,3,4,5,6,7",158 "EventCode": "0xc7",159 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",160 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",161 "SampleAfterValue": "100003",162 "UMask": "0x2",163 "Unit": "cpu_core"164 },165 {166 "BriefDescription": "Number of any Vector retired FP arithmetic instructions",167 "Counter": "0,1,2,3,4,5,6,7",168 "EventCode": "0xc7",169 "EventName": "FP_ARITH_INST_RETIRED.VECTOR",170 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",171 "SampleAfterValue": "1000003",172 "UMask": "0xfc",173 "Unit": "cpu_core"174 },175 {176 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",177 "Counter": "0,1,2,3,4,5",178 "EventCode": "0xc3",179 "EventName": "MACHINE_CLEARS.FP_ASSIST",180 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",181 "SampleAfterValue": "20003",182 "UMask": "0x4",183 "Unit": "cpu_atom"184 },185 {186 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",187 "Counter": "0,1,2,3,4,5",188 "EventCode": "0xc2",189 "EventName": "UOPS_RETIRED.FPDIV",190 "PEBS": "1",191 "SampleAfterValue": "2000003",192 "UMask": "0x8",193 "Unit": "cpu_atom"194 }195]196