185 lines · json
1[2 {3 "EventName": "ls_locks.bus_lock",4 "EventCode": "0x25",5 "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",6 "UMask": "0x01"7 },8 {9 "EventName": "ls_dispatch.ld_st_dispatch",10 "EventCode": "0x29",11 "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",12 "UMask": "0x04"13 },14 {15 "EventName": "ls_dispatch.store_dispatch",16 "EventCode": "0x29",17 "BriefDescription": "Counts the number of stores dispatched to the LS unit. Unit Masks ADDed.",18 "UMask": "0x02"19 },20 {21 "EventName": "ls_dispatch.ld_dispatch",22 "EventCode": "0x29",23 "BriefDescription": "Counts the number of loads dispatched to the LS unit. Unit Masks ADDed.",24 "UMask": "0x01"25 },26 {27 "EventName": "ls_stlf",28 "EventCode": "0x35",29 "BriefDescription": "Number of STLF hits."30 },31 {32 "EventName": "ls_dc_accesses",33 "EventCode": "0x40",34 "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."35 },36 {37 "EventName": "ls_mab_alloc.dc_prefetcher",38 "EventCode": "0x41",39 "BriefDescription": "LS MAB allocates by type - DC prefetcher.",40 "UMask": "0x08"41 },42 {43 "EventName": "ls_mab_alloc.stores",44 "EventCode": "0x41",45 "BriefDescription": "LS MAB allocates by type - stores.",46 "UMask": "0x02"47 },48 {49 "EventName": "ls_mab_alloc.loads",50 "EventCode": "0x41",51 "BriefDescription": "LS MAB allocates by type - loads.",52 "UMask": "0x01"53 },54 {55 "EventName": "ls_l1_d_tlb_miss.all",56 "EventCode": "0x45",57 "BriefDescription": "L1 DTLB Miss or Reload off all sizes.",58 "UMask": "0xff"59 },60 {61 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",62 "EventCode": "0x45",63 "BriefDescription": "L1 DTLB Miss of a page of 1G size.",64 "UMask": "0x80"65 },66 {67 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",68 "EventCode": "0x45",69 "BriefDescription": "L1 DTLB Miss of a page of 2M size.",70 "UMask": "0x40"71 },72 {73 "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss",74 "EventCode": "0x45",75 "BriefDescription": "L1 DTLB Miss of a page of 32K size.",76 "UMask": "0x20"77 },78 {79 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",80 "EventCode": "0x45",81 "BriefDescription": "L1 DTLB Miss of a page of 4K size.",82 "UMask": "0x10"83 },84 {85 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",86 "EventCode": "0x45",87 "BriefDescription": "L1 DTLB Reload of a page of 1G size.",88 "UMask": "0x08"89 },90 {91 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",92 "EventCode": "0x45",93 "BriefDescription": "L1 DTLB Reload of a page of 2M size.",94 "UMask": "0x04"95 },96 {97 "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit",98 "EventCode": "0x45",99 "BriefDescription": "L1 DTLB Reload of a page of 32K size.",100 "UMask": "0x02"101 },102 {103 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",104 "EventCode": "0x45",105 "BriefDescription": "L1 DTLB Reload of a page of 4K size.",106 "UMask": "0x01"107 },108 {109 "EventName": "ls_tablewalker.iside",110 "EventCode": "0x46",111 "BriefDescription": "Total Page Table Walks on I-side.",112 "UMask": "0x0c"113 },114 {115 "EventName": "ls_tablewalker.ic_type1",116 "EventCode": "0x46",117 "BriefDescription": "Total Page Table Walks IC Type 1.",118 "UMask": "0x08"119 },120 {121 "EventName": "ls_tablewalker.ic_type0",122 "EventCode": "0x46",123 "BriefDescription": "Total Page Table Walks IC Type 0.",124 "UMask": "0x04"125 },126 {127 "EventName": "ls_tablewalker.dside",128 "EventCode": "0x46",129 "BriefDescription": "Total Page Table Walks on D-side.",130 "UMask": "0x03"131 },132 {133 "EventName": "ls_tablewalker.dc_type1",134 "EventCode": "0x46",135 "BriefDescription": "Total Page Table Walks DC Type 1.",136 "UMask": "0x02"137 },138 {139 "EventName": "ls_tablewalker.dc_type0",140 "EventCode": "0x46",141 "BriefDescription": "Total Page Table Walks DC Type 0.",142 "UMask": "0x01"143 },144 {145 "EventName": "ls_misal_accesses",146 "EventCode": "0x47",147 "BriefDescription": "Misaligned loads."148 },149 {150 "EventName": "ls_pref_instr_disp.prefetch_nta",151 "EventCode": "0x4b",152 "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",153 "UMask": "0x04"154 },155 {156 "EventName": "ls_pref_instr_disp.store_prefetch_w",157 "EventCode": "0x4b",158 "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",159 "UMask": "0x02"160 },161 {162 "EventName": "ls_pref_instr_disp.load_prefetch_w",163 "EventCode": "0x4b",164 "BriefDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",165 "UMask": "0x01"166 },167 {168 "EventName": "ls_inef_sw_pref.mab_mch_cnt",169 "EventCode": "0x52",170 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",171 "UMask": "0x02"172 },173 {174 "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",175 "EventCode": "0x52",176 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",177 "UMask": "0x01"178 },179 {180 "EventName": "ls_not_halted_cyc",181 "EventCode": "0x76",182 "BriefDescription": "Cycles not in Halt."183 }184]185