41 lines · json
1[2 {3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0",4 "Counter": "0,1,2,3",5 "EventCode": "0x5C",6 "EventName": "CPL_CYCLES.RING0",7 "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",8 "SampleAfterValue": "2000003",9 "UMask": "0x1"10 },11 {12 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",13 "Counter": "0,1,2,3",14 "CounterMask": "1",15 "EdgeDetect": "1",16 "EventCode": "0x5C",17 "EventName": "CPL_CYCLES.RING0_TRANS",18 "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",19 "SampleAfterValue": "100007",20 "UMask": "0x1"21 },22 {23 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",24 "Counter": "0,1,2,3",25 "EventCode": "0x5C",26 "EventName": "CPL_CYCLES.RING123",27 "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",28 "SampleAfterValue": "2000003",29 "UMask": "0x2"30 },31 {32 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",33 "Counter": "0,1,2,3",34 "EventCode": "0x63",35 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",36 "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",37 "SampleAfterValue": "2000003",38 "UMask": "0x1"39 }40]41