561 lines · json
1[2 {3 "BriefDescription": "Counts the number of lfclk ticks",4 "Counter": "0,1,2,3,4,5,6,7",5 "EventCode": "0x01",6 "EventName": "UNC_CXLCM_CLOCKTICKS",7 "PerPkg": "1",8 "UMask": "0x2",9 "Unit": "CXLCM"10 },11 {12 "BriefDescription": "Number of Allocation to Mem Rxx AGF 0",13 "Counter": "4,5,6,7",14 "EventCode": "0x43",15 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA",16 "Experimental": "1",17 "PerPkg": "1",18 "UMask": "0x8",19 "Unit": "CXLCM"20 },21 {22 "BriefDescription": "Number of Allocation to Cache Req AGF0",23 "Counter": "4,5,6,7",24 "EventCode": "0x43",25 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0",26 "Experimental": "1",27 "PerPkg": "1",28 "UMask": "0x1",29 "Unit": "CXLCM"30 },31 {32 "BriefDescription": "Number of Allocation to Cache Rsp AGF",33 "Counter": "4,5,6,7",34 "EventCode": "0x43",35 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1",36 "Experimental": "1",37 "PerPkg": "1",38 "UMask": "0x2",39 "Unit": "CXLCM"40 },41 {42 "BriefDescription": "Number of Allocation to Cache Data AGF",43 "Counter": "4,5,6,7",44 "EventCode": "0x43",45 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0",46 "Experimental": "1",47 "PerPkg": "1",48 "UMask": "0x4",49 "Unit": "CXLCM"50 },51 {52 "BriefDescription": "Number of Allocation to Cache Rsp AGF",53 "Counter": "4,5,6,7",54 "EventCode": "0x43",55 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1",56 "Experimental": "1",57 "PerPkg": "1",58 "UMask": "0x40",59 "Unit": "CXLCM"60 },61 {62 "BriefDescription": "Number of Allocation to Cache Req AGF 1",63 "Counter": "4,5,6,7",64 "EventCode": "0x43",65 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA",66 "Experimental": "1",67 "PerPkg": "1",68 "UMask": "0x20",69 "Unit": "CXLCM"70 },71 {72 "BriefDescription": "Number of Allocation to Mem Data AGF",73 "Counter": "4,5,6,7",74 "EventCode": "0x43",75 "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ",76 "Experimental": "1",77 "PerPkg": "1",78 "UMask": "0x10",79 "Unit": "CXLCM"80 },81 {82 "BriefDescription": "Count the number of Flits with AK set",83 "Counter": "4,5,6,7",84 "EventCode": "0x4b",85 "EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR",86 "Experimental": "1",87 "PerPkg": "1",88 "UMask": "0x10",89 "Unit": "CXLCM"90 },91 {92 "BriefDescription": "Count the number of Flits with BE set",93 "Counter": "4,5,6,7",94 "EventCode": "0x4b",95 "EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR",96 "Experimental": "1",97 "PerPkg": "1",98 "UMask": "0x20",99 "Unit": "CXLCM"100 },101 {102 "BriefDescription": "Count the number of control flits received",103 "Counter": "4,5,6,7",104 "EventCode": "0x4b",105 "EventName": "UNC_CXLCM_RxC_FLITS.CTRL",106 "Experimental": "1",107 "PerPkg": "1",108 "UMask": "0x4",109 "Unit": "CXLCM"110 },111 {112 "BriefDescription": "Count the number of Headerless flits received",113 "Counter": "4,5,6,7",114 "EventCode": "0x4b",115 "EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR",116 "Experimental": "1",117 "PerPkg": "1",118 "UMask": "0x8",119 "Unit": "CXLCM"120 },121 {122 "BriefDescription": "Count the number of protocol flits received",123 "Counter": "4,5,6,7",124 "EventCode": "0x4b",125 "EventName": "UNC_CXLCM_RxC_FLITS.PROT",126 "Experimental": "1",127 "PerPkg": "1",128 "UMask": "0x2",129 "Unit": "CXLCM"130 },131 {132 "BriefDescription": "Count the number of Flits with SZ set",133 "Counter": "4,5,6,7",134 "EventCode": "0x4b",135 "EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR",136 "Experimental": "1",137 "PerPkg": "1",138 "UMask": "0x40",139 "Unit": "CXLCM"140 },141 {142 "BriefDescription": "Count the number of flits received",143 "Counter": "4,5,6,7",144 "EventCode": "0x4b",145 "EventName": "UNC_CXLCM_RxC_FLITS.VALID",146 "Experimental": "1",147 "PerPkg": "1",148 "UMask": "0x1",149 "Unit": "CXLCM"150 },151 {152 "BriefDescription": "Count the number of valid messages in the flit",153 "Counter": "4,5,6,7",154 "EventCode": "0x4b",155 "EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG",156 "Experimental": "1",157 "PerPkg": "1",158 "UMask": "0x80",159 "Unit": "CXLCM"160 },161 {162 "BriefDescription": "Count the number of CRC errors detected",163 "Counter": "4,5,6,7",164 "EventCode": "0x40",165 "EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS",166 "Experimental": "1",167 "PerPkg": "1",168 "UMask": "0x8",169 "Unit": "CXLCM"170 },171 {172 "BriefDescription": "Count the number of Init flits sent",173 "Counter": "4,5,6,7",174 "EventCode": "0x40",175 "EventName": "UNC_CXLCM_RxC_MISC.INIT",176 "Experimental": "1",177 "PerPkg": "1",178 "UMask": "0x4",179 "Unit": "CXLCM"180 },181 {182 "BriefDescription": "Count the number of LLCRD flits sent",183 "Counter": "4,5,6,7",184 "EventCode": "0x40",185 "EventName": "UNC_CXLCM_RxC_MISC.LLCRD",186 "Experimental": "1",187 "PerPkg": "1",188 "UMask": "0x1",189 "Unit": "CXLCM"190 },191 {192 "BriefDescription": "Count the number of Retry flits sent",193 "Counter": "4,5,6,7",194 "EventCode": "0x40",195 "EventName": "UNC_CXLCM_RxC_MISC.RETRY",196 "Experimental": "1",197 "PerPkg": "1",198 "UMask": "0x2",199 "Unit": "CXLCM"200 },201 {202 "BriefDescription": "Number of cycles the Packing Buffer is Full",203 "Counter": "4,5,6,7",204 "EventCode": "0x52",205 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA",206 "Experimental": "1",207 "PerPkg": "1",208 "UMask": "0x4",209 "Unit": "CXLCM"210 },211 {212 "BriefDescription": "Number of cycles the Packing Buffer is Full",213 "Counter": "4,5,6,7",214 "EventCode": "0x52",215 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ",216 "Experimental": "1",217 "PerPkg": "1",218 "UMask": "0x1",219 "Unit": "CXLCM"220 },221 {222 "BriefDescription": "Number of cycles the Packing Buffer is Full",223 "Counter": "4,5,6,7",224 "EventCode": "0x52",225 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP",226 "Experimental": "1",227 "PerPkg": "1",228 "UMask": "0x2",229 "Unit": "CXLCM"230 },231 {232 "BriefDescription": "Number of cycles the Packing Buffer is Full",233 "Counter": "4,5,6,7",234 "EventCode": "0x52",235 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA",236 "Experimental": "1",237 "PerPkg": "1",238 "UMask": "0x10",239 "Unit": "CXLCM"240 },241 {242 "BriefDescription": "Number of cycles the Packing Buffer is Full",243 "Counter": "4,5,6,7",244 "EventCode": "0x52",245 "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ",246 "Experimental": "1",247 "PerPkg": "1",248 "UMask": "0x8",249 "Unit": "CXLCM"250 },251 {252 "BriefDescription": "Number of Allocation to Cache Data Packing buffer",253 "Counter": "4,5,6,7",254 "EventCode": "0x41",255 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA",256 "Experimental": "1",257 "PerPkg": "1",258 "UMask": "0x4",259 "Unit": "CXLCM"260 },261 {262 "BriefDescription": "Number of Allocation to Cache Req Packing buffer",263 "Counter": "4,5,6,7",264 "EventCode": "0x41",265 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ",266 "Experimental": "1",267 "PerPkg": "1",268 "UMask": "0x1",269 "Unit": "CXLCM"270 },271 {272 "BriefDescription": "Number of Allocation to Cache Rsp Packing buffer",273 "Counter": "4,5,6,7",274 "EventCode": "0x41",275 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP",276 "Experimental": "1",277 "PerPkg": "1",278 "UMask": "0x2",279 "Unit": "CXLCM"280 },281 {282 "BriefDescription": "Number of Allocation to Mem Data Packing buffer",283 "Counter": "4,5,6,7",284 "EventCode": "0x41",285 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",286 "Experimental": "1",287 "PerPkg": "1",288 "UMask": "0x10",289 "Unit": "CXLCM"290 },291 {292 "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",293 "Counter": "4,5,6,7",294 "EventCode": "0x41",295 "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ",296 "Experimental": "1",297 "PerPkg": "1",298 "UMask": "0x8",299 "Unit": "CXLCM"300 },301 {302 "BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer",303 "Counter": "4,5,6,7",304 "EventCode": "0x42",305 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA",306 "Experimental": "1",307 "PerPkg": "1",308 "UMask": "0x4",309 "Unit": "CXLCM"310 },311 {312 "BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer",313 "Counter": "4,5,6,7",314 "EventCode": "0x42",315 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ",316 "Experimental": "1",317 "PerPkg": "1",318 "UMask": "0x1",319 "Unit": "CXLCM"320 },321 {322 "BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer",323 "Counter": "4,5,6,7",324 "EventCode": "0x42",325 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP",326 "Experimental": "1",327 "PerPkg": "1",328 "UMask": "0x2",329 "Unit": "CXLCM"330 },331 {332 "BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer",333 "Counter": "4,5,6,7",334 "EventCode": "0x42",335 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA",336 "Experimental": "1",337 "PerPkg": "1",338 "UMask": "0x10",339 "Unit": "CXLCM"340 },341 {342 "BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer",343 "Counter": "4,5,6,7",344 "EventCode": "0x42",345 "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ",346 "Experimental": "1",347 "PerPkg": "1",348 "UMask": "0x8",349 "Unit": "CXLCM"350 },351 {352 "BriefDescription": "Count the number of Flits with AK set",353 "Counter": "0,1,2,3",354 "EventCode": "0x05",355 "EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR",356 "Experimental": "1",357 "PerPkg": "1",358 "UMask": "0x10",359 "Unit": "CXLCM"360 },361 {362 "BriefDescription": "Count the number of Flits with BE set",363 "Counter": "0,1,2,3",364 "EventCode": "0x05",365 "EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR",366 "Experimental": "1",367 "PerPkg": "1",368 "UMask": "0x20",369 "Unit": "CXLCM"370 },371 {372 "BriefDescription": "Count the number of control flits packed",373 "Counter": "0,1,2,3",374 "EventCode": "0x05",375 "EventName": "UNC_CXLCM_TxC_FLITS.CTRL",376 "Experimental": "1",377 "PerPkg": "1",378 "UMask": "0x4",379 "Unit": "CXLCM"380 },381 {382 "BriefDescription": "Count the number of Headerless flits packed",383 "Counter": "0,1,2,3",384 "EventCode": "0x05",385 "EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR",386 "Experimental": "1",387 "PerPkg": "1",388 "UMask": "0x8",389 "Unit": "CXLCM"390 },391 {392 "BriefDescription": "Count the number of protocol flits packed",393 "Counter": "0,1,2,3",394 "EventCode": "0x05",395 "EventName": "UNC_CXLCM_TxC_FLITS.PROT",396 "Experimental": "1",397 "PerPkg": "1",398 "UMask": "0x2",399 "Unit": "CXLCM"400 },401 {402 "BriefDescription": "Count the number of Flits with SZ set",403 "Counter": "0,1,2,3",404 "EventCode": "0x05",405 "EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR",406 "Experimental": "1",407 "PerPkg": "1",408 "UMask": "0x40",409 "Unit": "CXLCM"410 },411 {412 "BriefDescription": "Count the number of flits packed",413 "Counter": "0,1,2,3",414 "EventCode": "0x05",415 "EventName": "UNC_CXLCM_TxC_FLITS.VALID",416 "Experimental": "1",417 "PerPkg": "1",418 "UMask": "0x1",419 "Unit": "CXLCM"420 },421 {422 "BriefDescription": "Number of Allocation to Cache Data Packing buffer",423 "Counter": "0,1,2,3",424 "EventCode": "0x02",425 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA",426 "Experimental": "1",427 "PerPkg": "1",428 "UMask": "0x4",429 "Unit": "CXLCM"430 },431 {432 "BriefDescription": "Number of Allocation to Cache Req Packing buffer",433 "Counter": "0,1,2,3",434 "EventCode": "0x02",435 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0",436 "Experimental": "1",437 "PerPkg": "1",438 "UMask": "0x1",439 "Unit": "CXLCM"440 },441 {442 "BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer",443 "Counter": "0,1,2,3",444 "EventCode": "0x02",445 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1",446 "Experimental": "1",447 "PerPkg": "1",448 "UMask": "0x40",449 "Unit": "CXLCM"450 },451 {452 "BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer",453 "Counter": "0,1,2,3",454 "EventCode": "0x02",455 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0",456 "Experimental": "1",457 "PerPkg": "1",458 "UMask": "0x2",459 "Unit": "CXLCM"460 },461 {462 "BriefDescription": "Number of Allocation to Cache Req Packing buffer",463 "Counter": "0,1,2,3",464 "EventCode": "0x02",465 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1",466 "Experimental": "1",467 "PerPkg": "1",468 "UMask": "0x20",469 "Unit": "CXLCM"470 },471 {472 "BriefDescription": "Number of Allocation to Mem Data Packing buffer",473 "Counter": "0,1,2,3",474 "EventCode": "0x02",475 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA",476 "Experimental": "1",477 "PerPkg": "1",478 "UMask": "0x10",479 "Unit": "CXLCM"480 },481 {482 "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer",483 "Counter": "0,1,2,3",484 "EventCode": "0x02",485 "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ",486 "Experimental": "1",487 "PerPkg": "1",488 "UMask": "0x8",489 "Unit": "CXLCM"490 },491 {492 "BriefDescription": "Counts the number of uclk ticks",493 "Counter": "0,1,2,3",494 "EventCode": "0x01",495 "EventName": "UNC_CXLDP_CLOCKTICKS",496 "PerPkg": "1",497 "UMask": "0x1",498 "Unit": "CXLDP"499 },500 {501 "BriefDescription": "Number of Allocation to M2S Data AGF",502 "Counter": "0,1,2,3",503 "EventCode": "0x02",504 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",505 "Experimental": "1",506 "PerPkg": "1",507 "UMask": "0x20",508 "Unit": "CXLDP"509 },510 {511 "BriefDescription": "Number of Allocation to M2S Req AGF",512 "Counter": "0,1,2,3",513 "EventCode": "0x02",514 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ",515 "Experimental": "1",516 "PerPkg": "1",517 "UMask": "0x10",518 "Unit": "CXLDP"519 },520 {521 "BriefDescription": "Number of Allocation to U2C Data AGF",522 "Counter": "0,1,2,3",523 "EventCode": "0x02",524 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA",525 "Experimental": "1",526 "PerPkg": "1",527 "UMask": "0x8",528 "Unit": "CXLDP"529 },530 {531 "BriefDescription": "Number of Allocation to U2C Req AGF",532 "Counter": "0,1,2,3",533 "EventCode": "0x02",534 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ",535 "Experimental": "1",536 "PerPkg": "1",537 "UMask": "0x1",538 "Unit": "CXLDP"539 },540 {541 "BriefDescription": "Number of Allocation to U2C Rsp AGF 0",542 "Counter": "0,1,2,3",543 "EventCode": "0x02",544 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0",545 "Experimental": "1",546 "PerPkg": "1",547 "UMask": "0x2",548 "Unit": "CXLDP"549 },550 {551 "BriefDescription": "Number of Allocation to U2C Rsp AGF 1",552 "Counter": "0,1,2,3",553 "EventCode": "0x02",554 "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1",555 "Experimental": "1",556 "PerPkg": "1",557 "UMask": "0x4",558 "Unit": "CXLDP"559 }560]561