1369 lines · json
1[2 {3 "BriefDescription": "IIO Clockticks",4 "Counter": "0,1,2,3",5 "EventCode": "0x01",6 "EventName": "UNC_IIO_CLOCKTICKS",7 "PerPkg": "1",8 "PortMask": "0x000",9 "Unit": "IIO"10 },11 {12 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",13 "Counter": "0,1,2,3",14 "EventCode": "0xC2",15 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",16 "Experimental": "1",17 "FCMask": "0x07",18 "PerPkg": "1",19 "PortMask": "0x0FF",20 "UMask": "0x70ff004",21 "Unit": "IIO"22 },23 {24 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",25 "Counter": "0,1,2,3",26 "EventCode": "0xC2",27 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",28 "Experimental": "1",29 "FCMask": "0x07",30 "PerPkg": "1",31 "PortMask": "0x001",32 "UMask": "0x7001004",33 "Unit": "IIO"34 },35 {36 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",37 "Counter": "0,1,2,3",38 "EventCode": "0xC2",39 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",40 "Experimental": "1",41 "FCMask": "0x07",42 "PerPkg": "1",43 "PortMask": "0x002",44 "UMask": "0x7002004",45 "Unit": "IIO"46 },47 {48 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",49 "Counter": "0,1,2,3",50 "EventCode": "0xC2",51 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",52 "Experimental": "1",53 "FCMask": "0x07",54 "PerPkg": "1",55 "PortMask": "0x004",56 "UMask": "0x7004004",57 "Unit": "IIO"58 },59 {60 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",61 "Counter": "0,1,2,3",62 "EventCode": "0xC2",63 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",64 "Experimental": "1",65 "FCMask": "0x07",66 "PerPkg": "1",67 "PortMask": "0x008",68 "UMask": "0x7008004",69 "Unit": "IIO"70 },71 {72 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",73 "Counter": "0,1,2,3",74 "EventCode": "0xC2",75 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",76 "Experimental": "1",77 "FCMask": "0x07",78 "PerPkg": "1",79 "PortMask": "0x010",80 "UMask": "0x7010004",81 "Unit": "IIO"82 },83 {84 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",85 "Counter": "0,1,2,3",86 "EventCode": "0xC2",87 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",88 "Experimental": "1",89 "FCMask": "0x07",90 "PerPkg": "1",91 "PortMask": "0x020",92 "UMask": "0x7020004",93 "Unit": "IIO"94 },95 {96 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",97 "Counter": "0,1,2,3",98 "EventCode": "0xC2",99 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",100 "Experimental": "1",101 "FCMask": "0x07",102 "PerPkg": "1",103 "PortMask": "0x040",104 "UMask": "0x7040004",105 "Unit": "IIO"106 },107 {108 "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",109 "Counter": "0,1,2,3",110 "EventCode": "0xC2",111 "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",112 "Experimental": "1",113 "FCMask": "0x07",114 "PerPkg": "1",115 "PortMask": "0x080",116 "UMask": "0x7080004",117 "Unit": "IIO"118 },119 {120 "BriefDescription": "Count of allocations in the completion buffer",121 "Counter": "2,3",122 "EventCode": "0xD5",123 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",124 "Experimental": "1",125 "FCMask": "0x07",126 "PerPkg": "1",127 "PortMask": "0x0FF",128 "UMask": "0x70ff0ff",129 "Unit": "IIO"130 },131 {132 "BriefDescription": "Count of allocations in the completion buffer",133 "Counter": "2,3",134 "EventCode": "0xD5",135 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",136 "Experimental": "1",137 "FCMask": "0x07",138 "PerPkg": "1",139 "PortMask": "0x001",140 "UMask": "0x7001001",141 "Unit": "IIO"142 },143 {144 "BriefDescription": "Count of allocations in the completion buffer",145 "Counter": "2,3",146 "EventCode": "0xD5",147 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",148 "Experimental": "1",149 "FCMask": "0x07",150 "PerPkg": "1",151 "PortMask": "0x002",152 "UMask": "0x7002002",153 "Unit": "IIO"154 },155 {156 "BriefDescription": "Count of allocations in the completion buffer",157 "Counter": "2,3",158 "EventCode": "0xD5",159 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",160 "Experimental": "1",161 "FCMask": "0x07",162 "PerPkg": "1",163 "PortMask": "0x004",164 "UMask": "0x7004004",165 "Unit": "IIO"166 },167 {168 "BriefDescription": "Count of allocations in the completion buffer",169 "Counter": "2,3",170 "EventCode": "0xD5",171 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",172 "Experimental": "1",173 "FCMask": "0x07",174 "PerPkg": "1",175 "PortMask": "0x008",176 "UMask": "0x7008008",177 "Unit": "IIO"178 },179 {180 "BriefDescription": "Count of allocations in the completion buffer",181 "Counter": "2,3",182 "EventCode": "0xD5",183 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",184 "Experimental": "1",185 "FCMask": "0x07",186 "PerPkg": "1",187 "PortMask": "0x010",188 "UMask": "0x7010010",189 "Unit": "IIO"190 },191 {192 "BriefDescription": "Count of allocations in the completion buffer",193 "Counter": "2,3",194 "EventCode": "0xD5",195 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",196 "Experimental": "1",197 "FCMask": "0x07",198 "PerPkg": "1",199 "PortMask": "0x020",200 "UMask": "0x7020020",201 "Unit": "IIO"202 },203 {204 "BriefDescription": "Count of allocations in the completion buffer",205 "Counter": "2,3",206 "EventCode": "0xD5",207 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",208 "Experimental": "1",209 "FCMask": "0x07",210 "PerPkg": "1",211 "PortMask": "0x040",212 "UMask": "0x7040040",213 "Unit": "IIO"214 },215 {216 "BriefDescription": "Count of allocations in the completion buffer",217 "Counter": "2,3",218 "EventCode": "0xD5",219 "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",220 "Experimental": "1",221 "FCMask": "0x07",222 "PerPkg": "1",223 "PortMask": "0x080",224 "UMask": "0x7080080",225 "Unit": "IIO"226 },227 {228 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",229 "Counter": "2,3",230 "EventCode": "0xC0",231 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS",232 "FCMask": "0x07",233 "PerPkg": "1",234 "PortMask": "0x0FF",235 "UMask": "0x70ff004",236 "Unit": "IIO"237 },238 {239 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",240 "Counter": "2,3",241 "EventCode": "0xC0",242 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",243 "Experimental": "1",244 "FCMask": "0x07",245 "PerPkg": "1",246 "PortMask": "0x001",247 "UMask": "0x7001004",248 "Unit": "IIO"249 },250 {251 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",252 "Counter": "2,3",253 "EventCode": "0xC0",254 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",255 "Experimental": "1",256 "FCMask": "0x07",257 "PerPkg": "1",258 "PortMask": "0x002",259 "UMask": "0x7002004",260 "Unit": "IIO"261 },262 {263 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",264 "Counter": "2,3",265 "EventCode": "0xC0",266 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",267 "Experimental": "1",268 "FCMask": "0x07",269 "PerPkg": "1",270 "PortMask": "0x004",271 "UMask": "0x7004004",272 "Unit": "IIO"273 },274 {275 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",276 "Counter": "2,3",277 "EventCode": "0xC0",278 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",279 "Experimental": "1",280 "FCMask": "0x07",281 "PerPkg": "1",282 "PortMask": "0x008",283 "UMask": "0x7008004",284 "Unit": "IIO"285 },286 {287 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",288 "Counter": "2,3",289 "EventCode": "0xC0",290 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",291 "Experimental": "1",292 "FCMask": "0x07",293 "PerPkg": "1",294 "PortMask": "0x010",295 "UMask": "0x7010004",296 "Unit": "IIO"297 },298 {299 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",300 "Counter": "2,3",301 "EventCode": "0xC0",302 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",303 "Experimental": "1",304 "FCMask": "0x07",305 "PerPkg": "1",306 "PortMask": "0x020",307 "UMask": "0x7020004",308 "Unit": "IIO"309 },310 {311 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",312 "Counter": "2,3",313 "EventCode": "0xC0",314 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",315 "Experimental": "1",316 "FCMask": "0x07",317 "PerPkg": "1",318 "PortMask": "0x040",319 "UMask": "0x7040004",320 "Unit": "IIO"321 },322 {323 "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",324 "Counter": "2,3",325 "EventCode": "0xC0",326 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",327 "Experimental": "1",328 "FCMask": "0x07",329 "PerPkg": "1",330 "PortMask": "0x080",331 "UMask": "0x7080004",332 "Unit": "IIO"333 },334 {335 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",336 "Counter": "2,3",337 "EventCode": "0xC0",338 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",339 "FCMask": "0x07",340 "PerPkg": "1",341 "PortMask": "0x0FF",342 "UMask": "0x70ff001",343 "Unit": "IIO"344 },345 {346 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",347 "Counter": "2,3",348 "EventCode": "0xC0",349 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",350 "FCMask": "0x07",351 "PerPkg": "1",352 "PortMask": "0x001",353 "UMask": "0x7001001",354 "Unit": "IIO"355 },356 {357 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",358 "Counter": "2,3",359 "EventCode": "0xC0",360 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",361 "FCMask": "0x07",362 "PerPkg": "1",363 "PortMask": "0x002",364 "UMask": "0x7002001",365 "Unit": "IIO"366 },367 {368 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",369 "Counter": "2,3",370 "EventCode": "0xC0",371 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",372 "FCMask": "0x07",373 "PerPkg": "1",374 "PortMask": "0x004",375 "UMask": "0x7004001",376 "Unit": "IIO"377 },378 {379 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",380 "Counter": "2,3",381 "EventCode": "0xC0",382 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",383 "FCMask": "0x07",384 "PerPkg": "1",385 "PortMask": "0x008",386 "UMask": "0x7008001",387 "Unit": "IIO"388 },389 {390 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",391 "Counter": "2,3",392 "EventCode": "0xC0",393 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",394 "FCMask": "0x07",395 "PerPkg": "1",396 "PortMask": "0x010",397 "UMask": "0x7010001",398 "Unit": "IIO"399 },400 {401 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",402 "Counter": "2,3",403 "EventCode": "0xC0",404 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",405 "FCMask": "0x07",406 "PerPkg": "1",407 "PortMask": "0x020",408 "UMask": "0x7020001",409 "Unit": "IIO"410 },411 {412 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",413 "Counter": "2,3",414 "EventCode": "0xC0",415 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",416 "FCMask": "0x07",417 "PerPkg": "1",418 "PortMask": "0x040",419 "UMask": "0x7040001",420 "Unit": "IIO"421 },422 {423 "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",424 "Counter": "2,3",425 "EventCode": "0xC0",426 "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",427 "FCMask": "0x07",428 "PerPkg": "1",429 "PortMask": "0x080",430 "UMask": "0x7080001",431 "Unit": "IIO"432 },433 {434 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",435 "Counter": "0,1",436 "EventCode": "0x83",437 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",438 "FCMask": "0x07",439 "PerPkg": "1",440 "PortMask": "0x001",441 "UMask": "0x7001004",442 "Unit": "IIO"443 },444 {445 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",446 "Counter": "0,1",447 "EventCode": "0x83",448 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",449 "FCMask": "0x07",450 "PerPkg": "1",451 "PortMask": "0x02",452 "UMask": "0x7002004",453 "Unit": "IIO"454 },455 {456 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",457 "Counter": "0,1",458 "EventCode": "0x83",459 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",460 "FCMask": "0x07",461 "PerPkg": "1",462 "PortMask": "0x04",463 "UMask": "0x7004004",464 "Unit": "IIO"465 },466 {467 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",468 "Counter": "0,1",469 "EventCode": "0x83",470 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",471 "FCMask": "0x07",472 "PerPkg": "1",473 "PortMask": "0x08",474 "UMask": "0x7008004",475 "Unit": "IIO"476 },477 {478 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",479 "Counter": "0,1",480 "EventCode": "0x83",481 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",482 "FCMask": "0x07",483 "PerPkg": "1",484 "PortMask": "0x10",485 "UMask": "0x7010004",486 "Unit": "IIO"487 },488 {489 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",490 "Counter": "0,1",491 "EventCode": "0x83",492 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",493 "FCMask": "0x07",494 "PerPkg": "1",495 "PortMask": "0x20",496 "UMask": "0x7020004",497 "Unit": "IIO"498 },499 {500 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",501 "Counter": "0,1",502 "EventCode": "0x83",503 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",504 "FCMask": "0x07",505 "PerPkg": "1",506 "PortMask": "0x40",507 "UMask": "0x7040004",508 "Unit": "IIO"509 },510 {511 "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",512 "Counter": "0,1",513 "EventCode": "0x83",514 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",515 "FCMask": "0x07",516 "PerPkg": "1",517 "PortMask": "0x80",518 "UMask": "0x7080004",519 "Unit": "IIO"520 },521 {522 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",523 "Counter": "0,1",524 "EventCode": "0x83",525 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",526 "FCMask": "0x07",527 "PerPkg": "1",528 "PortMask": "0x001",529 "UMask": "0x7001001",530 "Unit": "IIO"531 },532 {533 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",534 "Counter": "0,1",535 "EventCode": "0x83",536 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",537 "FCMask": "0x07",538 "PerPkg": "1",539 "PortMask": "0x02",540 "UMask": "0x7002001",541 "Unit": "IIO"542 },543 {544 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",545 "Counter": "0,1",546 "EventCode": "0x83",547 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",548 "FCMask": "0x07",549 "PerPkg": "1",550 "PortMask": "0x04",551 "UMask": "0x7004001",552 "Unit": "IIO"553 },554 {555 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",556 "Counter": "0,1",557 "EventCode": "0x83",558 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",559 "FCMask": "0x07",560 "PerPkg": "1",561 "PortMask": "0x08",562 "UMask": "0x7008001",563 "Unit": "IIO"564 },565 {566 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",567 "Counter": "0,1",568 "EventCode": "0x83",569 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",570 "FCMask": "0x07",571 "PerPkg": "1",572 "PortMask": "0x10",573 "UMask": "0x7010001",574 "Unit": "IIO"575 },576 {577 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",578 "Counter": "0,1",579 "EventCode": "0x83",580 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",581 "FCMask": "0x07",582 "PerPkg": "1",583 "PortMask": "0x20",584 "UMask": "0x7020001",585 "Unit": "IIO"586 },587 {588 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",589 "Counter": "0,1",590 "EventCode": "0x83",591 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",592 "FCMask": "0x07",593 "PerPkg": "1",594 "PortMask": "0x40",595 "UMask": "0x7040001",596 "Unit": "IIO"597 },598 {599 "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",600 "Counter": "0,1",601 "EventCode": "0x83",602 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",603 "FCMask": "0x07",604 "PerPkg": "1",605 "PortMask": "0x80",606 "UMask": "0x7080001",607 "Unit": "IIO"608 },609 {610 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",611 "Counter": "0,1",612 "EventCode": "0x83",613 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",614 "Experimental": "1",615 "FCMask": "0x07",616 "PerPkg": "1",617 "PortMask": "0x001",618 "UMask": "0x7001002",619 "Unit": "IIO"620 },621 {622 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",623 "Counter": "0,1",624 "EventCode": "0x83",625 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",626 "Experimental": "1",627 "FCMask": "0x07",628 "PerPkg": "1",629 "PortMask": "0x002",630 "UMask": "0x7002002",631 "Unit": "IIO"632 },633 {634 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",635 "Counter": "0,1",636 "EventCode": "0x83",637 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",638 "Experimental": "1",639 "FCMask": "0x07",640 "PerPkg": "1",641 "PortMask": "0x004",642 "UMask": "0x7004002",643 "Unit": "IIO"644 },645 {646 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",647 "Counter": "0,1",648 "EventCode": "0x83",649 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",650 "Experimental": "1",651 "FCMask": "0x07",652 "PerPkg": "1",653 "PortMask": "0x008",654 "UMask": "0x7008002",655 "Unit": "IIO"656 },657 {658 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",659 "Counter": "0,1",660 "EventCode": "0x83",661 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",662 "Experimental": "1",663 "FCMask": "0x07",664 "PerPkg": "1",665 "PortMask": "0x010",666 "UMask": "0x7010002",667 "Unit": "IIO"668 },669 {670 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",671 "Counter": "0,1",672 "EventCode": "0x83",673 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",674 "Experimental": "1",675 "FCMask": "0x07",676 "PerPkg": "1",677 "PortMask": "0x020",678 "UMask": "0x7020002",679 "Unit": "IIO"680 },681 {682 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",683 "Counter": "0,1",684 "EventCode": "0x83",685 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",686 "Experimental": "1",687 "FCMask": "0x07",688 "PerPkg": "1",689 "PortMask": "0x040",690 "UMask": "0x7040002",691 "Unit": "IIO"692 },693 {694 "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",695 "Counter": "0,1",696 "EventCode": "0x83",697 "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",698 "Experimental": "1",699 "FCMask": "0x07",700 "PerPkg": "1",701 "PortMask": "0x080",702 "UMask": "0x7080002",703 "Unit": "IIO"704 },705 {706 "BriefDescription": "IOTLB Hits to a 1G Page",707 "Counter": "0,1,2,3",708 "EventCode": "0x40",709 "EventName": "UNC_IIO_IOMMU0.1G_HITS",710 "Experimental": "1",711 "PerPkg": "1",712 "PortMask": "0x000",713 "UMask": "0x10",714 "Unit": "IIO"715 },716 {717 "BriefDescription": "IOTLB Hits to a 2M Page",718 "Counter": "0,1,2,3",719 "EventCode": "0x40",720 "EventName": "UNC_IIO_IOMMU0.2M_HITS",721 "Experimental": "1",722 "PerPkg": "1",723 "PortMask": "0x000",724 "UMask": "0x8",725 "Unit": "IIO"726 },727 {728 "BriefDescription": "IOTLB Hits to a 4K Page",729 "Counter": "0,1,2,3",730 "EventCode": "0x40",731 "EventName": "UNC_IIO_IOMMU0.4K_HITS",732 "Experimental": "1",733 "PerPkg": "1",734 "PortMask": "0x000",735 "UMask": "0x4",736 "Unit": "IIO"737 },738 {739 "BriefDescription": "Context cache hits",740 "Counter": "0,1,2,3",741 "EventCode": "0x40",742 "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",743 "Experimental": "1",744 "PerPkg": "1",745 "PortMask": "0x000",746 "UMask": "0x80",747 "Unit": "IIO"748 },749 {750 "BriefDescription": "Context cache lookups",751 "Counter": "0,1,2,3",752 "EventCode": "0x40",753 "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",754 "Experimental": "1",755 "PerPkg": "1",756 "PortMask": "0x000",757 "UMask": "0x40",758 "Unit": "IIO"759 },760 {761 "BriefDescription": "IOTLB lookups first",762 "Counter": "0,1,2,3",763 "EventCode": "0x40",764 "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",765 "Experimental": "1",766 "PerPkg": "1",767 "PortMask": "0x000",768 "UMask": "0x1",769 "Unit": "IIO"770 },771 {772 "BriefDescription": "IOTLB Fills (same as IOTLB miss)",773 "Counter": "0,1,2,3",774 "EventCode": "0x40",775 "EventName": "UNC_IIO_IOMMU0.MISSES",776 "Experimental": "1",777 "PerPkg": "1",778 "PortMask": "0x000",779 "UMask": "0x20",780 "Unit": "IIO"781 },782 {783 "BriefDescription": "IOMMU memory access (both low and high priority)",784 "Counter": "0,1,2,3",785 "EventCode": "0x41",786 "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",787 "Experimental": "1",788 "PerPkg": "1",789 "PortMask": "0x000",790 "UMask": "0xc0",791 "Unit": "IIO"792 },793 {794 "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page",795 "Counter": "0,1,2,3",796 "EventCode": "0x41",797 "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS",798 "Experimental": "1",799 "PerPkg": "1",800 "PortMask": "0x000",801 "UMask": "0x4",802 "Unit": "IIO"803 },804 {805 "BriefDescription": "Second Level Page Walk Cache Hit to a 256T page",806 "Counter": "0,1,2,3",807 "EventCode": "0x41",808 "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS",809 "Experimental": "1",810 "PerPkg": "1",811 "PortMask": "0x000",812 "UMask": "0x10",813 "Unit": "IIO"814 },815 {816 "BriefDescription": "Second Level Page Walk Cache Hit to a 512G page",817 "Counter": "0,1,2,3",818 "EventCode": "0x41",819 "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS",820 "Experimental": "1",821 "PerPkg": "1",822 "PortMask": "0x000",823 "UMask": "0x8",824 "Unit": "IIO"825 },826 {827 "BriefDescription": "-",828 "Counter": "0,1,2,3",829 "EventCode": "0x8e",830 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",831 "Experimental": "1",832 "FCMask": "0x07",833 "PerPkg": "1",834 "PortMask": "0x0FF",835 "UMask": "0x70ff080",836 "Unit": "IIO"837 },838 {839 "BriefDescription": "-",840 "Counter": "0,1,2,3",841 "EventCode": "0x8e",842 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",843 "Experimental": "1",844 "FCMask": "0x07",845 "PerPkg": "1",846 "PortMask": "0x0FF",847 "UMask": "0x70ff040",848 "Unit": "IIO"849 },850 {851 "BriefDescription": "-",852 "Counter": "0,1,2,3",853 "EventCode": "0x8e",854 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",855 "Experimental": "1",856 "FCMask": "0x07",857 "PerPkg": "1",858 "PortMask": "0x0FF",859 "UMask": "0x70ff020",860 "Unit": "IIO"861 },862 {863 "BriefDescription": "-",864 "Counter": "0,1,2,3",865 "EventCode": "0x8e",866 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",867 "Experimental": "1",868 "FCMask": "0x07",869 "PerPkg": "1",870 "PortMask": "0x0FF",871 "UMask": "0x70ff002",872 "Unit": "IIO"873 },874 {875 "BriefDescription": "-",876 "Counter": "0,1,2,3",877 "EventCode": "0x8e",878 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",879 "Experimental": "1",880 "FCMask": "0x07",881 "PerPkg": "1",882 "PortMask": "0x0FF",883 "UMask": "0x70ff008",884 "Unit": "IIO"885 },886 {887 "BriefDescription": "-",888 "Counter": "0,1,2,3",889 "EventCode": "0x8e",890 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",891 "Experimental": "1",892 "FCMask": "0x07",893 "PerPkg": "1",894 "PortMask": "0x0FF",895 "UMask": "0x70ff001",896 "Unit": "IIO"897 },898 {899 "BriefDescription": "-",900 "Counter": "0,1,2,3",901 "EventCode": "0x8e",902 "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",903 "Experimental": "1",904 "FCMask": "0x07",905 "PerPkg": "1",906 "PortMask": "0x0FF",907 "UMask": "0x70ff004",908 "Unit": "IIO"909 },910 {911 "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy",912 "Counter": "0,1,2,3",913 "EventCode": "0x42",914 "EventName": "UNC_IIO_PWT_OCCUPANCY",915 "Experimental": "1",916 "PerPkg": "1",917 "PortMask": "0x000",918 "Unit": "IIO"919 },920 {921 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",922 "Counter": "2,3",923 "EventCode": "0xC1",924 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",925 "FCMask": "0x07",926 "PerPkg": "1",927 "PortMask": "0x001",928 "UMask": "0x7001004",929 "Unit": "IIO"930 },931 {932 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",933 "Counter": "2,3",934 "EventCode": "0xC1",935 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",936 "FCMask": "0x07",937 "PerPkg": "1",938 "PortMask": "0x002",939 "UMask": "0x7002004",940 "Unit": "IIO"941 },942 {943 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",944 "Counter": "2,3",945 "EventCode": "0xC1",946 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",947 "FCMask": "0x07",948 "PerPkg": "1",949 "PortMask": "0x004",950 "UMask": "0x7004004",951 "Unit": "IIO"952 },953 {954 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",955 "Counter": "2,3",956 "EventCode": "0xC1",957 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",958 "FCMask": "0x07",959 "PerPkg": "1",960 "PortMask": "0x008",961 "UMask": "0x7008004",962 "Unit": "IIO"963 },964 {965 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",966 "Counter": "2,3",967 "EventCode": "0xC1",968 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",969 "FCMask": "0x07",970 "PerPkg": "1",971 "PortMask": "0x010",972 "UMask": "0x7010004",973 "Unit": "IIO"974 },975 {976 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",977 "Counter": "2,3",978 "EventCode": "0xC1",979 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",980 "FCMask": "0x07",981 "PerPkg": "1",982 "PortMask": "0x020",983 "UMask": "0x7020004",984 "Unit": "IIO"985 },986 {987 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",988 "Counter": "2,3",989 "EventCode": "0xC1",990 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",991 "FCMask": "0x07",992 "PerPkg": "1",993 "PortMask": "0x040",994 "UMask": "0x7040004",995 "Unit": "IIO"996 },997 {998 "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",999 "Counter": "2,3",1000 "EventCode": "0xC1",1001 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",1002 "FCMask": "0x07",1003 "PerPkg": "1",1004 "PortMask": "0x080",1005 "UMask": "0x7080004",1006 "Unit": "IIO"1007 },1008 {1009 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1010 "Counter": "2,3",1011 "EventCode": "0xC1",1012 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",1013 "FCMask": "0x07",1014 "PerPkg": "1",1015 "PortMask": "0x001",1016 "UMask": "0x7001001",1017 "Unit": "IIO"1018 },1019 {1020 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1021 "Counter": "2,3",1022 "EventCode": "0xC1",1023 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",1024 "FCMask": "0x07",1025 "PerPkg": "1",1026 "PortMask": "0x002",1027 "UMask": "0x7002001",1028 "Unit": "IIO"1029 },1030 {1031 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1032 "Counter": "2,3",1033 "EventCode": "0xC1",1034 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",1035 "FCMask": "0x07",1036 "PerPkg": "1",1037 "PortMask": "0x004",1038 "UMask": "0x7004001",1039 "Unit": "IIO"1040 },1041 {1042 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1043 "Counter": "2,3",1044 "EventCode": "0xC1",1045 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",1046 "FCMask": "0x07",1047 "PerPkg": "1",1048 "PortMask": "0x008",1049 "UMask": "0x7008001",1050 "Unit": "IIO"1051 },1052 {1053 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1054 "Counter": "2,3",1055 "EventCode": "0xC1",1056 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",1057 "FCMask": "0x07",1058 "PerPkg": "1",1059 "PortMask": "0x010",1060 "UMask": "0x7010001",1061 "Unit": "IIO"1062 },1063 {1064 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1065 "Counter": "2,3",1066 "EventCode": "0xC1",1067 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",1068 "FCMask": "0x07",1069 "PerPkg": "1",1070 "PortMask": "0x020",1071 "UMask": "0x7020001",1072 "Unit": "IIO"1073 },1074 {1075 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1076 "Counter": "2,3",1077 "EventCode": "0xC1",1078 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",1079 "FCMask": "0x07",1080 "PerPkg": "1",1081 "PortMask": "0x040",1082 "UMask": "0x7040001",1083 "Unit": "IIO"1084 },1085 {1086 "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",1087 "Counter": "2,3",1088 "EventCode": "0xC1",1089 "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",1090 "FCMask": "0x07",1091 "PerPkg": "1",1092 "PortMask": "0x080",1093 "UMask": "0x7080001",1094 "Unit": "IIO"1095 },1096 {1097 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1098 "Counter": "0,1",1099 "EventCode": "0x84",1100 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",1101 "FCMask": "0x07",1102 "PerPkg": "1",1103 "PortMask": "0x001",1104 "UMask": "0x7001004",1105 "Unit": "IIO"1106 },1107 {1108 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1109 "Counter": "0,1",1110 "EventCode": "0x84",1111 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",1112 "FCMask": "0x07",1113 "PerPkg": "1",1114 "PortMask": "0x002",1115 "UMask": "0x7002004",1116 "Unit": "IIO"1117 },1118 {1119 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1120 "Counter": "0,1",1121 "EventCode": "0x84",1122 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",1123 "FCMask": "0x07",1124 "PerPkg": "1",1125 "PortMask": "0x004",1126 "UMask": "0x7004004",1127 "Unit": "IIO"1128 },1129 {1130 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1131 "Counter": "0,1",1132 "EventCode": "0x84",1133 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",1134 "FCMask": "0x07",1135 "PerPkg": "1",1136 "PortMask": "0x008",1137 "UMask": "0x7008004",1138 "Unit": "IIO"1139 },1140 {1141 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1142 "Counter": "0,1",1143 "EventCode": "0x84",1144 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",1145 "FCMask": "0x07",1146 "PerPkg": "1",1147 "PortMask": "0x010",1148 "UMask": "0x7010004",1149 "Unit": "IIO"1150 },1151 {1152 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1153 "Counter": "0,1",1154 "EventCode": "0x84",1155 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",1156 "FCMask": "0x07",1157 "PerPkg": "1",1158 "PortMask": "0x020",1159 "UMask": "0x7020004",1160 "Unit": "IIO"1161 },1162 {1163 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1164 "Counter": "0,1",1165 "EventCode": "0x84",1166 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",1167 "FCMask": "0x07",1168 "PerPkg": "1",1169 "PortMask": "0x040",1170 "UMask": "0x7040004",1171 "Unit": "IIO"1172 },1173 {1174 "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",1175 "Counter": "0,1",1176 "EventCode": "0x84",1177 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",1178 "FCMask": "0x07",1179 "PerPkg": "1",1180 "PortMask": "0x080",1181 "UMask": "0x7080004",1182 "Unit": "IIO"1183 },1184 {1185 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1186 "Counter": "0,1",1187 "EventCode": "0x84",1188 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",1189 "FCMask": "0x07",1190 "PerPkg": "1",1191 "PortMask": "0x001",1192 "UMask": "0x7001001",1193 "Unit": "IIO"1194 },1195 {1196 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1197 "Counter": "0,1",1198 "EventCode": "0x84",1199 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",1200 "FCMask": "0x07",1201 "PerPkg": "1",1202 "PortMask": "0x002",1203 "UMask": "0x7002001",1204 "Unit": "IIO"1205 },1206 {1207 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1208 "Counter": "0,1",1209 "EventCode": "0x84",1210 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",1211 "FCMask": "0x07",1212 "PerPkg": "1",1213 "PortMask": "0x004",1214 "UMask": "0x7004001",1215 "Unit": "IIO"1216 },1217 {1218 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1219 "Counter": "0,1",1220 "EventCode": "0x84",1221 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",1222 "FCMask": "0x07",1223 "PerPkg": "1",1224 "PortMask": "0x008",1225 "UMask": "0x7008001",1226 "Unit": "IIO"1227 },1228 {1229 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1230 "Counter": "0,1",1231 "EventCode": "0x84",1232 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",1233 "FCMask": "0x07",1234 "PerPkg": "1",1235 "PortMask": "0x010",1236 "UMask": "0x7010001",1237 "Unit": "IIO"1238 },1239 {1240 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1241 "Counter": "0,1",1242 "EventCode": "0x84",1243 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",1244 "FCMask": "0x07",1245 "PerPkg": "1",1246 "PortMask": "0x020",1247 "UMask": "0x7020001",1248 "Unit": "IIO"1249 },1250 {1251 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1252 "Counter": "0,1",1253 "EventCode": "0x84",1254 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",1255 "FCMask": "0x07",1256 "PerPkg": "1",1257 "PortMask": "0x040",1258 "UMask": "0x7040001",1259 "Unit": "IIO"1260 },1261 {1262 "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",1263 "Counter": "0,1",1264 "EventCode": "0x84",1265 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",1266 "FCMask": "0x07",1267 "PerPkg": "1",1268 "PortMask": "0x080",1269 "UMask": "0x7080001",1270 "Unit": "IIO"1271 },1272 {1273 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1274 "Counter": "0,1",1275 "EventCode": "0x84",1276 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",1277 "Experimental": "1",1278 "FCMask": "0x07",1279 "PerPkg": "1",1280 "PortMask": "0x001",1281 "UMask": "0x7001002",1282 "Unit": "IIO"1283 },1284 {1285 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1286 "Counter": "0,1",1287 "EventCode": "0x84",1288 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",1289 "Experimental": "1",1290 "FCMask": "0x07",1291 "PerPkg": "1",1292 "PortMask": "0x002",1293 "UMask": "0x7002002",1294 "Unit": "IIO"1295 },1296 {1297 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1298 "Counter": "0,1",1299 "EventCode": "0x84",1300 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",1301 "Experimental": "1",1302 "FCMask": "0x07",1303 "PerPkg": "1",1304 "PortMask": "0x004",1305 "UMask": "0x7004002",1306 "Unit": "IIO"1307 },1308 {1309 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1310 "Counter": "0,1",1311 "EventCode": "0x84",1312 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",1313 "Experimental": "1",1314 "FCMask": "0x07",1315 "PerPkg": "1",1316 "PortMask": "0x008",1317 "UMask": "0x7008002",1318 "Unit": "IIO"1319 },1320 {1321 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1322 "Counter": "0,1",1323 "EventCode": "0x84",1324 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",1325 "Experimental": "1",1326 "FCMask": "0x07",1327 "PerPkg": "1",1328 "PortMask": "0x010",1329 "UMask": "0x7010002",1330 "Unit": "IIO"1331 },1332 {1333 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1334 "Counter": "0,1",1335 "EventCode": "0x84",1336 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",1337 "Experimental": "1",1338 "FCMask": "0x07",1339 "PerPkg": "1",1340 "PortMask": "0x020",1341 "UMask": "0x7020002",1342 "Unit": "IIO"1343 },1344 {1345 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1346 "Counter": "0,1",1347 "EventCode": "0x84",1348 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",1349 "Experimental": "1",1350 "FCMask": "0x07",1351 "PerPkg": "1",1352 "PortMask": "0x040",1353 "UMask": "0x7040002",1354 "Unit": "IIO"1355 },1356 {1357 "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",1358 "Counter": "0,1",1359 "EventCode": "0x84",1360 "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",1361 "Experimental": "1",1362 "FCMask": "0x07",1363 "PerPkg": "1",1364 "PortMask": "0x080",1365 "UMask": "0x7080002",1366 "Unit": "IIO"1367 }1368]1369