927 lines · json
1[2 {3 "BriefDescription": "L1D data line replacements",4 "Counter": "0,1,2,3",5 "EventCode": "0x51",6 "EventName": "L1D.REPLACEMENT",7 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",8 "SampleAfterValue": "2000003",9 "UMask": "0x1"10 },11 {12 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",13 "Counter": "0,1,2,3",14 "CounterMask": "1",15 "EventCode": "0x48",16 "EventName": "L1D_PEND_MISS.FB_FULL",17 "SampleAfterValue": "2000003",18 "UMask": "0x2"19 },20 {21 "BriefDescription": "L1D miss outstanding duration in cycles",22 "Counter": "2",23 "EventCode": "0x48",24 "EventName": "L1D_PEND_MISS.PENDING",25 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",26 "SampleAfterValue": "2000003",27 "UMask": "0x1"28 },29 {30 "BriefDescription": "Cycles with L1D load Misses outstanding.",31 "Counter": "2",32 "CounterMask": "1",33 "EventCode": "0x48",34 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",35 "SampleAfterValue": "2000003",36 "UMask": "0x1"37 },38 {39 "AnyThread": "1",40 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",41 "Counter": "2",42 "CounterMask": "1",43 "EventCode": "0x48",44 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",45 "SampleAfterValue": "2000003",46 "UMask": "0x1"47 },48 {49 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",50 "Counter": "0,1,2,3",51 "EventCode": "0x48",52 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",53 "SampleAfterValue": "2000003",54 "UMask": "0x2"55 },56 {57 "BriefDescription": "Not rejected writebacks that hit L2 cache",58 "Counter": "0,1,2,3",59 "EventCode": "0x27",60 "EventName": "L2_DEMAND_RQSTS.WB_HIT",61 "PublicDescription": "Not rejected writebacks that hit L2 cache.",62 "SampleAfterValue": "200003",63 "UMask": "0x50"64 },65 {66 "BriefDescription": "L2 cache lines filling L2",67 "Counter": "0,1,2,3",68 "EventCode": "0xF1",69 "EventName": "L2_LINES_IN.ALL",70 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",71 "SampleAfterValue": "100003",72 "UMask": "0x7"73 },74 {75 "BriefDescription": "L2 cache lines in E state filling L2",76 "Counter": "0,1,2,3",77 "EventCode": "0xF1",78 "EventName": "L2_LINES_IN.E",79 "PublicDescription": "L2 cache lines in E state filling L2.",80 "SampleAfterValue": "100003",81 "UMask": "0x4"82 },83 {84 "BriefDescription": "L2 cache lines in I state filling L2",85 "Counter": "0,1,2,3",86 "EventCode": "0xF1",87 "EventName": "L2_LINES_IN.I",88 "PublicDescription": "L2 cache lines in I state filling L2.",89 "SampleAfterValue": "100003",90 "UMask": "0x1"91 },92 {93 "BriefDescription": "L2 cache lines in S state filling L2",94 "Counter": "0,1,2,3",95 "EventCode": "0xF1",96 "EventName": "L2_LINES_IN.S",97 "PublicDescription": "L2 cache lines in S state filling L2.",98 "SampleAfterValue": "100003",99 "UMask": "0x2"100 },101 {102 "BriefDescription": "Clean L2 cache lines evicted by demand",103 "Counter": "0,1,2,3",104 "EventCode": "0xF2",105 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",106 "PublicDescription": "Clean L2 cache lines evicted by demand.",107 "SampleAfterValue": "100003",108 "UMask": "0x5"109 },110 {111 "BriefDescription": "Dirty L2 cache lines evicted by demand",112 "Counter": "0,1,2,3",113 "EventCode": "0xF2",114 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",115 "PublicDescription": "Dirty L2 cache lines evicted by demand.",116 "SampleAfterValue": "100003",117 "UMask": "0x6"118 },119 {120 "BriefDescription": "L2 code requests",121 "Counter": "0,1,2,3",122 "EventCode": "0x24",123 "EventName": "L2_RQSTS.ALL_CODE_RD",124 "PublicDescription": "Counts all L2 code requests.",125 "SampleAfterValue": "200003",126 "UMask": "0xe4"127 },128 {129 "BriefDescription": "Demand Data Read requests",130 "Counter": "0,1,2,3",131 "Errata": "HSD78, HSM80",132 "EventCode": "0x24",133 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",134 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",135 "SampleAfterValue": "200003",136 "UMask": "0xe1"137 },138 {139 "BriefDescription": "Demand requests that miss L2 cache",140 "Counter": "0,1,2,3",141 "Errata": "HSD78, HSM80",142 "EventCode": "0x24",143 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",144 "PublicDescription": "Demand requests that miss L2 cache.",145 "SampleAfterValue": "200003",146 "UMask": "0x27"147 },148 {149 "BriefDescription": "Demand requests to L2 cache",150 "Counter": "0,1,2,3",151 "Errata": "HSD78, HSM80",152 "EventCode": "0x24",153 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",154 "PublicDescription": "Demand requests to L2 cache.",155 "SampleAfterValue": "200003",156 "UMask": "0xe7"157 },158 {159 "BriefDescription": "Requests from L2 hardware prefetchers",160 "Counter": "0,1,2,3",161 "EventCode": "0x24",162 "EventName": "L2_RQSTS.ALL_PF",163 "PublicDescription": "Counts all L2 HW prefetcher requests.",164 "SampleAfterValue": "200003",165 "UMask": "0xf8"166 },167 {168 "BriefDescription": "RFO requests to L2 cache",169 "Counter": "0,1,2,3",170 "EventCode": "0x24",171 "EventName": "L2_RQSTS.ALL_RFO",172 "PublicDescription": "Counts all L2 store RFO requests.",173 "SampleAfterValue": "200003",174 "UMask": "0xe2"175 },176 {177 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",178 "Counter": "0,1,2,3",179 "EventCode": "0x24",180 "EventName": "L2_RQSTS.CODE_RD_HIT",181 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",182 "SampleAfterValue": "200003",183 "UMask": "0xc4"184 },185 {186 "BriefDescription": "L2 cache misses when fetching instructions",187 "Counter": "0,1,2,3",188 "EventCode": "0x24",189 "EventName": "L2_RQSTS.CODE_RD_MISS",190 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",191 "SampleAfterValue": "200003",192 "UMask": "0x24"193 },194 {195 "BriefDescription": "Demand Data Read requests that hit L2 cache",196 "Counter": "0,1,2,3",197 "Errata": "HSD78, HSM80",198 "EventCode": "0x24",199 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",200 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",201 "SampleAfterValue": "200003",202 "UMask": "0xc1"203 },204 {205 "BriefDescription": "Demand Data Read miss L2, no rejects",206 "Counter": "0,1,2,3",207 "Errata": "HSD78, HSM80",208 "EventCode": "0x24",209 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",210 "PublicDescription": "Demand data read requests that missed L2, no rejects.",211 "SampleAfterValue": "200003",212 "UMask": "0x21"213 },214 {215 "BriefDescription": "L2 prefetch requests that hit L2 cache",216 "Counter": "0,1,2,3",217 "EventCode": "0x24",218 "EventName": "L2_RQSTS.L2_PF_HIT",219 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",220 "SampleAfterValue": "200003",221 "UMask": "0xd0"222 },223 {224 "BriefDescription": "L2 prefetch requests that miss L2 cache",225 "Counter": "0,1,2,3",226 "EventCode": "0x24",227 "EventName": "L2_RQSTS.L2_PF_MISS",228 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",229 "SampleAfterValue": "200003",230 "UMask": "0x30"231 },232 {233 "BriefDescription": "All requests that miss L2 cache",234 "Counter": "0,1,2,3",235 "Errata": "HSD78, HSM80",236 "EventCode": "0x24",237 "EventName": "L2_RQSTS.MISS",238 "PublicDescription": "All requests that missed L2.",239 "SampleAfterValue": "200003",240 "UMask": "0x3f"241 },242 {243 "BriefDescription": "All L2 requests",244 "Counter": "0,1,2,3",245 "Errata": "HSD78, HSM80",246 "EventCode": "0x24",247 "EventName": "L2_RQSTS.REFERENCES",248 "PublicDescription": "All requests to L2 cache.",249 "SampleAfterValue": "200003",250 "UMask": "0xff"251 },252 {253 "BriefDescription": "RFO requests that hit L2 cache",254 "Counter": "0,1,2,3",255 "EventCode": "0x24",256 "EventName": "L2_RQSTS.RFO_HIT",257 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",258 "SampleAfterValue": "200003",259 "UMask": "0xc2"260 },261 {262 "BriefDescription": "RFO requests that miss L2 cache",263 "Counter": "0,1,2,3",264 "EventCode": "0x24",265 "EventName": "L2_RQSTS.RFO_MISS",266 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",267 "SampleAfterValue": "200003",268 "UMask": "0x22"269 },270 {271 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",272 "Counter": "0,1,2,3",273 "EventCode": "0xf0",274 "EventName": "L2_TRANS.ALL_PF",275 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",276 "SampleAfterValue": "200003",277 "UMask": "0x8"278 },279 {280 "BriefDescription": "Transactions accessing L2 pipe",281 "Counter": "0,1,2,3",282 "EventCode": "0xf0",283 "EventName": "L2_TRANS.ALL_REQUESTS",284 "PublicDescription": "Transactions accessing L2 pipe.",285 "SampleAfterValue": "200003",286 "UMask": "0x80"287 },288 {289 "BriefDescription": "L2 cache accesses when fetching instructions",290 "Counter": "0,1,2,3",291 "EventCode": "0xf0",292 "EventName": "L2_TRANS.CODE_RD",293 "PublicDescription": "L2 cache accesses when fetching instructions.",294 "SampleAfterValue": "200003",295 "UMask": "0x4"296 },297 {298 "BriefDescription": "Demand Data Read requests that access L2 cache",299 "Counter": "0,1,2,3",300 "EventCode": "0xf0",301 "EventName": "L2_TRANS.DEMAND_DATA_RD",302 "PublicDescription": "Demand data read requests that access L2 cache.",303 "SampleAfterValue": "200003",304 "UMask": "0x1"305 },306 {307 "BriefDescription": "L1D writebacks that access L2 cache",308 "Counter": "0,1,2,3",309 "EventCode": "0xf0",310 "EventName": "L2_TRANS.L1D_WB",311 "PublicDescription": "L1D writebacks that access L2 cache.",312 "SampleAfterValue": "200003",313 "UMask": "0x10"314 },315 {316 "BriefDescription": "L2 fill requests that access L2 cache",317 "Counter": "0,1,2,3",318 "EventCode": "0xf0",319 "EventName": "L2_TRANS.L2_FILL",320 "PublicDescription": "L2 fill requests that access L2 cache.",321 "SampleAfterValue": "200003",322 "UMask": "0x20"323 },324 {325 "BriefDescription": "L2 writebacks that access L2 cache",326 "Counter": "0,1,2,3",327 "EventCode": "0xf0",328 "EventName": "L2_TRANS.L2_WB",329 "PublicDescription": "L2 writebacks that access L2 cache.",330 "SampleAfterValue": "200003",331 "UMask": "0x40"332 },333 {334 "BriefDescription": "RFO requests that access L2 cache",335 "Counter": "0,1,2,3",336 "EventCode": "0xf0",337 "EventName": "L2_TRANS.RFO",338 "PublicDescription": "RFO requests that access L2 cache.",339 "SampleAfterValue": "200003",340 "UMask": "0x2"341 },342 {343 "BriefDescription": "Cycles when L1D is locked",344 "Counter": "0,1,2,3",345 "EventCode": "0x63",346 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",347 "PublicDescription": "Cycles in which the L1D is locked.",348 "SampleAfterValue": "2000003",349 "UMask": "0x2"350 },351 {352 "BriefDescription": "Core-originated cacheable demand requests missed L3",353 "Counter": "0,1,2,3",354 "EventCode": "0x2E",355 "EventName": "LONGEST_LAT_CACHE.MISS",356 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",357 "SampleAfterValue": "100003",358 "UMask": "0x41"359 },360 {361 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",362 "Counter": "0,1,2,3",363 "EventCode": "0x2E",364 "EventName": "LONGEST_LAT_CACHE.REFERENCE",365 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",366 "SampleAfterValue": "100003",367 "UMask": "0x4f"368 },369 {370 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",371 "Counter": "0,1,2,3",372 "Data_LA": "1",373 "Errata": "HSD29, HSD25, HSM26, HSM30",374 "EventCode": "0xD2",375 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",376 "PEBS": "1",377 "SampleAfterValue": "20011",378 "UMask": "0x2"379 },380 {381 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",382 "Counter": "0,1,2,3",383 "Data_LA": "1",384 "Errata": "HSD29, HSD25, HSM26, HSM30",385 "EventCode": "0xD2",386 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",387 "PEBS": "1",388 "SampleAfterValue": "20011",389 "UMask": "0x4"390 },391 {392 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",393 "Counter": "0,1,2,3",394 "Data_LA": "1",395 "Errata": "HSD29, HSD25, HSM26, HSM30",396 "EventCode": "0xD2",397 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",398 "PEBS": "1",399 "SampleAfterValue": "20011",400 "UMask": "0x1"401 },402 {403 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",404 "Counter": "0,1,2,3",405 "Data_LA": "1",406 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",407 "EventCode": "0xD2",408 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",409 "PEBS": "1",410 "SampleAfterValue": "100003",411 "UMask": "0x8"412 },413 {414 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",415 "Counter": "0,1,2,3",416 "Data_LA": "1",417 "Errata": "HSD74, HSD29, HSD25, HSM30",418 "EventCode": "0xD3",419 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",420 "PEBS": "1",421 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",422 "SampleAfterValue": "100003",423 "UMask": "0x1"424 },425 {426 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",427 "Counter": "0,1,2,3",428 "Data_LA": "1",429 "Errata": "HSM30",430 "EventCode": "0xD1",431 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",432 "PEBS": "1",433 "SampleAfterValue": "100003",434 "UMask": "0x40"435 },436 {437 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",438 "Counter": "0,1,2,3",439 "Data_LA": "1",440 "Errata": "HSD29, HSM30",441 "EventCode": "0xD1",442 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",443 "PEBS": "1",444 "SampleAfterValue": "2000003",445 "UMask": "0x1"446 },447 {448 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",449 "Counter": "0,1,2,3",450 "Data_LA": "1",451 "Errata": "HSM30",452 "EventCode": "0xD1",453 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",454 "PEBS": "1",455 "PublicDescription": "Retired load uops missed L1 cache as data sources.",456 "SampleAfterValue": "100003",457 "UMask": "0x8"458 },459 {460 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",461 "Counter": "0,1,2,3",462 "Data_LA": "1",463 "Errata": "HSD76, HSD29, HSM30",464 "EventCode": "0xD1",465 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",466 "PEBS": "1",467 "SampleAfterValue": "100003",468 "UMask": "0x2"469 },470 {471 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",472 "Counter": "0,1,2,3",473 "Data_LA": "1",474 "Errata": "HSD29, HSM30",475 "EventCode": "0xD1",476 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",477 "PEBS": "1",478 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",479 "SampleAfterValue": "50021",480 "UMask": "0x10"481 },482 {483 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",484 "Counter": "0,1,2,3",485 "Data_LA": "1",486 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",487 "EventCode": "0xD1",488 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",489 "PEBS": "1",490 "PublicDescription": "Retired load uops with L3 cache hits as data sources.",491 "SampleAfterValue": "50021",492 "UMask": "0x4"493 },494 {495 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",496 "Counter": "0,1,2,3",497 "Data_LA": "1",498 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",499 "EventCode": "0xD1",500 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",501 "PEBS": "1",502 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",503 "SampleAfterValue": "100003",504 "UMask": "0x20"505 },506 {507 "BriefDescription": "Retired load uops.",508 "Counter": "0,1,2,3",509 "Data_LA": "1",510 "Errata": "HSD29, HSM30",511 "EventCode": "0xD0",512 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",513 "PEBS": "1",514 "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",515 "SampleAfterValue": "2000003",516 "UMask": "0x81"517 },518 {519 "BriefDescription": "Retired store uops.",520 "Counter": "0,1,2,3",521 "Data_LA": "1",522 "Errata": "HSD29, HSM30",523 "EventCode": "0xD0",524 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",525 "PEBS": "1",526 "PublicDescription": "Counts all retired store uops.",527 "SampleAfterValue": "2000003",528 "UMask": "0x82"529 },530 {531 "BriefDescription": "Retired load uops with locked access.",532 "Counter": "0,1,2,3",533 "Data_LA": "1",534 "Errata": "HSD76, HSD29, HSM30",535 "EventCode": "0xD0",536 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",537 "PEBS": "1",538 "SampleAfterValue": "100003",539 "UMask": "0x21"540 },541 {542 "BriefDescription": "Retired load uops that split across a cacheline boundary.",543 "Counter": "0,1,2,3",544 "Data_LA": "1",545 "Errata": "HSD29, HSM30",546 "EventCode": "0xD0",547 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",548 "PEBS": "1",549 "SampleAfterValue": "100003",550 "UMask": "0x41"551 },552 {553 "BriefDescription": "Retired store uops that split across a cacheline boundary.",554 "Counter": "0,1,2,3",555 "Data_LA": "1",556 "Errata": "HSD29, HSM30",557 "EventCode": "0xD0",558 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",559 "PEBS": "1",560 "SampleAfterValue": "100003",561 "UMask": "0x42"562 },563 {564 "BriefDescription": "Retired load uops that miss the STLB.",565 "Counter": "0,1,2,3",566 "Data_LA": "1",567 "Errata": "HSD29, HSM30",568 "EventCode": "0xD0",569 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",570 "PEBS": "1",571 "SampleAfterValue": "100003",572 "UMask": "0x11"573 },574 {575 "BriefDescription": "Retired store uops that miss the STLB.",576 "Counter": "0,1,2,3",577 "Data_LA": "1",578 "Errata": "HSD29, HSM30",579 "EventCode": "0xD0",580 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",581 "PEBS": "1",582 "SampleAfterValue": "100003",583 "UMask": "0x12"584 },585 {586 "BriefDescription": "Demand and prefetch data reads",587 "Counter": "0,1,2,3",588 "EventCode": "0xB0",589 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",590 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",591 "SampleAfterValue": "100003",592 "UMask": "0x8"593 },594 {595 "BriefDescription": "Cacheable and noncacheable code read requests",596 "Counter": "0,1,2,3",597 "EventCode": "0xB0",598 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",599 "PublicDescription": "Demand code read requests sent to uncore.",600 "SampleAfterValue": "100003",601 "UMask": "0x2"602 },603 {604 "BriefDescription": "Demand Data Read requests sent to uncore",605 "Counter": "0,1,2,3",606 "Errata": "HSD78, HSM80",607 "EventCode": "0xb0",608 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",609 "PublicDescription": "Demand data read requests sent to uncore.",610 "SampleAfterValue": "100003",611 "UMask": "0x1"612 },613 {614 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",615 "Counter": "0,1,2,3",616 "EventCode": "0xB0",617 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",618 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",619 "SampleAfterValue": "100003",620 "UMask": "0x4"621 },622 {623 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",624 "Counter": "0,1,2,3",625 "EventCode": "0xb2",626 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",627 "SampleAfterValue": "2000003",628 "UMask": "0x1"629 },630 {631 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",632 "Counter": "0,1,2,3",633 "Errata": "HSD62, HSD61, HSM63",634 "EventCode": "0x60",635 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",636 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",637 "SampleAfterValue": "2000003",638 "UMask": "0x8"639 },640 {641 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",642 "Counter": "0,1,2,3",643 "CounterMask": "1",644 "Errata": "HSD62, HSD61, HSM63",645 "EventCode": "0x60",646 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",647 "SampleAfterValue": "2000003",648 "UMask": "0x8"649 },650 {651 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",652 "Counter": "0,1,2,3",653 "CounterMask": "1",654 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",655 "EventCode": "0x60",656 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",657 "SampleAfterValue": "2000003",658 "UMask": "0x1"659 },660 {661 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",662 "Counter": "0,1,2,3",663 "CounterMask": "1",664 "Errata": "HSD62, HSD61, HSM63",665 "EventCode": "0x60",666 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",667 "SampleAfterValue": "2000003",668 "UMask": "0x4"669 },670 {671 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",672 "Counter": "0,1,2,3",673 "Errata": "HSD62, HSD61, HSM63",674 "EventCode": "0x60",675 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",676 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",677 "SampleAfterValue": "2000003",678 "UMask": "0x2"679 },680 {681 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",682 "Counter": "0,1,2,3",683 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",684 "EventCode": "0x60",685 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",686 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",687 "SampleAfterValue": "2000003",688 "UMask": "0x1"689 },690 {691 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",692 "Counter": "0,1,2,3",693 "CounterMask": "6",694 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",695 "EventCode": "0x60",696 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",697 "SampleAfterValue": "2000003",698 "UMask": "0x1"699 },700 {701 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",702 "Counter": "0,1,2,3",703 "Errata": "HSD62, HSD61, HSM63",704 "EventCode": "0x60",705 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",706 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",707 "SampleAfterValue": "2000003",708 "UMask": "0x4"709 },710 {711 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",712 "Counter": "0,1,2,3",713 "EventCode": "0xB7, 0xBB",714 "EventName": "OFFCORE_RESPONSE",715 "SampleAfterValue": "100003",716 "UMask": "0x1"717 },718 {719 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",720 "Counter": "0,1,2,3",721 "EventCode": "0xB7, 0xBB",722 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",723 "MSRIndex": "0x1a6,0x1a7",724 "MSRValue": "0x4003C0244",725 "SampleAfterValue": "100003",726 "UMask": "0x1"727 },728 {729 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",730 "Counter": "0,1,2,3",731 "EventCode": "0xB7, 0xBB",732 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",733 "MSRIndex": "0x1a6,0x1a7",734 "MSRValue": "0x10003C0091",735 "SampleAfterValue": "100003",736 "UMask": "0x1"737 },738 {739 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",740 "Counter": "0,1,2,3",741 "EventCode": "0xB7, 0xBB",742 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",743 "MSRIndex": "0x1a6,0x1a7",744 "MSRValue": "0x4003C0091",745 "SampleAfterValue": "100003",746 "UMask": "0x1"747 },748 {749 "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",750 "Counter": "0,1,2,3",751 "EventCode": "0xB7, 0xBB",752 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",753 "MSRIndex": "0x1a6,0x1a7",754 "MSRValue": "0x10003C07F7",755 "SampleAfterValue": "100003",756 "UMask": "0x1"757 },758 {759 "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",760 "Counter": "0,1,2,3",761 "EventCode": "0xB7, 0xBB",762 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",763 "MSRIndex": "0x1a6,0x1a7",764 "MSRValue": "0x4003C07F7",765 "SampleAfterValue": "100003",766 "UMask": "0x1"767 },768 {769 "BriefDescription": "Counts all requests hit in the L3",770 "Counter": "0,1,2,3",771 "EventCode": "0xB7, 0xBB",772 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",773 "MSRIndex": "0x1a6,0x1a7",774 "MSRValue": "0x3F803C8FFF",775 "SampleAfterValue": "100003",776 "UMask": "0x1"777 },778 {779 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",780 "Counter": "0,1,2,3",781 "EventCode": "0xB7, 0xBB",782 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",783 "MSRIndex": "0x1a6,0x1a7",784 "MSRValue": "0x10003C0122",785 "SampleAfterValue": "100003",786 "UMask": "0x1"787 },788 {789 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",790 "Counter": "0,1,2,3",791 "EventCode": "0xB7, 0xBB",792 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",793 "MSRIndex": "0x1a6,0x1a7",794 "MSRValue": "0x4003C0122",795 "SampleAfterValue": "100003",796 "UMask": "0x1"797 },798 {799 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",800 "Counter": "0,1,2,3",801 "EventCode": "0xB7, 0xBB",802 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",803 "MSRIndex": "0x1a6,0x1a7",804 "MSRValue": "0x10003C0004",805 "SampleAfterValue": "100003",806 "UMask": "0x1"807 },808 {809 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",810 "Counter": "0,1,2,3",811 "EventCode": "0xB7, 0xBB",812 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",813 "MSRIndex": "0x1a6,0x1a7",814 "MSRValue": "0x4003C0004",815 "SampleAfterValue": "100003",816 "UMask": "0x1"817 },818 {819 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",820 "Counter": "0,1,2,3",821 "EventCode": "0xB7, 0xBB",822 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",823 "MSRIndex": "0x1a6,0x1a7",824 "MSRValue": "0x10003C0001",825 "SampleAfterValue": "100003",826 "UMask": "0x1"827 },828 {829 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",830 "Counter": "0,1,2,3",831 "EventCode": "0xB7, 0xBB",832 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",833 "MSRIndex": "0x1a6,0x1a7",834 "MSRValue": "0x4003C0001",835 "SampleAfterValue": "100003",836 "UMask": "0x1"837 },838 {839 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",840 "Counter": "0,1,2,3",841 "EventCode": "0xB7, 0xBB",842 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",843 "MSRIndex": "0x1a6,0x1a7",844 "MSRValue": "0x10003C0002",845 "SampleAfterValue": "100003",846 "UMask": "0x1"847 },848 {849 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",850 "Counter": "0,1,2,3",851 "EventCode": "0xB7, 0xBB",852 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",853 "MSRIndex": "0x1a6,0x1a7",854 "MSRValue": "0x4003C0002",855 "SampleAfterValue": "100003",856 "UMask": "0x1"857 },858 {859 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",860 "Counter": "0,1,2,3",861 "EventCode": "0xB7, 0xBB",862 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",863 "MSRIndex": "0x1a6,0x1a7",864 "MSRValue": "0x3F803C0040",865 "SampleAfterValue": "100003",866 "UMask": "0x1"867 },868 {869 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",870 "Counter": "0,1,2,3",871 "EventCode": "0xB7, 0xBB",872 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",873 "MSRIndex": "0x1a6,0x1a7",874 "MSRValue": "0x3F803C0010",875 "SampleAfterValue": "100003",876 "UMask": "0x1"877 },878 {879 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",880 "Counter": "0,1,2,3",881 "EventCode": "0xB7, 0xBB",882 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",883 "MSRIndex": "0x1a6,0x1a7",884 "MSRValue": "0x3F803C0020",885 "SampleAfterValue": "100003",886 "UMask": "0x1"887 },888 {889 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",890 "Counter": "0,1,2,3",891 "EventCode": "0xB7, 0xBB",892 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",893 "MSRIndex": "0x1a6,0x1a7",894 "MSRValue": "0x3F803C0200",895 "SampleAfterValue": "100003",896 "UMask": "0x1"897 },898 {899 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",900 "Counter": "0,1,2,3",901 "EventCode": "0xB7, 0xBB",902 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",903 "MSRIndex": "0x1a6,0x1a7",904 "MSRValue": "0x3F803C0080",905 "SampleAfterValue": "100003",906 "UMask": "0x1"907 },908 {909 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",910 "Counter": "0,1,2,3",911 "EventCode": "0xB7, 0xBB",912 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",913 "MSRIndex": "0x1a6,0x1a7",914 "MSRValue": "0x3F803C0100",915 "SampleAfterValue": "100003",916 "UMask": "0x1"917 },918 {919 "BriefDescription": "Split locks in SQ",920 "Counter": "0,1,2,3",921 "EventCode": "0xf4",922 "EventName": "SQ_MISC.SPLIT_LOCK",923 "SampleAfterValue": "100003",924 "UMask": "0x10"925 }926]927