40 lines · json
1[2 {3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0",4 "Counter": "0,1,2,3",5 "EventCode": "0x5C",6 "EventName": "CPL_CYCLES.RING0",7 "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",8 "SampleAfterValue": "2000003",9 "UMask": "0x1"10 },11 {12 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",13 "Counter": "0,1,2,3",14 "CounterMask": "1",15 "EdgeDetect": "1",16 "EventCode": "0x5C",17 "EventName": "CPL_CYCLES.RING0_TRANS",18 "SampleAfterValue": "100003",19 "UMask": "0x1"20 },21 {22 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",23 "Counter": "0,1,2,3",24 "EventCode": "0x5C",25 "EventName": "CPL_CYCLES.RING123",26 "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",27 "SampleAfterValue": "2000003",28 "UMask": "0x2"29 },30 {31 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",32 "Counter": "0,1,2,3",33 "EventCode": "0x63",34 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",35 "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",36 "SampleAfterValue": "2000003",37 "UMask": "0x1"38 }39]40