960 lines · json
1[2 {3 "BriefDescription": "L1D data line replacements",4 "Counter": "0,1,2,3",5 "EventCode": "0x51",6 "EventName": "L1D.REPLACEMENT",7 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",8 "SampleAfterValue": "2000003",9 "UMask": "0x1"10 },11 {12 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",13 "Counter": "0,1,2,3",14 "CounterMask": "1",15 "EventCode": "0x48",16 "EventName": "L1D_PEND_MISS.FB_FULL",17 "SampleAfterValue": "2000003",18 "UMask": "0x2"19 },20 {21 "BriefDescription": "L1D miss outstanding duration in cycles",22 "Counter": "2",23 "EventCode": "0x48",24 "EventName": "L1D_PEND_MISS.PENDING",25 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",26 "SampleAfterValue": "2000003",27 "UMask": "0x1"28 },29 {30 "BriefDescription": "Cycles with L1D load Misses outstanding.",31 "Counter": "2",32 "CounterMask": "1",33 "EventCode": "0x48",34 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",35 "SampleAfterValue": "2000003",36 "UMask": "0x1"37 },38 {39 "AnyThread": "1",40 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",41 "Counter": "2",42 "CounterMask": "1",43 "EventCode": "0x48",44 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",45 "SampleAfterValue": "2000003",46 "UMask": "0x1"47 },48 {49 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",50 "Counter": "0,1,2,3",51 "EventCode": "0x48",52 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",53 "SampleAfterValue": "2000003",54 "UMask": "0x2"55 },56 {57 "BriefDescription": "Not rejected writebacks that hit L2 cache",58 "Counter": "0,1,2,3",59 "EventCode": "0x27",60 "EventName": "L2_DEMAND_RQSTS.WB_HIT",61 "PublicDescription": "Not rejected writebacks that hit L2 cache.",62 "SampleAfterValue": "200003",63 "UMask": "0x50"64 },65 {66 "BriefDescription": "L2 cache lines filling L2",67 "Counter": "0,1,2,3",68 "EventCode": "0xF1",69 "EventName": "L2_LINES_IN.ALL",70 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",71 "SampleAfterValue": "100003",72 "UMask": "0x7"73 },74 {75 "BriefDescription": "L2 cache lines in E state filling L2",76 "Counter": "0,1,2,3",77 "EventCode": "0xF1",78 "EventName": "L2_LINES_IN.E",79 "PublicDescription": "L2 cache lines in E state filling L2.",80 "SampleAfterValue": "100003",81 "UMask": "0x4"82 },83 {84 "BriefDescription": "L2 cache lines in I state filling L2",85 "Counter": "0,1,2,3",86 "EventCode": "0xF1",87 "EventName": "L2_LINES_IN.I",88 "PublicDescription": "L2 cache lines in I state filling L2.",89 "SampleAfterValue": "100003",90 "UMask": "0x1"91 },92 {93 "BriefDescription": "L2 cache lines in S state filling L2",94 "Counter": "0,1,2,3",95 "EventCode": "0xF1",96 "EventName": "L2_LINES_IN.S",97 "PublicDescription": "L2 cache lines in S state filling L2.",98 "SampleAfterValue": "100003",99 "UMask": "0x2"100 },101 {102 "BriefDescription": "Clean L2 cache lines evicted by demand",103 "Counter": "0,1,2,3",104 "EventCode": "0xF2",105 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",106 "PublicDescription": "Clean L2 cache lines evicted by demand.",107 "SampleAfterValue": "100003",108 "UMask": "0x5"109 },110 {111 "BriefDescription": "Dirty L2 cache lines evicted by demand",112 "Counter": "0,1,2,3",113 "EventCode": "0xF2",114 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",115 "PublicDescription": "Dirty L2 cache lines evicted by demand.",116 "SampleAfterValue": "100003",117 "UMask": "0x6"118 },119 {120 "BriefDescription": "L2 code requests",121 "Counter": "0,1,2,3",122 "EventCode": "0x24",123 "EventName": "L2_RQSTS.ALL_CODE_RD",124 "PublicDescription": "Counts all L2 code requests.",125 "SampleAfterValue": "200003",126 "UMask": "0xe4"127 },128 {129 "BriefDescription": "Demand Data Read requests",130 "Counter": "0,1,2,3",131 "Errata": "HSD78, HSM80",132 "EventCode": "0x24",133 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",134 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",135 "SampleAfterValue": "200003",136 "UMask": "0xe1"137 },138 {139 "BriefDescription": "Demand requests that miss L2 cache",140 "Counter": "0,1,2,3",141 "Errata": "HSD78, HSM80",142 "EventCode": "0x24",143 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",144 "PublicDescription": "Demand requests that miss L2 cache.",145 "SampleAfterValue": "200003",146 "UMask": "0x27"147 },148 {149 "BriefDescription": "Demand requests to L2 cache",150 "Counter": "0,1,2,3",151 "Errata": "HSD78, HSM80",152 "EventCode": "0x24",153 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",154 "PublicDescription": "Demand requests to L2 cache.",155 "SampleAfterValue": "200003",156 "UMask": "0xe7"157 },158 {159 "BriefDescription": "Requests from L2 hardware prefetchers",160 "Counter": "0,1,2,3",161 "EventCode": "0x24",162 "EventName": "L2_RQSTS.ALL_PF",163 "PublicDescription": "Counts all L2 HW prefetcher requests.",164 "SampleAfterValue": "200003",165 "UMask": "0xf8"166 },167 {168 "BriefDescription": "RFO requests to L2 cache",169 "Counter": "0,1,2,3",170 "EventCode": "0x24",171 "EventName": "L2_RQSTS.ALL_RFO",172 "PublicDescription": "Counts all L2 store RFO requests.",173 "SampleAfterValue": "200003",174 "UMask": "0xe2"175 },176 {177 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",178 "Counter": "0,1,2,3",179 "EventCode": "0x24",180 "EventName": "L2_RQSTS.CODE_RD_HIT",181 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",182 "SampleAfterValue": "200003",183 "UMask": "0xc4"184 },185 {186 "BriefDescription": "L2 cache misses when fetching instructions",187 "Counter": "0,1,2,3",188 "EventCode": "0x24",189 "EventName": "L2_RQSTS.CODE_RD_MISS",190 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",191 "SampleAfterValue": "200003",192 "UMask": "0x24"193 },194 {195 "BriefDescription": "Demand Data Read requests that hit L2 cache",196 "Counter": "0,1,2,3",197 "Errata": "HSD78, HSM80",198 "EventCode": "0x24",199 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",200 "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",201 "SampleAfterValue": "200003",202 "UMask": "0xc1"203 },204 {205 "BriefDescription": "Demand Data Read miss L2, no rejects",206 "Counter": "0,1,2,3",207 "Errata": "HSD78, HSM80",208 "EventCode": "0x24",209 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",210 "PublicDescription": "Demand data read requests that missed L2, no rejects.",211 "SampleAfterValue": "200003",212 "UMask": "0x21"213 },214 {215 "BriefDescription": "L2 prefetch requests that hit L2 cache",216 "Counter": "0,1,2,3",217 "EventCode": "0x24",218 "EventName": "L2_RQSTS.L2_PF_HIT",219 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",220 "SampleAfterValue": "200003",221 "UMask": "0xd0"222 },223 {224 "BriefDescription": "L2 prefetch requests that miss L2 cache",225 "Counter": "0,1,2,3",226 "EventCode": "0x24",227 "EventName": "L2_RQSTS.L2_PF_MISS",228 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",229 "SampleAfterValue": "200003",230 "UMask": "0x30"231 },232 {233 "BriefDescription": "All requests that miss L2 cache",234 "Counter": "0,1,2,3",235 "Errata": "HSD78, HSM80",236 "EventCode": "0x24",237 "EventName": "L2_RQSTS.MISS",238 "PublicDescription": "All requests that missed L2.",239 "SampleAfterValue": "200003",240 "UMask": "0x3f"241 },242 {243 "BriefDescription": "All L2 requests",244 "Counter": "0,1,2,3",245 "Errata": "HSD78, HSM80",246 "EventCode": "0x24",247 "EventName": "L2_RQSTS.REFERENCES",248 "PublicDescription": "All requests to L2 cache.",249 "SampleAfterValue": "200003",250 "UMask": "0xff"251 },252 {253 "BriefDescription": "RFO requests that hit L2 cache",254 "Counter": "0,1,2,3",255 "EventCode": "0x24",256 "EventName": "L2_RQSTS.RFO_HIT",257 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",258 "SampleAfterValue": "200003",259 "UMask": "0xc2"260 },261 {262 "BriefDescription": "RFO requests that miss L2 cache",263 "Counter": "0,1,2,3",264 "EventCode": "0x24",265 "EventName": "L2_RQSTS.RFO_MISS",266 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",267 "SampleAfterValue": "200003",268 "UMask": "0x22"269 },270 {271 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",272 "Counter": "0,1,2,3",273 "EventCode": "0xf0",274 "EventName": "L2_TRANS.ALL_PF",275 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",276 "SampleAfterValue": "200003",277 "UMask": "0x8"278 },279 {280 "BriefDescription": "Transactions accessing L2 pipe",281 "Counter": "0,1,2,3",282 "EventCode": "0xf0",283 "EventName": "L2_TRANS.ALL_REQUESTS",284 "PublicDescription": "Transactions accessing L2 pipe.",285 "SampleAfterValue": "200003",286 "UMask": "0x80"287 },288 {289 "BriefDescription": "L2 cache accesses when fetching instructions",290 "Counter": "0,1,2,3",291 "EventCode": "0xf0",292 "EventName": "L2_TRANS.CODE_RD",293 "PublicDescription": "L2 cache accesses when fetching instructions.",294 "SampleAfterValue": "200003",295 "UMask": "0x4"296 },297 {298 "BriefDescription": "Demand Data Read requests that access L2 cache",299 "Counter": "0,1,2,3",300 "EventCode": "0xf0",301 "EventName": "L2_TRANS.DEMAND_DATA_RD",302 "PublicDescription": "Demand data read requests that access L2 cache.",303 "SampleAfterValue": "200003",304 "UMask": "0x1"305 },306 {307 "BriefDescription": "L1D writebacks that access L2 cache",308 "Counter": "0,1,2,3",309 "EventCode": "0xf0",310 "EventName": "L2_TRANS.L1D_WB",311 "PublicDescription": "L1D writebacks that access L2 cache.",312 "SampleAfterValue": "200003",313 "UMask": "0x10"314 },315 {316 "BriefDescription": "L2 fill requests that access L2 cache",317 "Counter": "0,1,2,3",318 "EventCode": "0xf0",319 "EventName": "L2_TRANS.L2_FILL",320 "PublicDescription": "L2 fill requests that access L2 cache.",321 "SampleAfterValue": "200003",322 "UMask": "0x20"323 },324 {325 "BriefDescription": "L2 writebacks that access L2 cache",326 "Counter": "0,1,2,3",327 "EventCode": "0xf0",328 "EventName": "L2_TRANS.L2_WB",329 "PublicDescription": "L2 writebacks that access L2 cache.",330 "SampleAfterValue": "200003",331 "UMask": "0x40"332 },333 {334 "BriefDescription": "RFO requests that access L2 cache",335 "Counter": "0,1,2,3",336 "EventCode": "0xf0",337 "EventName": "L2_TRANS.RFO",338 "PublicDescription": "RFO requests that access L2 cache.",339 "SampleAfterValue": "200003",340 "UMask": "0x2"341 },342 {343 "BriefDescription": "Cycles when L1D is locked",344 "Counter": "0,1,2,3",345 "EventCode": "0x63",346 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",347 "PublicDescription": "Cycles in which the L1D is locked.",348 "SampleAfterValue": "2000003",349 "UMask": "0x2"350 },351 {352 "BriefDescription": "Core-originated cacheable demand requests missed L3",353 "Counter": "0,1,2,3",354 "EventCode": "0x2E",355 "EventName": "LONGEST_LAT_CACHE.MISS",356 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",357 "SampleAfterValue": "100003",358 "UMask": "0x41"359 },360 {361 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",362 "Counter": "0,1,2,3",363 "EventCode": "0x2E",364 "EventName": "LONGEST_LAT_CACHE.REFERENCE",365 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",366 "SampleAfterValue": "100003",367 "UMask": "0x4f"368 },369 {370 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",371 "Counter": "0,1,2,3",372 "Data_LA": "1",373 "Errata": "HSD29, HSD25, HSM26, HSM30",374 "EventCode": "0xD2",375 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",376 "PEBS": "1",377 "SampleAfterValue": "20011",378 "UMask": "0x2"379 },380 {381 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",382 "Counter": "0,1,2,3",383 "Data_LA": "1",384 "Errata": "HSD29, HSD25, HSM26, HSM30",385 "EventCode": "0xD2",386 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",387 "PEBS": "1",388 "SampleAfterValue": "20011",389 "UMask": "0x4"390 },391 {392 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",393 "Counter": "0,1,2,3",394 "Data_LA": "1",395 "Errata": "HSD29, HSD25, HSM26, HSM30",396 "EventCode": "0xD2",397 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",398 "PEBS": "1",399 "SampleAfterValue": "20011",400 "UMask": "0x1"401 },402 {403 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",404 "Counter": "0,1,2,3",405 "Data_LA": "1",406 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",407 "EventCode": "0xD2",408 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",409 "PEBS": "1",410 "SampleAfterValue": "100003",411 "UMask": "0x8"412 },413 {414 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",415 "Counter": "0,1,2,3",416 "Data_LA": "1",417 "Errata": "HSD74, HSD29, HSD25, HSM30",418 "EventCode": "0xD3",419 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",420 "PEBS": "1",421 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",422 "SampleAfterValue": "100003",423 "UMask": "0x1"424 },425 {426 "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",427 "Counter": "0,1,2,3",428 "Data_LA": "1",429 "Errata": "HSD29, HSM30",430 "EventCode": "0xD3",431 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",432 "PEBS": "1",433 "SampleAfterValue": "100003",434 "UMask": "0x4"435 },436 {437 "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",438 "Counter": "0,1,2,3",439 "Data_LA": "1",440 "Errata": "HSM30",441 "EventCode": "0xD3",442 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",443 "PEBS": "1",444 "SampleAfterValue": "100003",445 "UMask": "0x20"446 },447 {448 "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",449 "Counter": "0,1,2,3",450 "Data_LA": "1",451 "Errata": "HSM30",452 "EventCode": "0xD3",453 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",454 "PEBS": "1",455 "SampleAfterValue": "100003",456 "UMask": "0x10"457 },458 {459 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",460 "Counter": "0,1,2,3",461 "Data_LA": "1",462 "Errata": "HSM30",463 "EventCode": "0xD1",464 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",465 "PEBS": "1",466 "SampleAfterValue": "100003",467 "UMask": "0x40"468 },469 {470 "BriefDescription": "Retired load uops with L1 cache hits as data sources.",471 "Counter": "0,1,2,3",472 "Data_LA": "1",473 "Errata": "HSD29, HSM30",474 "EventCode": "0xD1",475 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",476 "PEBS": "1",477 "SampleAfterValue": "2000003",478 "UMask": "0x1"479 },480 {481 "BriefDescription": "Retired load uops misses in L1 cache as data sources.",482 "Counter": "0,1,2,3",483 "Data_LA": "1",484 "Errata": "HSM30",485 "EventCode": "0xD1",486 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",487 "PEBS": "1",488 "PublicDescription": "Retired load uops missed L1 cache as data sources.",489 "SampleAfterValue": "100003",490 "UMask": "0x8"491 },492 {493 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",494 "Counter": "0,1,2,3",495 "Data_LA": "1",496 "Errata": "HSD76, HSD29, HSM30",497 "EventCode": "0xD1",498 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",499 "PEBS": "1",500 "SampleAfterValue": "100003",501 "UMask": "0x2"502 },503 {504 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",505 "Counter": "0,1,2,3",506 "Data_LA": "1",507 "Errata": "HSD29, HSM30",508 "EventCode": "0xD1",509 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",510 "PEBS": "1",511 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",512 "SampleAfterValue": "50021",513 "UMask": "0x10"514 },515 {516 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",517 "Counter": "0,1,2,3",518 "Data_LA": "1",519 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",520 "EventCode": "0xD1",521 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",522 "PEBS": "1",523 "PublicDescription": "Retired load uops with L3 cache hits as data sources.",524 "SampleAfterValue": "50021",525 "UMask": "0x4"526 },527 {528 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",529 "Counter": "0,1,2,3",530 "Data_LA": "1",531 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",532 "EventCode": "0xD1",533 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",534 "PEBS": "1",535 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",536 "SampleAfterValue": "100003",537 "UMask": "0x20"538 },539 {540 "BriefDescription": "Retired load uops.",541 "Counter": "0,1,2,3",542 "Data_LA": "1",543 "Errata": "HSD29, HSM30",544 "EventCode": "0xD0",545 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",546 "PEBS": "1",547 "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",548 "SampleAfterValue": "2000003",549 "UMask": "0x81"550 },551 {552 "BriefDescription": "Retired store uops.",553 "Counter": "0,1,2,3",554 "Data_LA": "1",555 "Errata": "HSD29, HSM30",556 "EventCode": "0xD0",557 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",558 "PEBS": "1",559 "PublicDescription": "Counts all retired store uops.",560 "SampleAfterValue": "2000003",561 "UMask": "0x82"562 },563 {564 "BriefDescription": "Retired load uops with locked access.",565 "Counter": "0,1,2,3",566 "Data_LA": "1",567 "Errata": "HSD76, HSD29, HSM30",568 "EventCode": "0xD0",569 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",570 "PEBS": "1",571 "SampleAfterValue": "100003",572 "UMask": "0x21"573 },574 {575 "BriefDescription": "Retired load uops that split across a cacheline boundary.",576 "Counter": "0,1,2,3",577 "Data_LA": "1",578 "Errata": "HSD29, HSM30",579 "EventCode": "0xD0",580 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",581 "PEBS": "1",582 "SampleAfterValue": "100003",583 "UMask": "0x41"584 },585 {586 "BriefDescription": "Retired store uops that split across a cacheline boundary.",587 "Counter": "0,1,2,3",588 "Data_LA": "1",589 "Errata": "HSD29, HSM30",590 "EventCode": "0xD0",591 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",592 "PEBS": "1",593 "SampleAfterValue": "100003",594 "UMask": "0x42"595 },596 {597 "BriefDescription": "Retired load uops that miss the STLB.",598 "Counter": "0,1,2,3",599 "Data_LA": "1",600 "Errata": "HSD29, HSM30",601 "EventCode": "0xD0",602 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",603 "PEBS": "1",604 "SampleAfterValue": "100003",605 "UMask": "0x11"606 },607 {608 "BriefDescription": "Retired store uops that miss the STLB.",609 "Counter": "0,1,2,3",610 "Data_LA": "1",611 "Errata": "HSD29, HSM30",612 "EventCode": "0xD0",613 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",614 "PEBS": "1",615 "SampleAfterValue": "100003",616 "UMask": "0x12"617 },618 {619 "BriefDescription": "Demand and prefetch data reads",620 "Counter": "0,1,2,3",621 "EventCode": "0xB0",622 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",623 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",624 "SampleAfterValue": "100003",625 "UMask": "0x8"626 },627 {628 "BriefDescription": "Cacheable and noncacheable code read requests",629 "Counter": "0,1,2,3",630 "EventCode": "0xB0",631 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",632 "PublicDescription": "Demand code read requests sent to uncore.",633 "SampleAfterValue": "100003",634 "UMask": "0x2"635 },636 {637 "BriefDescription": "Demand Data Read requests sent to uncore",638 "Counter": "0,1,2,3",639 "Errata": "HSD78, HSM80",640 "EventCode": "0xb0",641 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",642 "PublicDescription": "Demand data read requests sent to uncore.",643 "SampleAfterValue": "100003",644 "UMask": "0x1"645 },646 {647 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",648 "Counter": "0,1,2,3",649 "EventCode": "0xB0",650 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",651 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",652 "SampleAfterValue": "100003",653 "UMask": "0x4"654 },655 {656 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",657 "Counter": "0,1,2,3",658 "EventCode": "0xb2",659 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",660 "SampleAfterValue": "2000003",661 "UMask": "0x1"662 },663 {664 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",665 "Counter": "0,1,2,3",666 "Errata": "HSD62, HSD61, HSM63",667 "EventCode": "0x60",668 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",669 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",670 "SampleAfterValue": "2000003",671 "UMask": "0x8"672 },673 {674 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",675 "Counter": "0,1,2,3",676 "CounterMask": "1",677 "Errata": "HSD62, HSD61, HSM63",678 "EventCode": "0x60",679 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",680 "SampleAfterValue": "2000003",681 "UMask": "0x8"682 },683 {684 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",685 "Counter": "0,1,2,3",686 "CounterMask": "1",687 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",688 "EventCode": "0x60",689 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",690 "SampleAfterValue": "2000003",691 "UMask": "0x1"692 },693 {694 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",695 "Counter": "0,1,2,3",696 "CounterMask": "1",697 "Errata": "HSD62, HSD61, HSM63",698 "EventCode": "0x60",699 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",700 "SampleAfterValue": "2000003",701 "UMask": "0x4"702 },703 {704 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",705 "Counter": "0,1,2,3",706 "Errata": "HSD62, HSD61, HSM63",707 "EventCode": "0x60",708 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",709 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",710 "SampleAfterValue": "2000003",711 "UMask": "0x2"712 },713 {714 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",715 "Counter": "0,1,2,3",716 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",717 "EventCode": "0x60",718 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",719 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",720 "SampleAfterValue": "2000003",721 "UMask": "0x1"722 },723 {724 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",725 "Counter": "0,1,2,3",726 "CounterMask": "6",727 "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",728 "EventCode": "0x60",729 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",730 "SampleAfterValue": "2000003",731 "UMask": "0x1"732 },733 {734 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",735 "Counter": "0,1,2,3",736 "Errata": "HSD62, HSD61, HSM63",737 "EventCode": "0x60",738 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",739 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",740 "SampleAfterValue": "2000003",741 "UMask": "0x4"742 },743 {744 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",745 "Counter": "0,1,2,3",746 "EventCode": "0xB7, 0xBB",747 "EventName": "OFFCORE_RESPONSE",748 "SampleAfterValue": "100003",749 "UMask": "0x1"750 },751 {752 "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",753 "Counter": "0,1,2,3",754 "EventCode": "0xB7, 0xBB",755 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",756 "MSRIndex": "0x1a6,0x1a7",757 "MSRValue": "0x4003C0244",758 "SampleAfterValue": "100003",759 "UMask": "0x1"760 },761 {762 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",763 "Counter": "0,1,2,3",764 "EventCode": "0xB7, 0xBB",765 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",766 "MSRIndex": "0x1a6,0x1a7",767 "MSRValue": "0x10003C0091",768 "SampleAfterValue": "100003",769 "UMask": "0x1"770 },771 {772 "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",773 "Counter": "0,1,2,3",774 "EventCode": "0xB7, 0xBB",775 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",776 "MSRIndex": "0x1a6,0x1a7",777 "MSRValue": "0x4003C0091",778 "SampleAfterValue": "100003",779 "UMask": "0x1"780 },781 {782 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",783 "Counter": "0,1,2,3",784 "EventCode": "0xB7, 0xBB",785 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",786 "MSRIndex": "0x1a6,0x1a7",787 "MSRValue": "0x10003C07F7",788 "SampleAfterValue": "100003",789 "UMask": "0x1"790 },791 {792 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",793 "Counter": "0,1,2,3",794 "EventCode": "0xB7, 0xBB",795 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",796 "MSRIndex": "0x1a6,0x1a7",797 "MSRValue": "0x4003C07F7",798 "SampleAfterValue": "100003",799 "UMask": "0x1"800 },801 {802 "BriefDescription": "Counts all requests hit in the L3",803 "Counter": "0,1,2,3",804 "EventCode": "0xB7, 0xBB",805 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",806 "MSRIndex": "0x1a6,0x1a7",807 "MSRValue": "0x3F803C8FFF",808 "SampleAfterValue": "100003",809 "UMask": "0x1"810 },811 {812 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",813 "Counter": "0,1,2,3",814 "EventCode": "0xB7, 0xBB",815 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",816 "MSRIndex": "0x1a6,0x1a7",817 "MSRValue": "0x10003C0122",818 "SampleAfterValue": "100003",819 "UMask": "0x1"820 },821 {822 "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",823 "Counter": "0,1,2,3",824 "EventCode": "0xB7, 0xBB",825 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",826 "MSRIndex": "0x1a6,0x1a7",827 "MSRValue": "0x4003C0122",828 "SampleAfterValue": "100003",829 "UMask": "0x1"830 },831 {832 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",833 "Counter": "0,1,2,3",834 "EventCode": "0xB7, 0xBB",835 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",836 "MSRIndex": "0x1a6,0x1a7",837 "MSRValue": "0x10003C0004",838 "SampleAfterValue": "100003",839 "UMask": "0x1"840 },841 {842 "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",843 "Counter": "0,1,2,3",844 "EventCode": "0xB7, 0xBB",845 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",846 "MSRIndex": "0x1a6,0x1a7",847 "MSRValue": "0x4003C0004",848 "SampleAfterValue": "100003",849 "UMask": "0x1"850 },851 {852 "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",853 "Counter": "0,1,2,3",854 "EventCode": "0xB7, 0xBB",855 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",856 "MSRIndex": "0x1a6,0x1a7",857 "MSRValue": "0x10003C0001",858 "SampleAfterValue": "100003",859 "UMask": "0x1"860 },861 {862 "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",863 "Counter": "0,1,2,3",864 "EventCode": "0xB7, 0xBB",865 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",866 "MSRIndex": "0x1a6,0x1a7",867 "MSRValue": "0x4003C0001",868 "SampleAfterValue": "100003",869 "UMask": "0x1"870 },871 {872 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",873 "Counter": "0,1,2,3",874 "EventCode": "0xB7, 0xBB",875 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",876 "MSRIndex": "0x1a6,0x1a7",877 "MSRValue": "0x10003C0002",878 "SampleAfterValue": "100003",879 "UMask": "0x1"880 },881 {882 "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",883 "Counter": "0,1,2,3",884 "EventCode": "0xB7, 0xBB",885 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",886 "MSRIndex": "0x1a6,0x1a7",887 "MSRValue": "0x4003C0002",888 "SampleAfterValue": "100003",889 "UMask": "0x1"890 },891 {892 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",893 "Counter": "0,1,2,3",894 "EventCode": "0xB7, 0xBB",895 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",896 "MSRIndex": "0x1a6,0x1a7",897 "MSRValue": "0x3F803C0040",898 "SampleAfterValue": "100003",899 "UMask": "0x1"900 },901 {902 "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",903 "Counter": "0,1,2,3",904 "EventCode": "0xB7, 0xBB",905 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",906 "MSRIndex": "0x1a6,0x1a7",907 "MSRValue": "0x3F803C0010",908 "SampleAfterValue": "100003",909 "UMask": "0x1"910 },911 {912 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",913 "Counter": "0,1,2,3",914 "EventCode": "0xB7, 0xBB",915 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",916 "MSRIndex": "0x1a6,0x1a7",917 "MSRValue": "0x3F803C0020",918 "SampleAfterValue": "100003",919 "UMask": "0x1"920 },921 {922 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",923 "Counter": "0,1,2,3",924 "EventCode": "0xB7, 0xBB",925 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",926 "MSRIndex": "0x1a6,0x1a7",927 "MSRValue": "0x3F803C0200",928 "SampleAfterValue": "100003",929 "UMask": "0x1"930 },931 {932 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",933 "Counter": "0,1,2,3",934 "EventCode": "0xB7, 0xBB",935 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",936 "MSRIndex": "0x1a6,0x1a7",937 "MSRValue": "0x3F803C0080",938 "SampleAfterValue": "100003",939 "UMask": "0x1"940 },941 {942 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",943 "Counter": "0,1,2,3",944 "EventCode": "0xB7, 0xBB",945 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",946 "MSRIndex": "0x1a6,0x1a7",947 "MSRValue": "0x3F803C0100",948 "SampleAfterValue": "100003",949 "UMask": "0x1"950 },951 {952 "BriefDescription": "Split locks in SQ",953 "Counter": "0,1,2,3",954 "EventCode": "0xf4",955 "EventName": "SQ_MISC.SPLIT_LOCK",956 "SampleAfterValue": "100003",957 "UMask": "0x10"958 }959]960