270 lines · json
1[2 {3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",4 "Counter": "0,1,2,3",5 "EventCode": "0x28",6 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",7 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",8 "SampleAfterValue": "200003",9 "UMask": "0x7"10 },11 {12 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",13 "Counter": "0,1,2,3",14 "EventCode": "0x28",15 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",16 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",17 "SampleAfterValue": "200003",18 "UMask": "0x18"19 },20 {21 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",22 "Counter": "0,1,2,3",23 "EventCode": "0x28",24 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",25 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",26 "SampleAfterValue": "200003",27 "UMask": "0x20"28 },29 {30 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",31 "Counter": "0,1,2,3",32 "EventCode": "0xB7, 0xBB",33 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",34 "MSRIndex": "0x1a6,0x1a7",35 "MSRValue": "0x10004",36 "SampleAfterValue": "100003",37 "UMask": "0x1"38 },39 {40 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",41 "Counter": "0,1,2,3",42 "EventCode": "0xB7, 0xBB",43 "EventName": "OCR.DEMAND_CODE_RD.DRAM",44 "MSRIndex": "0x1a6,0x1a7",45 "MSRValue": "0x184000004",46 "SampleAfterValue": "100003",47 "UMask": "0x1"48 },49 {50 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",51 "Counter": "0,1,2,3",52 "EventCode": "0xB7, 0xBB",53 "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",54 "MSRIndex": "0x1a6,0x1a7",55 "MSRValue": "0x184000004",56 "SampleAfterValue": "100003",57 "UMask": "0x1"58 },59 {60 "BriefDescription": "Counts demand data reads that have any type of response.",61 "Counter": "0,1,2,3",62 "EventCode": "0xB7, 0xBB",63 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",64 "MSRIndex": "0x1a6,0x1a7",65 "MSRValue": "0x10001",66 "SampleAfterValue": "100003",67 "UMask": "0x1"68 },69 {70 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",71 "Counter": "0,1,2,3",72 "EventCode": "0xB7, 0xBB",73 "EventName": "OCR.DEMAND_DATA_RD.DRAM",74 "MSRIndex": "0x1a6,0x1a7",75 "MSRValue": "0x184000001",76 "SampleAfterValue": "100003",77 "UMask": "0x1"78 },79 {80 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",81 "Counter": "0,1,2,3",82 "EventCode": "0xB7, 0xBB",83 "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",84 "MSRIndex": "0x1a6,0x1a7",85 "MSRValue": "0x184000001",86 "SampleAfterValue": "100003",87 "UMask": "0x1"88 },89 {90 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",91 "Counter": "0,1,2,3",92 "EventCode": "0xB7, 0xBB",93 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",94 "MSRIndex": "0x1a6,0x1a7",95 "MSRValue": "0x10002",96 "SampleAfterValue": "100003",97 "UMask": "0x1"98 },99 {100 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",101 "Counter": "0,1,2,3",102 "EventCode": "0xB7, 0xBB",103 "EventName": "OCR.DEMAND_RFO.DRAM",104 "MSRIndex": "0x1a6,0x1a7",105 "MSRValue": "0x184000002",106 "SampleAfterValue": "100003",107 "UMask": "0x1"108 },109 {110 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",111 "Counter": "0,1,2,3",112 "EventCode": "0xB7, 0xBB",113 "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",114 "MSRIndex": "0x1a6,0x1a7",115 "MSRValue": "0x184000002",116 "SampleAfterValue": "100003",117 "UMask": "0x1"118 },119 {120 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",121 "Counter": "0,1,2,3",122 "EventCode": "0xB7, 0xBB",123 "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",124 "MSRIndex": "0x1a6,0x1a7",125 "MSRValue": "0x10400",126 "SampleAfterValue": "100003",127 "UMask": "0x1"128 },129 {130 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",131 "Counter": "0,1,2,3",132 "EventCode": "0xB7, 0xBB",133 "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",134 "MSRIndex": "0x1a6,0x1a7",135 "MSRValue": "0x184000400",136 "SampleAfterValue": "100003",137 "UMask": "0x1"138 },139 {140 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",141 "Counter": "0,1,2,3",142 "EventCode": "0xB7, 0xBB",143 "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",144 "MSRIndex": "0x1a6,0x1a7",145 "MSRValue": "0x184000400",146 "SampleAfterValue": "100003",147 "UMask": "0x1"148 },149 {150 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",151 "Counter": "0,1,2,3",152 "EventCode": "0xB7, 0xBB",153 "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",154 "MSRIndex": "0x1a6,0x1a7",155 "MSRValue": "0x10010",156 "SampleAfterValue": "100003",157 "UMask": "0x1"158 },159 {160 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",161 "Counter": "0,1,2,3",162 "EventCode": "0xB7, 0xBB",163 "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",164 "MSRIndex": "0x1a6,0x1a7",165 "MSRValue": "0x184000010",166 "SampleAfterValue": "100003",167 "UMask": "0x1"168 },169 {170 "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",171 "Counter": "0,1,2,3",172 "EventCode": "0xB7, 0xBB",173 "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",174 "MSRIndex": "0x1a6,0x1a7",175 "MSRValue": "0x184000010",176 "SampleAfterValue": "100003",177 "UMask": "0x1"178 },179 {180 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",181 "Counter": "0,1,2,3",182 "EventCode": "0xB7, 0xBB",183 "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",184 "MSRIndex": "0x1a6,0x1a7",185 "MSRValue": "0x10020",186 "SampleAfterValue": "100003",187 "UMask": "0x1"188 },189 {190 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",191 "Counter": "0,1,2,3",192 "EventCode": "0xB7, 0xBB",193 "EventName": "OCR.HWPF_L2_RFO.DRAM",194 "MSRIndex": "0x1a6,0x1a7",195 "MSRValue": "0x184000020",196 "SampleAfterValue": "100003",197 "UMask": "0x1"198 },199 {200 "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",201 "Counter": "0,1,2,3",202 "EventCode": "0xB7, 0xBB",203 "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",204 "MSRIndex": "0x1a6,0x1a7",205 "MSRValue": "0x184000020",206 "SampleAfterValue": "100003",207 "UMask": "0x1"208 },209 {210 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",211 "Counter": "0,1,2,3",212 "EventCode": "0xB7, 0xBB",213 "EventName": "OCR.OTHER.ANY_RESPONSE",214 "MSRIndex": "0x1a6,0x1a7",215 "MSRValue": "0x18000",216 "SampleAfterValue": "100003",217 "UMask": "0x1"218 },219 {220 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",221 "Counter": "0,1,2,3",222 "EventCode": "0xB7, 0xBB",223 "EventName": "OCR.OTHER.DRAM",224 "MSRIndex": "0x1a6,0x1a7",225 "MSRValue": "0x184008000",226 "SampleAfterValue": "100003",227 "UMask": "0x1"228 },229 {230 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",231 "Counter": "0,1,2,3",232 "EventCode": "0xB7, 0xBB",233 "EventName": "OCR.OTHER.LOCAL_DRAM",234 "MSRIndex": "0x1a6,0x1a7",235 "MSRValue": "0x184008000",236 "SampleAfterValue": "100003",237 "UMask": "0x1"238 },239 {240 "BriefDescription": "Counts streaming stores that have any type of response.",241 "Counter": "0,1,2,3",242 "EventCode": "0xB7, 0xBB",243 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",244 "MSRIndex": "0x1a6,0x1a7",245 "MSRValue": "0x10800",246 "SampleAfterValue": "100003",247 "UMask": "0x1"248 },249 {250 "BriefDescription": "Counts streaming stores that DRAM supplied the request.",251 "Counter": "0,1,2,3",252 "EventCode": "0xB7, 0xBB",253 "EventName": "OCR.STREAMING_WR.DRAM",254 "MSRIndex": "0x1a6,0x1a7",255 "MSRValue": "0x184000800",256 "SampleAfterValue": "100003",257 "UMask": "0x1"258 },259 {260 "BriefDescription": "Counts streaming stores that DRAM supplied the request.",261 "Counter": "0,1,2,3",262 "EventCode": "0xB7, 0xBB",263 "EventName": "OCR.STREAMING_WR.LOCAL_DRAM",264 "MSRIndex": "0x1a6,0x1a7",265 "MSRValue": "0x184000800",266 "SampleAfterValue": "100003",267 "UMask": "0x1"268 }269]270