286 lines · json
1[2 {3 "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",4 "Counter": "0,1,2,3",5 "EventCode": "0xE6",6 "EventName": "BACLEARS.ANY",7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",8 "SampleAfterValue": "100003",9 "UMask": "0x1f"10 },11 {12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",13 "Counter": "0,1,2,3",14 "EventCode": "0xAB",15 "EventName": "DSB2MITE_SWITCHES.COUNT",16 "PublicDescription": "Number of DSB to MITE switches.",17 "SampleAfterValue": "2000003",18 "UMask": "0x1"19 },20 {21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",22 "Counter": "0,1,2,3",23 "EventCode": "0xAB",24 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",25 "PublicDescription": "Cycles DSB to MITE switches caused delay.",26 "SampleAfterValue": "2000003",27 "UMask": "0x2"28 },29 {30 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",31 "Counter": "0,1,2,3",32 "EventCode": "0xAC",33 "EventName": "DSB_FILL.EXCEED_DSB_LINES",34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",35 "SampleAfterValue": "2000003",36 "UMask": "0x8"37 },38 {39 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",40 "Counter": "0,1,2,3",41 "EventCode": "0x80",42 "EventName": "ICACHE.HIT",43 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",44 "SampleAfterValue": "2000003",45 "UMask": "0x1"46 },47 {48 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",49 "Counter": "0,1,2,3",50 "EventCode": "0x80",51 "EventName": "ICACHE.IFETCH_STALL",52 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",53 "SampleAfterValue": "2000003",54 "UMask": "0x4"55 },56 {57 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",58 "Counter": "0,1,2,3",59 "EventCode": "0x80",60 "EventName": "ICACHE.MISSES",61 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",62 "SampleAfterValue": "200003",63 "UMask": "0x2"64 },65 {66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",67 "Counter": "0,1,2,3",68 "CounterMask": "4",69 "EventCode": "0x79",70 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",72 "SampleAfterValue": "2000003",73 "UMask": "0x18"74 },75 {76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",77 "Counter": "0,1,2,3",78 "CounterMask": "1",79 "EventCode": "0x79",80 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",82 "SampleAfterValue": "2000003",83 "UMask": "0x18"84 },85 {86 "BriefDescription": "Cycles MITE is delivering 4 Uops",87 "Counter": "0,1,2,3",88 "CounterMask": "4",89 "EventCode": "0x79",90 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",91 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",92 "SampleAfterValue": "2000003",93 "UMask": "0x24"94 },95 {96 "BriefDescription": "Cycles MITE is delivering any Uop",97 "Counter": "0,1,2,3",98 "CounterMask": "1",99 "EventCode": "0x79",100 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",101 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",102 "SampleAfterValue": "2000003",103 "UMask": "0x24"104 },105 {106 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",107 "Counter": "0,1,2,3",108 "CounterMask": "1",109 "EventCode": "0x79",110 "EventName": "IDQ.DSB_CYCLES",111 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",112 "SampleAfterValue": "2000003",113 "UMask": "0x8"114 },115 {116 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",117 "Counter": "0,1,2,3",118 "EventCode": "0x79",119 "EventName": "IDQ.DSB_UOPS",120 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",121 "SampleAfterValue": "2000003",122 "UMask": "0x8"123 },124 {125 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",126 "Counter": "0,1,2,3",127 "EventCode": "0x79",128 "EventName": "IDQ.EMPTY",129 "PublicDescription": "Counts cycles the IDQ is empty.",130 "SampleAfterValue": "2000003",131 "UMask": "0x2"132 },133 {134 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",135 "Counter": "0,1,2,3",136 "EventCode": "0x79",137 "EventName": "IDQ.MITE_ALL_UOPS",138 "PublicDescription": "Number of uops delivered to IDQ from any path.",139 "SampleAfterValue": "2000003",140 "UMask": "0x3c"141 },142 {143 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",144 "Counter": "0,1,2,3",145 "CounterMask": "1",146 "EventCode": "0x79",147 "EventName": "IDQ.MITE_CYCLES",148 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",149 "SampleAfterValue": "2000003",150 "UMask": "0x4"151 },152 {153 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",154 "Counter": "0,1,2,3",155 "EventCode": "0x79",156 "EventName": "IDQ.MITE_UOPS",157 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",158 "SampleAfterValue": "2000003",159 "UMask": "0x4"160 },161 {162 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",163 "Counter": "0,1,2,3",164 "CounterMask": "1",165 "EventCode": "0x79",166 "EventName": "IDQ.MS_CYCLES",167 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",168 "SampleAfterValue": "2000003",169 "UMask": "0x30"170 },171 {172 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",173 "Counter": "0,1,2,3",174 "CounterMask": "1",175 "EventCode": "0x79",176 "EventName": "IDQ.MS_DSB_CYCLES",177 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",178 "SampleAfterValue": "2000003",179 "UMask": "0x10"180 },181 {182 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",183 "Counter": "0,1,2,3",184 "CounterMask": "1",185 "EdgeDetect": "1",186 "EventCode": "0x79",187 "EventName": "IDQ.MS_DSB_OCCUR",188 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",189 "SampleAfterValue": "2000003",190 "UMask": "0x10"191 },192 {193 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",194 "Counter": "0,1,2,3",195 "EventCode": "0x79",196 "EventName": "IDQ.MS_DSB_UOPS",197 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",198 "SampleAfterValue": "2000003",199 "UMask": "0x10"200 },201 {202 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",203 "Counter": "0,1,2,3",204 "EventCode": "0x79",205 "EventName": "IDQ.MS_MITE_UOPS",206 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",207 "SampleAfterValue": "2000003",208 "UMask": "0x20"209 },210 {211 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",212 "Counter": "0,1,2,3",213 "CounterMask": "1",214 "EdgeDetect": "1",215 "EventCode": "0x79",216 "EventName": "IDQ.MS_SWITCHES",217 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",218 "SampleAfterValue": "2000003",219 "UMask": "0x30"220 },221 {222 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",223 "Counter": "0,1,2,3",224 "EventCode": "0x79",225 "EventName": "IDQ.MS_UOPS",226 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",227 "SampleAfterValue": "2000003",228 "UMask": "0x30"229 },230 {231 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",232 "Counter": "0,1,2,3",233 "EventCode": "0x9C",234 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",235 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",236 "SampleAfterValue": "2000003",237 "UMask": "0x1"238 },239 {240 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",241 "Counter": "0,1,2,3",242 "CounterMask": "4",243 "EventCode": "0x9C",244 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",245 "SampleAfterValue": "2000003",246 "UMask": "0x1"247 },248 {249 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",250 "Counter": "0,1,2,3",251 "CounterMask": "1",252 "EventCode": "0x9C",253 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",254 "Invert": "1",255 "SampleAfterValue": "2000003",256 "UMask": "0x1"257 },258 {259 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",260 "Counter": "0,1,2,3",261 "CounterMask": "3",262 "EventCode": "0x9C",263 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",264 "SampleAfterValue": "2000003",265 "UMask": "0x1"266 },267 {268 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",269 "Counter": "0,1,2,3",270 "CounterMask": "2",271 "EventCode": "0x9C",272 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",273 "SampleAfterValue": "2000003",274 "UMask": "0x1"275 },276 {277 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",278 "Counter": "0,1,2,3",279 "CounterMask": "1",280 "EventCode": "0x9C",281 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",282 "SampleAfterValue": "2000003",283 "UMask": "0x1"284 }285]286