1011 lines · json
1[2 {3 "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards",4 "Counter": "0,1",5 "EventCode": "0xC3",6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",7 "SampleAfterValue": "200003",8 "UMask": "0x2"9 },10 {11 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",12 "Counter": "0,1",13 "EventCode": "0xB7",14 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",15 "MSRIndex": "0x1a6,0x1a7",16 "MSRValue": "0x0181800044",17 "SampleAfterValue": "100007",18 "UMask": "0x1"19 },20 {21 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.",22 "Counter": "0,1",23 "EventCode": "0xB7",24 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",25 "MSRIndex": "0x1a6,0x1a7",26 "MSRValue": "0x0101000044",27 "SampleAfterValue": "100007",28 "UMask": "0x1"29 },30 {31 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.",32 "Counter": "0,1",33 "EventCode": "0xB7",34 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",35 "MSRIndex": "0x1a6,0x1a7",36 "MSRValue": "0x0080800044",37 "SampleAfterValue": "100007",38 "UMask": "0x1"39 },40 {41 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)",42 "Counter": "0,1",43 "EventCode": "0xB7",44 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",45 "MSRIndex": "0x1a6,0x1a7",46 "MSRValue": "0x0180600044",47 "SampleAfterValue": "100007",48 "UMask": "0x1"49 },50 {51 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",52 "Counter": "0,1",53 "EventCode": "0xB7",54 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",55 "MSRIndex": "0x1a6,0x1a7",56 "MSRValue": "0x0100400044",57 "SampleAfterValue": "100007",58 "UMask": "0x1"59 },60 {61 "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.",62 "Counter": "0,1",63 "EventCode": "0xB7",64 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",65 "MSRIndex": "0x1a6,0x1a7",66 "MSRValue": "0x0080200044",67 "SampleAfterValue": "100007",68 "UMask": "0x1"69 },70 {71 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",72 "Counter": "0,1",73 "EventCode": "0xB7",74 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",75 "MSRIndex": "0x1a6,0x1a7",76 "MSRValue": "0x0181803091",77 "SampleAfterValue": "100007",78 "UMask": "0x1"79 },80 {81 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.",82 "Counter": "0,1",83 "EventCode": "0xB7",84 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",85 "MSRIndex": "0x1a6,0x1a7",86 "MSRValue": "0x0101003091",87 "SampleAfterValue": "100007",88 "UMask": "0x1"89 },90 {91 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",92 "Counter": "0,1",93 "EventCode": "0xB7",94 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",95 "MSRIndex": "0x1a6,0x1a7",96 "MSRValue": "0x0080803091",97 "SampleAfterValue": "100007",98 "UMask": "0x1"99 },100 {101 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)",102 "Counter": "0,1",103 "EventCode": "0xB7",104 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",105 "MSRIndex": "0x1a6,0x1a7",106 "MSRValue": "0x0180603091",107 "SampleAfterValue": "100007",108 "UMask": "0x1"109 },110 {111 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",112 "Counter": "0,1",113 "EventCode": "0xB7",114 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",115 "MSRIndex": "0x1a6,0x1a7",116 "MSRValue": "0x0100403091",117 "SampleAfterValue": "100007",118 "UMask": "0x1"119 },120 {121 "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.",122 "Counter": "0,1",123 "EventCode": "0xB7",124 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",125 "MSRIndex": "0x1a6,0x1a7",126 "MSRValue": "0x0080203091",127 "SampleAfterValue": "100007",128 "UMask": "0x1"129 },130 {131 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",132 "Counter": "0,1",133 "EventCode": "0xB7",134 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",135 "MSRIndex": "0x1a6,0x1a7",136 "MSRValue": "0x0101000070",137 "SampleAfterValue": "100007",138 "UMask": "0x1"139 },140 {141 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",142 "Counter": "0,1",143 "EventCode": "0xB7",144 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",145 "MSRIndex": "0x1a6,0x1a7",146 "MSRValue": "0x0080800070",147 "SampleAfterValue": "100007",148 "UMask": "0x1"149 },150 {151 "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",152 "Counter": "0,1",153 "EventCode": "0xB7",154 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",155 "MSRIndex": "0x1a6,0x1a7",156 "MSRValue": "0x0180600070",157 "SampleAfterValue": "100007",158 "UMask": "0x1"159 },160 {161 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",162 "Counter": "0,1",163 "EventCode": "0xB7",164 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",165 "MSRIndex": "0x1a6,0x1a7",166 "MSRValue": "0x0100400070",167 "SampleAfterValue": "100007",168 "UMask": "0x1"169 },170 {171 "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",172 "Counter": "0,1",173 "EventCode": "0xB7",174 "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",175 "MSRIndex": "0x1a6,0x1a7",176 "MSRValue": "0x0080200070",177 "SampleAfterValue": "100007",178 "UMask": "0x1"179 },180 {181 "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",182 "Counter": "0,1",183 "EventCode": "0xB7",184 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",185 "MSRIndex": "0x1a6,0x1a7",186 "MSRValue": "0x01818032f7",187 "SampleAfterValue": "100007",188 "UMask": "0x1"189 },190 {191 "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.",192 "Counter": "0,1",193 "EventCode": "0xB7",194 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",195 "MSRIndex": "0x1a6,0x1a7",196 "MSRValue": "0x01010032f7",197 "SampleAfterValue": "100007",198 "UMask": "0x1"199 },200 {201 "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",202 "Counter": "0,1",203 "EventCode": "0xB7",204 "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",205 "MSRIndex": "0x1a6,0x1a7",206 "MSRValue": "0x00808032f7",207 "SampleAfterValue": "100007",208 "UMask": "0x1"209 },210 {211 "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)",212 "Counter": "0,1",213 "EventCode": "0xB7",214 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",215 "MSRIndex": "0x1a6,0x1a7",216 "MSRValue": "0x01806032f7",217 "SampleAfterValue": "100007",218 "UMask": "0x1"219 },220 {221 "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",222 "Counter": "0,1",223 "EventCode": "0xB7",224 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",225 "MSRIndex": "0x1a6,0x1a7",226 "MSRValue": "0x01004032f7",227 "SampleAfterValue": "100007",228 "UMask": "0x1"229 },230 {231 "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.",232 "Counter": "0,1",233 "EventCode": "0xB7",234 "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",235 "MSRIndex": "0x1a6,0x1a7",236 "MSRValue": "0x00802032f7",237 "SampleAfterValue": "100007",238 "UMask": "0x1"239 },240 {241 "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",242 "Counter": "0,1",243 "EventCode": "0xB7",244 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",245 "MSRIndex": "0x1a6,0x1a7",246 "MSRValue": "0x0181808000",247 "SampleAfterValue": "100007",248 "UMask": "0x1"249 },250 {251 "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",252 "Counter": "0,1",253 "EventCode": "0xB7",254 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",255 "MSRIndex": "0x1a6,0x1a7",256 "MSRValue": "0x0101008000",257 "SampleAfterValue": "100007",258 "UMask": "0x1"259 },260 {261 "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",262 "Counter": "0,1",263 "EventCode": "0xB7",264 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",265 "MSRIndex": "0x1a6,0x1a7",266 "MSRValue": "0x0080808000",267 "SampleAfterValue": "100007",268 "UMask": "0x1"269 },270 {271 "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",272 "Counter": "0,1",273 "EventCode": "0xB7",274 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",275 "MSRIndex": "0x1a6,0x1a7",276 "MSRValue": "0x0180608000",277 "SampleAfterValue": "100007",278 "UMask": "0x1"279 },280 {281 "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",282 "Counter": "0,1",283 "EventCode": "0xB7",284 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",285 "MSRIndex": "0x1a6,0x1a7",286 "MSRValue": "0x0100408000",287 "SampleAfterValue": "100007",288 "UMask": "0x1"289 },290 {291 "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",292 "Counter": "0,1",293 "EventCode": "0xB7",294 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",295 "MSRIndex": "0x1a6,0x1a7",296 "MSRValue": "0x0080208000",297 "SampleAfterValue": "100007",298 "UMask": "0x1"299 },300 {301 "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",302 "Counter": "0,1",303 "EventCode": "0xB7",304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",305 "MSRIndex": "0x1a6,0x1a7",306 "MSRValue": "0x0181800022",307 "SampleAfterValue": "100007",308 "UMask": "0x1"309 },310 {311 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.",312 "Counter": "0,1",313 "EventCode": "0xB7",314 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",315 "MSRIndex": "0x1a6,0x1a7",316 "MSRValue": "0x0101000022",317 "SampleAfterValue": "100007",318 "UMask": "0x1"319 },320 {321 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",322 "Counter": "0,1",323 "EventCode": "0xB7",324 "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",325 "MSRIndex": "0x1a6,0x1a7",326 "MSRValue": "0x0080800022",327 "SampleAfterValue": "100007",328 "UMask": "0x1"329 },330 {331 "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)",332 "Counter": "0,1",333 "EventCode": "0xB7",334 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",335 "MSRIndex": "0x1a6,0x1a7",336 "MSRValue": "0x0180600022",337 "SampleAfterValue": "100007",338 "UMask": "0x1"339 },340 {341 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",342 "Counter": "0,1",343 "EventCode": "0xB7",344 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",345 "MSRIndex": "0x1a6,0x1a7",346 "MSRValue": "0x0100400022",347 "SampleAfterValue": "100007",348 "UMask": "0x1"349 },350 {351 "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.",352 "Counter": "0,1",353 "EventCode": "0xB7",354 "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",355 "MSRIndex": "0x1a6,0x1a7",356 "MSRValue": "0x0080200022",357 "SampleAfterValue": "100007",358 "UMask": "0x1"359 },360 {361 "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",362 "Counter": "0,1",363 "EventCode": "0xB7",364 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",365 "MSRIndex": "0x1a6,0x1a7",366 "MSRValue": "0x0181800400",367 "SampleAfterValue": "100007",368 "UMask": "0x1"369 },370 {371 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",372 "Counter": "0,1",373 "EventCode": "0xB7",374 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",375 "MSRIndex": "0x1a6,0x1a7",376 "MSRValue": "0x0101000400",377 "SampleAfterValue": "100007",378 "UMask": "0x1"379 },380 {381 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",382 "Counter": "0,1",383 "EventCode": "0xB7",384 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",385 "MSRIndex": "0x1a6,0x1a7",386 "MSRValue": "0x0080800400",387 "SampleAfterValue": "100007",388 "UMask": "0x1"389 },390 {391 "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",392 "Counter": "0,1",393 "EventCode": "0xB7",394 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",395 "MSRIndex": "0x1a6,0x1a7",396 "MSRValue": "0x0180600400",397 "SampleAfterValue": "100007",398 "UMask": "0x1"399 },400 {401 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",402 "Counter": "0,1",403 "EventCode": "0xB7",404 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",405 "MSRIndex": "0x1a6,0x1a7",406 "MSRValue": "0x0100400400",407 "SampleAfterValue": "100007",408 "UMask": "0x1"409 },410 {411 "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",412 "Counter": "0,1",413 "EventCode": "0xB7",414 "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",415 "MSRIndex": "0x1a6,0x1a7",416 "MSRValue": "0x0080200400",417 "SampleAfterValue": "100007",418 "UMask": "0x1"419 },420 {421 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",422 "Counter": "0,1",423 "EventCode": "0xB7",424 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",425 "MSRIndex": "0x1a6,0x1a7",426 "MSRValue": "0x0181800004",427 "SampleAfterValue": "100007",428 "UMask": "0x1"429 },430 {431 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",432 "Counter": "0,1",433 "EventCode": "0xB7",434 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",435 "MSRIndex": "0x1a6,0x1a7",436 "MSRValue": "0x0101000004",437 "SampleAfterValue": "100007",438 "UMask": "0x1"439 },440 {441 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",442 "Counter": "0,1",443 "EventCode": "0xB7",444 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",445 "MSRIndex": "0x1a6,0x1a7",446 "MSRValue": "0x0080800004",447 "SampleAfterValue": "100007",448 "UMask": "0x1"449 },450 {451 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",452 "Counter": "0,1",453 "EventCode": "0xB7",454 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",455 "MSRIndex": "0x1a6,0x1a7",456 "MSRValue": "0x0180600004",457 "SampleAfterValue": "100007",458 "UMask": "0x1"459 },460 {461 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",462 "Counter": "0,1",463 "EventCode": "0xB7",464 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",465 "MSRIndex": "0x1a6,0x1a7",466 "MSRValue": "0x0100400004",467 "SampleAfterValue": "100007",468 "UMask": "0x1"469 },470 {471 "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",472 "Counter": "0,1",473 "EventCode": "0xB7",474 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",475 "MSRIndex": "0x1a6,0x1a7",476 "MSRValue": "0x0080200004",477 "SampleAfterValue": "100007",478 "UMask": "0x1"479 },480 {481 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",482 "Counter": "0,1",483 "EventCode": "0xB7",484 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",485 "MSRIndex": "0x1a6,0x1a7",486 "MSRValue": "0x0181800001",487 "SampleAfterValue": "100007",488 "UMask": "0x1"489 },490 {491 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",492 "Counter": "0,1",493 "EventCode": "0xB7",494 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",495 "MSRIndex": "0x1a6,0x1a7",496 "MSRValue": "0x0101000001",497 "SampleAfterValue": "100007",498 "UMask": "0x1"499 },500 {501 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",502 "Counter": "0,1",503 "EventCode": "0xB7",504 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",505 "MSRIndex": "0x1a6,0x1a7",506 "MSRValue": "0x0080800001",507 "SampleAfterValue": "100007",508 "UMask": "0x1"509 },510 {511 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",512 "Counter": "0,1",513 "EventCode": "0xB7",514 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",515 "MSRIndex": "0x1a6,0x1a7",516 "MSRValue": "0x0180600001",517 "SampleAfterValue": "100007",518 "UMask": "0x1"519 },520 {521 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",522 "Counter": "0,1",523 "EventCode": "0xB7",524 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",525 "MSRIndex": "0x1a6,0x1a7",526 "MSRValue": "0x0100400001",527 "SampleAfterValue": "100007",528 "UMask": "0x1"529 },530 {531 "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",532 "Counter": "0,1",533 "EventCode": "0xB7",534 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",535 "MSRIndex": "0x1a6,0x1a7",536 "MSRValue": "0x0080200001",537 "SampleAfterValue": "100007",538 "UMask": "0x1"539 },540 {541 "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",542 "Counter": "0,1",543 "EventCode": "0xB7",544 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",545 "MSRIndex": "0x1a6,0x1a7",546 "MSRValue": "0x0181800002",547 "SampleAfterValue": "100007",548 "UMask": "0x1"549 },550 {551 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",552 "Counter": "0,1",553 "EventCode": "0xB7",554 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",555 "MSRIndex": "0x1a6,0x1a7",556 "MSRValue": "0x0101000002",557 "SampleAfterValue": "100007",558 "UMask": "0x1"559 },560 {561 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",562 "Counter": "0,1",563 "EventCode": "0xB7",564 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",565 "MSRIndex": "0x1a6,0x1a7",566 "MSRValue": "0x0080800002",567 "SampleAfterValue": "100007",568 "UMask": "0x1"569 },570 {571 "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",572 "Counter": "0,1",573 "EventCode": "0xB7",574 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",575 "MSRIndex": "0x1a6,0x1a7",576 "MSRValue": "0x0180600002",577 "SampleAfterValue": "100007",578 "UMask": "0x1"579 },580 {581 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",582 "Counter": "0,1",583 "EventCode": "0xB7",584 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",585 "MSRIndex": "0x1a6,0x1a7",586 "MSRValue": "0x0100400002",587 "SampleAfterValue": "100007",588 "UMask": "0x1"589 },590 {591 "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",592 "Counter": "0,1",593 "EventCode": "0xB7",594 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",595 "MSRIndex": "0x1a6,0x1a7",596 "MSRValue": "0x0080200002",597 "SampleAfterValue": "100007",598 "UMask": "0x1"599 },600 {601 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)",602 "Counter": "0,1",603 "EventCode": "0xB7",604 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",605 "MSRIndex": "0x1a6,0x1a7",606 "MSRValue": "0x0181800080",607 "SampleAfterValue": "100007",608 "UMask": "0x1"609 },610 {611 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.",612 "Counter": "0,1",613 "EventCode": "0xB7",614 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",615 "MSRIndex": "0x1a6,0x1a7",616 "MSRValue": "0x0101000080",617 "SampleAfterValue": "100007",618 "UMask": "0x1"619 },620 {621 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.",622 "Counter": "0,1",623 "EventCode": "0xB7",624 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",625 "MSRIndex": "0x1a6,0x1a7",626 "MSRValue": "0x0080800080",627 "SampleAfterValue": "100007",628 "UMask": "0x1"629 },630 {631 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)",632 "Counter": "0,1",633 "EventCode": "0xB7",634 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",635 "MSRIndex": "0x1a6,0x1a7",636 "MSRValue": "0x0180600080",637 "SampleAfterValue": "100007",638 "UMask": "0x1"639 },640 {641 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",642 "Counter": "0,1",643 "EventCode": "0xB7",644 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",645 "MSRIndex": "0x1a6,0x1a7",646 "MSRValue": "0x0100400080",647 "SampleAfterValue": "100007",648 "UMask": "0x1"649 },650 {651 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.",652 "Counter": "0,1",653 "EventCode": "0xB7",654 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",655 "MSRIndex": "0x1a6,0x1a7",656 "MSRValue": "0x0080200080",657 "SampleAfterValue": "100007",658 "UMask": "0x1"659 },660 {661 "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",662 "Counter": "0,1",663 "EventCode": "0xB7",664 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",665 "MSRIndex": "0x1a6,0x1a7",666 "MSRValue": "0x2000020080",667 "SampleAfterValue": "100007",668 "UMask": "0x1"669 },670 {671 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",672 "Counter": "0,1",673 "EventCode": "0xB7",674 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",675 "MSRIndex": "0x1a7",676 "MSRValue": "0x0101000100",677 "SampleAfterValue": "100007",678 "UMask": "0x1"679 },680 {681 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",682 "Counter": "0,1",683 "EventCode": "0xB7",684 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",685 "MSRIndex": "0x1a7",686 "MSRValue": "0x0080800100",687 "SampleAfterValue": "100007",688 "UMask": "0x1"689 },690 {691 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",692 "Counter": "0,1",693 "EventCode": "0xB7",694 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",695 "MSRIndex": "0x1a7",696 "MSRValue": "0x0180600100",697 "SampleAfterValue": "100007",698 "UMask": "0x1"699 },700 {701 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",702 "Counter": "0,1",703 "EventCode": "0xB7",704 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",705 "MSRIndex": "0x1a7",706 "MSRValue": "0x0100400100",707 "SampleAfterValue": "100007",708 "UMask": "0x1"709 },710 {711 "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",712 "Counter": "0,1",713 "EventCode": "0xB7",714 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",715 "MSRIndex": "0x1a7",716 "MSRValue": "0x0080200100",717 "SampleAfterValue": "100007",718 "UMask": "0x1"719 },720 {721 "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",722 "Counter": "0,1",723 "EventCode": "0xB7",724 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",725 "MSRIndex": "0x1a6,0x1a7",726 "MSRValue": "0x0181802000",727 "SampleAfterValue": "100007",728 "UMask": "0x1"729 },730 {731 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",732 "Counter": "0,1",733 "EventCode": "0xB7",734 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",735 "MSRIndex": "0x1a6,0x1a7",736 "MSRValue": "0x0101002000",737 "SampleAfterValue": "100007",738 "UMask": "0x1"739 },740 {741 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",742 "Counter": "0,1",743 "EventCode": "0xB7",744 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",745 "MSRIndex": "0x1a6,0x1a7",746 "MSRValue": "0x0080802000",747 "SampleAfterValue": "100007",748 "UMask": "0x1"749 },750 {751 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",752 "Counter": "0,1",753 "EventCode": "0xB7",754 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",755 "MSRIndex": "0x1a6,0x1a7",756 "MSRValue": "0x0100402000",757 "SampleAfterValue": "100007",758 "UMask": "0x1"759 },760 {761 "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",762 "Counter": "0,1",763 "EventCode": "0xB7",764 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",765 "MSRIndex": "0x1a6,0x1a7",766 "MSRValue": "0x0080202000",767 "SampleAfterValue": "100007",768 "UMask": "0x1"769 },770 {771 "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",772 "Counter": "0,1",773 "EventCode": "0xB7",774 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",775 "MSRIndex": "0x1a6,0x1a7",776 "MSRValue": "0x0181800040",777 "SampleAfterValue": "100007",778 "UMask": "0x1"779 },780 {781 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",782 "Counter": "0,1",783 "EventCode": "0xB7",784 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",785 "MSRIndex": "0x1a6,0x1a7",786 "MSRValue": "0x0101000040",787 "SampleAfterValue": "100007",788 "UMask": "0x1"789 },790 {791 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",792 "Counter": "0,1",793 "EventCode": "0xB7",794 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",795 "MSRIndex": "0x1a6,0x1a7",796 "MSRValue": "0x0080800040",797 "SampleAfterValue": "100007",798 "UMask": "0x1"799 },800 {801 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",802 "Counter": "0,1",803 "EventCode": "0xB7",804 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",805 "MSRIndex": "0x1a6,0x1a7",806 "MSRValue": "0x0100400040",807 "SampleAfterValue": "100007",808 "UMask": "0x1"809 },810 {811 "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",812 "Counter": "0,1",813 "EventCode": "0xB7",814 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",815 "MSRIndex": "0x1a6,0x1a7",816 "MSRValue": "0x0080200040",817 "SampleAfterValue": "100007",818 "UMask": "0x1"819 },820 {821 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",822 "Counter": "0,1",823 "EventCode": "0xB7",824 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",825 "MSRIndex": "0x1a6,0x1a7",826 "MSRValue": "0x0181800020",827 "SampleAfterValue": "100007",828 "UMask": "0x1"829 },830 {831 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",832 "Counter": "0,1",833 "EventCode": "0xB7",834 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",835 "MSRIndex": "0x1a6,0x1a7",836 "MSRValue": "0x0101000020",837 "SampleAfterValue": "100007",838 "UMask": "0x1"839 },840 {841 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",842 "Counter": "0,1",843 "EventCode": "0xB7",844 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",845 "MSRIndex": "0x1a6,0x1a7",846 "MSRValue": "0x0080800020",847 "SampleAfterValue": "100007",848 "UMask": "0x1"849 },850 {851 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",852 "Counter": "0,1",853 "EventCode": "0xB7",854 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",855 "MSRIndex": "0x1a6,0x1a7",856 "MSRValue": "0x0180600020",857 "SampleAfterValue": "100007",858 "UMask": "0x1"859 },860 {861 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",862 "Counter": "0,1",863 "EventCode": "0xB7",864 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",865 "MSRIndex": "0x1a6,0x1a7",866 "MSRValue": "0x0100400020",867 "SampleAfterValue": "100007",868 "UMask": "0x1"869 },870 {871 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",872 "Counter": "0,1",873 "EventCode": "0xB7",874 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",875 "MSRIndex": "0x1a6,0x1a7",876 "MSRValue": "0x0080200020",877 "SampleAfterValue": "100007",878 "UMask": "0x1"879 },880 {881 "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",882 "Counter": "0,1",883 "EventCode": "0xB7",884 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",885 "MSRIndex": "0x1a6,0x1a7",886 "MSRValue": "0x2000020020",887 "SampleAfterValue": "100007",888 "UMask": "0x1"889 },890 {891 "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",892 "Counter": "0,1",893 "EventCode": "0xB7",894 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",895 "MSRIndex": "0x1a6,0x1a7",896 "MSRValue": "0x0181801000",897 "SampleAfterValue": "100007",898 "UMask": "0x1"899 },900 {901 "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",902 "Counter": "0,1",903 "EventCode": "0xB7",904 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",905 "MSRIndex": "0x1a6,0x1a7",906 "MSRValue": "0x0101001000",907 "SampleAfterValue": "100007",908 "UMask": "0x1"909 },910 {911 "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",912 "Counter": "0,1",913 "EventCode": "0xB7",914 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",915 "MSRIndex": "0x1a6,0x1a7",916 "MSRValue": "0x0080801000",917 "SampleAfterValue": "100007",918 "UMask": "0x1"919 },920 {921 "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",922 "Counter": "0,1",923 "EventCode": "0xB7",924 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",925 "MSRIndex": "0x1a6,0x1a7",926 "MSRValue": "0x0180601000",927 "SampleAfterValue": "100007",928 "UMask": "0x1"929 },930 {931 "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",932 "Counter": "0,1",933 "EventCode": "0xB7",934 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",935 "MSRIndex": "0x1a6,0x1a7",936 "MSRValue": "0x0100401000",937 "SampleAfterValue": "100007",938 "UMask": "0x1"939 },940 {941 "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",942 "Counter": "0,1",943 "EventCode": "0xB7",944 "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",945 "MSRIndex": "0x1a6,0x1a7",946 "MSRValue": "0x0080201000",947 "SampleAfterValue": "100007",948 "UMask": "0x1"949 },950 {951 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)",952 "Counter": "0,1",953 "EventCode": "0xB7",954 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",955 "MSRIndex": "0x1a6,0x1a7",956 "MSRValue": "0x0181800200",957 "SampleAfterValue": "100007",958 "UMask": "0x1"959 },960 {961 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.",962 "Counter": "0,1",963 "EventCode": "0xB7",964 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",965 "MSRIndex": "0x1a6,0x1a7",966 "MSRValue": "0x0101000200",967 "SampleAfterValue": "100007",968 "UMask": "0x1"969 },970 {971 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.",972 "Counter": "0,1",973 "EventCode": "0xB7",974 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",975 "MSRIndex": "0x1a6,0x1a7",976 "MSRValue": "0x0080800200",977 "SampleAfterValue": "100007",978 "UMask": "0x1"979 },980 {981 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)",982 "Counter": "0,1",983 "EventCode": "0xB7",984 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",985 "MSRIndex": "0x1a6,0x1a7",986 "MSRValue": "0x0180600200",987 "SampleAfterValue": "100007",988 "UMask": "0x1"989 },990 {991 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",992 "Counter": "0,1",993 "EventCode": "0xB7",994 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",995 "MSRIndex": "0x1a6,0x1a7",996 "MSRValue": "0x0100400200",997 "SampleAfterValue": "100007",998 "UMask": "0x1"999 },1000 {1001 "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.",1002 "Counter": "0,1",1003 "EventCode": "0xB7",1004 "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",1005 "MSRIndex": "0x1a6,0x1a7",1006 "MSRValue": "0x0080200200",1007 "SampleAfterValue": "100007",1008 "UMask": "0x1"1009 }1010]1011