306 lines · json
1[2 {3 "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",4 "Counter": "0,1,2,3,4,5,6,7",5 "CounterMask": "1",6 "EventCode": "0xcd",7 "EventName": "ARITH.FPDIV_ACTIVE",8 "SampleAfterValue": "1000003",9 "UMask": "0x2",10 "Unit": "cpu_atom"11 },12 {13 "BriefDescription": "This event counts the cycles the floating point divider is busy.",14 "Counter": "0,1,2,3,4,5,6,7",15 "CounterMask": "1",16 "EventCode": "0xb0",17 "EventName": "ARITH.FPDIV_ACTIVE",18 "SampleAfterValue": "1000003",19 "UMask": "0x1",20 "Unit": "cpu_core"21 },22 {23 "BriefDescription": "Counts all microcode FP assists.",24 "Counter": "0,1,2,3,4,5,6,7",25 "EventCode": "0xc1",26 "EventName": "ASSISTS.FP",27 "PublicDescription": "Counts all microcode Floating Point assists.",28 "SampleAfterValue": "100003",29 "UMask": "0x2",30 "Unit": "cpu_core"31 },32 {33 "BriefDescription": "ASSISTS.SSE_AVX_MIX",34 "Counter": "0,1,2,3,4,5,6,7",35 "EventCode": "0xc1",36 "EventName": "ASSISTS.SSE_AVX_MIX",37 "SampleAfterValue": "1000003",38 "UMask": "0x10",39 "Unit": "cpu_core"40 },41 {42 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",43 "Counter": "0,1,2,3,4,5,6,7",44 "EventCode": "0xb3",45 "EventName": "FP_ARITH_DISPATCHED.PORT_0",46 "SampleAfterValue": "2000003",47 "UMask": "0x1",48 "Unit": "cpu_core"49 },50 {51 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",52 "Counter": "0,1,2,3,4,5,6,7",53 "EventCode": "0xb3",54 "EventName": "FP_ARITH_DISPATCHED.PORT_1",55 "SampleAfterValue": "2000003",56 "UMask": "0x2",57 "Unit": "cpu_core"58 },59 {60 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",61 "Counter": "0,1,2,3,4,5,6,7",62 "EventCode": "0xb3",63 "EventName": "FP_ARITH_DISPATCHED.PORT_5",64 "SampleAfterValue": "2000003",65 "UMask": "0x4",66 "Unit": "cpu_core"67 },68 {69 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",70 "Counter": "0,1,2,3,4,5,6,7",71 "EventCode": "0xb3",72 "EventName": "FP_ARITH_DISPATCHED.V0",73 "SampleAfterValue": "2000003",74 "UMask": "0x1",75 "Unit": "cpu_core"76 },77 {78 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",79 "Counter": "0,1,2,3,4,5,6,7",80 "EventCode": "0xb3",81 "EventName": "FP_ARITH_DISPATCHED.V1",82 "SampleAfterValue": "2000003",83 "UMask": "0x2",84 "Unit": "cpu_core"85 },86 {87 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",88 "Counter": "0,1,2,3,4,5,6,7",89 "EventCode": "0xb3",90 "EventName": "FP_ARITH_DISPATCHED.V2",91 "SampleAfterValue": "2000003",92 "UMask": "0x4",93 "Unit": "cpu_core"94 },95 {96 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",97 "Counter": "0,1,2,3,4,5,6,7",98 "EventCode": "0xc7",99 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",100 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",101 "SampleAfterValue": "100003",102 "UMask": "0x4",103 "Unit": "cpu_core"104 },105 {106 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",107 "Counter": "0,1,2,3,4,5,6,7",108 "EventCode": "0xc7",109 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",110 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",111 "SampleAfterValue": "100003",112 "UMask": "0x8",113 "Unit": "cpu_core"114 },115 {116 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",117 "Counter": "0,1,2,3,4,5,6,7",118 "EventCode": "0xc7",119 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",120 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",121 "SampleAfterValue": "100003",122 "UMask": "0x10",123 "Unit": "cpu_core"124 },125 {126 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",127 "Counter": "0,1,2,3,4,5,6,7",128 "EventCode": "0xc7",129 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",130 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",131 "SampleAfterValue": "100003",132 "UMask": "0x20",133 "Unit": "cpu_core"134 },135 {136 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",137 "Counter": "0,1,2,3,4,5,6,7",138 "EventCode": "0xc7",139 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",140 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",141 "SampleAfterValue": "100003",142 "UMask": "0x18",143 "Unit": "cpu_core"144 },145 {146 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",147 "Counter": "0,1,2,3,4,5,6,7",148 "EventCode": "0xc7",149 "EventName": "FP_ARITH_INST_RETIRED.SCALAR",150 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",151 "SampleAfterValue": "1000003",152 "UMask": "0x3",153 "Unit": "cpu_core"154 },155 {156 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",157 "Counter": "0,1,2,3,4,5,6,7",158 "EventCode": "0xc7",159 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",160 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",161 "SampleAfterValue": "100003",162 "UMask": "0x1",163 "Unit": "cpu_core"164 },165 {166 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",167 "Counter": "0,1,2,3,4,5,6,7",168 "EventCode": "0xc7",169 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",170 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",171 "SampleAfterValue": "100003",172 "UMask": "0x2",173 "Unit": "cpu_core"174 },175 {176 "BriefDescription": "Number of any Vector retired FP arithmetic instructions",177 "Counter": "0,1,2,3,4,5,6,7",178 "EventCode": "0xc7",179 "EventName": "FP_ARITH_INST_RETIRED.VECTOR",180 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",181 "SampleAfterValue": "1000003",182 "UMask": "0xfc",183 "Unit": "cpu_core"184 },185 {186 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",187 "Counter": "0,1,2,3,4,5,6,7",188 "EventCode": "0xc8",189 "EventName": "FP_FLOPS_RETIRED.ALL",190 "SampleAfterValue": "1000003",191 "UMask": "0x3",192 "Unit": "cpu_atom"193 },194 {195 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",196 "Counter": "0,1,2,3,4,5,6,7",197 "Deprecated": "1",198 "EventCode": "0xc8",199 "EventName": "FP_FLOPS_RETIRED.DP",200 "SampleAfterValue": "1000003",201 "UMask": "0x1",202 "Unit": "cpu_atom"203 },204 {205 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",206 "Counter": "0,1,2,3,4,5,6,7",207 "EventCode": "0xc8",208 "EventName": "FP_FLOPS_RETIRED.FP32",209 "SampleAfterValue": "1000003",210 "UMask": "0x2",211 "Unit": "cpu_atom"212 },213 {214 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",215 "Counter": "0,1,2,3,4,5,6,7",216 "EventCode": "0xc8",217 "EventName": "FP_FLOPS_RETIRED.FP64",218 "SampleAfterValue": "1000003",219 "UMask": "0x1",220 "Unit": "cpu_atom"221 },222 {223 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",224 "Counter": "0,1,2,3,4,5,6,7",225 "Deprecated": "1",226 "EventCode": "0xc8",227 "EventName": "FP_FLOPS_RETIRED.SP",228 "SampleAfterValue": "1000003",229 "UMask": "0x2",230 "Unit": "cpu_atom"231 },232 {233 "BriefDescription": "Counts the total number of floating point retired instructions.",234 "Counter": "0,1,2,3,4,5,6,7",235 "EventCode": "0xc7",236 "EventName": "FP_INST_RETIRED.128B_DP",237 "SampleAfterValue": "1000003",238 "UMask": "0x8",239 "Unit": "cpu_atom"240 },241 {242 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",243 "Counter": "0,1,2,3,4,5,6,7",244 "EventCode": "0xc7",245 "EventName": "FP_INST_RETIRED.128B_SP",246 "SampleAfterValue": "1000003",247 "UMask": "0x4",248 "Unit": "cpu_atom"249 },250 {251 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",252 "Counter": "0,1,2,3,4,5,6,7",253 "EventCode": "0xc7",254 "EventName": "FP_INST_RETIRED.256B_DP",255 "SampleAfterValue": "1000003",256 "UMask": "0x20",257 "Unit": "cpu_atom"258 },259 {260 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.",261 "Counter": "0,1,2,3,4,5,6,7",262 "EventCode": "0xc7",263 "EventName": "FP_INST_RETIRED.32B_SP",264 "SampleAfterValue": "1000003",265 "UMask": "0x1",266 "Unit": "cpu_atom"267 },268 {269 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.",270 "Counter": "0,1,2,3,4,5,6,7",271 "EventCode": "0xc7",272 "EventName": "FP_INST_RETIRED.64B_DP",273 "SampleAfterValue": "1000003",274 "UMask": "0x2",275 "Unit": "cpu_atom"276 },277 {278 "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",279 "Counter": "0,1,2,3,4,5,6,7",280 "EventCode": "0xb2",281 "EventName": "FP_VINT_UOPS_EXECUTED.STD",282 "SampleAfterValue": "1000003",283 "UMask": "0x1",284 "Unit": "cpu_atom"285 },286 {287 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",288 "Counter": "0,1,2,3,4,5,6,7",289 "EventCode": "0xc3",290 "EventName": "MACHINE_CLEARS.FP_ASSIST",291 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",292 "SampleAfterValue": "20003",293 "UMask": "0x4",294 "Unit": "cpu_atom"295 },296 {297 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",298 "Counter": "0,1,2,3,4,5,6,7",299 "EventCode": "0xc2",300 "EventName": "UOPS_RETIRED.FPDIV",301 "SampleAfterValue": "2000003",302 "UMask": "0x8",303 "Unit": "cpu_atom"304 }305]306