53 lines · json
1[2 {3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",4 "Counter": "0,1,2,3",5 "EventCode": "0x5C",6 "EventName": "CPL_CYCLES.RING0",7 "SampleAfterValue": "2000003",8 "UMask": "0x1"9 },10 {11 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",12 "Counter": "0,1,2,3",13 "CounterMask": "1",14 "EdgeDetect": "1",15 "EventCode": "0x5C",16 "EventName": "CPL_CYCLES.RING0_TRANS",17 "SampleAfterValue": "100007",18 "UMask": "0x1"19 },20 {21 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",22 "Counter": "0,1,2,3",23 "EventCode": "0x5C",24 "EventName": "CPL_CYCLES.RING123",25 "SampleAfterValue": "2000003",26 "UMask": "0x2"27 },28 {29 "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",30 "Counter": "0,1,2,3",31 "EventCode": "0x4E",32 "EventName": "HW_PRE_REQ.DL1_MISS",33 "SampleAfterValue": "2000003",34 "UMask": "0x2"35 },36 {37 "BriefDescription": "Valid instructions written to IQ per cycle.",38 "Counter": "0,1,2,3",39 "EventCode": "0x17",40 "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",41 "SampleAfterValue": "2000003",42 "UMask": "0x1"43 },44 {45 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",46 "Counter": "0,1,2,3",47 "EventCode": "0x63",48 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",49 "SampleAfterValue": "2000003",50 "UMask": "0x1"51 }52]53