93 lines · json
1[2 {3 "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",4 "Counter": "0,1,2,3",5 "EventCode": "0xC7",6 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",7 "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",8 "SampleAfterValue": "2000003",9 "UMask": "0x4"10 },11 {12 "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",13 "Counter": "0,1,2,3",14 "EventCode": "0xC7",15 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",16 "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",17 "SampleAfterValue": "2000003",18 "UMask": "0x8"19 },20 {21 "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",22 "Counter": "0,1,2,3",23 "EventCode": "0xC7",24 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",25 "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",26 "SampleAfterValue": "2000003",27 "UMask": "0x10"28 },29 {30 "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",31 "Counter": "0,1,2,3",32 "EventCode": "0xC7",33 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",34 "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",35 "SampleAfterValue": "2000003",36 "UMask": "0x20"37 },38 {39 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",40 "Counter": "0,1,2,3",41 "EventCode": "0xC7",42 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",43 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",44 "SampleAfterValue": "1000003",45 "UMask": "0x18"46 },47 {48 "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",49 "Counter": "0,1,2,3",50 "EventCode": "0xC7",51 "EventName": "FP_ARITH_INST_RETIRED.SCALAR",52 "PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",53 "SampleAfterValue": "2000003",54 "UMask": "0x3"55 },56 {57 "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",58 "Counter": "0,1,2,3",59 "EventCode": "0xC7",60 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",61 "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",62 "SampleAfterValue": "2000003",63 "UMask": "0x1"64 },65 {66 "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",67 "Counter": "0,1,2,3",68 "EventCode": "0xC7",69 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",70 "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",71 "SampleAfterValue": "2000003",72 "UMask": "0x2"73 },74 {75 "BriefDescription": "Number of any Vector retired FP arithmetic instructions",76 "Counter": "0,1,2,3",77 "EventCode": "0xC7",78 "EventName": "FP_ARITH_INST_RETIRED.VECTOR",79 "SampleAfterValue": "2000003",80 "UMask": "0xfc"81 },82 {83 "BriefDescription": "Cycles with any input/output SSE or FP assist",84 "Counter": "0,1,2,3",85 "CounterMask": "1",86 "EventCode": "0xCA",87 "EventName": "FP_ASSIST.ANY",88 "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",89 "SampleAfterValue": "100003",90 "UMask": "0x1e"91 }92]93