243 lines · json
1[2 {3 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",4 "Counter": "0,1,2,3",5 "CounterMask": "6",6 "EventCode": "0xa3",7 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",8 "SampleAfterValue": "1000003",9 "UMask": "0x6"10 },11 {12 "BriefDescription": "Number of machine clears due to memory ordering conflicts.",13 "Counter": "0,1,2,3,4,5,6,7",14 "EventCode": "0xc3",15 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",16 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",17 "SampleAfterValue": "100003",18 "UMask": "0x2"19 },20 {21 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",22 "Counter": "0,1,2,3,4,5,6,7",23 "Data_LA": "1",24 "EventCode": "0xcd",25 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",26 "MSRIndex": "0x3F6",27 "MSRValue": "0x80",28 "PEBS": "2",29 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",30 "SampleAfterValue": "1009",31 "UMask": "0x1"32 },33 {34 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",35 "Counter": "0,1,2,3,4,5,6,7",36 "Data_LA": "1",37 "EventCode": "0xcd",38 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",39 "MSRIndex": "0x3F6",40 "MSRValue": "0x10",41 "PEBS": "2",42 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",43 "SampleAfterValue": "20011",44 "UMask": "0x1"45 },46 {47 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",48 "Counter": "0,1,2,3,4,5,6,7",49 "Data_LA": "1",50 "EventCode": "0xcd",51 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",52 "MSRIndex": "0x3F6",53 "MSRValue": "0x100",54 "PEBS": "2",55 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",56 "SampleAfterValue": "503",57 "UMask": "0x1"58 },59 {60 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",61 "Counter": "0,1,2,3,4,5,6,7",62 "Data_LA": "1",63 "EventCode": "0xcd",64 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",65 "MSRIndex": "0x3F6",66 "MSRValue": "0x20",67 "PEBS": "2",68 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",69 "SampleAfterValue": "100007",70 "UMask": "0x1"71 },72 {73 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",74 "Counter": "0,1,2,3,4,5,6,7",75 "Data_LA": "1",76 "EventCode": "0xcd",77 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",78 "MSRIndex": "0x3F6",79 "MSRValue": "0x4",80 "PEBS": "2",81 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",82 "SampleAfterValue": "100003",83 "UMask": "0x1"84 },85 {86 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",87 "Counter": "0,1,2,3,4,5,6,7",88 "Data_LA": "1",89 "EventCode": "0xcd",90 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",91 "MSRIndex": "0x3F6",92 "MSRValue": "0x200",93 "PEBS": "2",94 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",95 "SampleAfterValue": "101",96 "UMask": "0x1"97 },98 {99 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",100 "Counter": "0,1,2,3,4,5,6,7",101 "Data_LA": "1",102 "EventCode": "0xcd",103 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",104 "MSRIndex": "0x3F6",105 "MSRValue": "0x40",106 "PEBS": "2",107 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",108 "SampleAfterValue": "2003",109 "UMask": "0x1"110 },111 {112 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",113 "Counter": "0,1,2,3,4,5,6,7",114 "Data_LA": "1",115 "EventCode": "0xcd",116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",117 "MSRIndex": "0x3F6",118 "MSRValue": "0x8",119 "PEBS": "2",120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",121 "SampleAfterValue": "50021",122 "UMask": "0x1"123 },124 {125 "BriefDescription": "Demand Data Read requests who miss L3 cache",126 "Counter": "0,1,2,3",127 "EventCode": "0xb0",128 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",129 "PublicDescription": "Demand Data Read requests who miss L3 cache.",130 "SampleAfterValue": "100003",131 "UMask": "0x10"132 },133 {134 "BriefDescription": "Number of times an RTM execution aborted.",135 "Counter": "0,1,2,3,4,5,6,7",136 "EventCode": "0xc9",137 "EventName": "RTM_RETIRED.ABORTED",138 "PEBS": "1",139 "PublicDescription": "Counts the number of times RTM abort was triggered.",140 "SampleAfterValue": "100003",141 "UMask": "0x4"142 },143 {144 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",145 "Counter": "0,1,2,3,4,5,6,7",146 "EventCode": "0xc9",147 "EventName": "RTM_RETIRED.ABORTED_EVENTS",148 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",149 "SampleAfterValue": "100003",150 "UMask": "0x80"151 },152 {153 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",154 "Counter": "0,1,2,3,4,5,6,7",155 "EventCode": "0xc9",156 "EventName": "RTM_RETIRED.ABORTED_MEM",157 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",158 "SampleAfterValue": "100003",159 "UMask": "0x8"160 },161 {162 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",163 "Counter": "0,1,2,3,4,5,6,7",164 "EventCode": "0xc9",165 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",166 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",167 "SampleAfterValue": "100003",168 "UMask": "0x40"169 },170 {171 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",172 "Counter": "0,1,2,3,4,5,6,7",173 "EventCode": "0xc9",174 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",175 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",176 "SampleAfterValue": "100003",177 "UMask": "0x20"178 },179 {180 "BriefDescription": "Number of times an RTM execution successfully committed",181 "Counter": "0,1,2,3,4,5,6,7",182 "EventCode": "0xc9",183 "EventName": "RTM_RETIRED.COMMIT",184 "PublicDescription": "Counts the number of times RTM commit succeeded.",185 "SampleAfterValue": "100003",186 "UMask": "0x2"187 },188 {189 "BriefDescription": "Number of times an RTM execution started.",190 "Counter": "0,1,2,3,4,5,6,7",191 "EventCode": "0xc9",192 "EventName": "RTM_RETIRED.START",193 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",194 "SampleAfterValue": "100003",195 "UMask": "0x1"196 },197 {198 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",199 "Counter": "0,1,2,3,4,5,6,7",200 "EventCode": "0x5d",201 "EventName": "TX_EXEC.MISC2",202 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",203 "SampleAfterValue": "100003",204 "UMask": "0x2"205 },206 {207 "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",208 "Counter": "0,1,2,3,4,5,6,7",209 "EventCode": "0x5d",210 "EventName": "TX_EXEC.MISC3",211 "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",212 "SampleAfterValue": "100003",213 "UMask": "0x4"214 },215 {216 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",217 "Counter": "0,1,2,3",218 "EventCode": "0x54",219 "EventName": "TX_MEM.ABORT_CAPACITY_READ",220 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",221 "SampleAfterValue": "100003",222 "UMask": "0x80"223 },224 {225 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",226 "Counter": "0,1,2,3",227 "EventCode": "0x54",228 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",229 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",230 "SampleAfterValue": "100003",231 "UMask": "0x2"232 },233 {234 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",235 "Counter": "0,1,2,3",236 "EventCode": "0x54",237 "EventName": "TX_MEM.ABORT_CONFLICT",238 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",239 "SampleAfterValue": "100003",240 "UMask": "0x1"241 }242]243