956 lines · json
1[2 {3 "BriefDescription": "Cycles the divider is busy",4 "Counter": "0,1,2,3",5 "EventCode": "0x14",6 "EventName": "ARITH.CYCLES_DIV_BUSY",7 "SampleAfterValue": "2000000",8 "UMask": "0x1"9 },10 {11 "BriefDescription": "Divide Operations executed",12 "Counter": "0,1,2,3",13 "CounterMask": "1",14 "EdgeDetect": "1",15 "EventCode": "0x14",16 "EventName": "ARITH.DIV",17 "Invert": "1",18 "SampleAfterValue": "2000000",19 "UMask": "0x1"20 },21 {22 "BriefDescription": "Multiply operations executed",23 "Counter": "0,1,2,3",24 "EventCode": "0x14",25 "EventName": "ARITH.MUL",26 "SampleAfterValue": "2000000",27 "UMask": "0x2"28 },29 {30 "BriefDescription": "BACLEAR asserted with bad target address",31 "Counter": "0,1,2,3",32 "EventCode": "0xE6",33 "EventName": "BACLEAR.BAD_TARGET",34 "SampleAfterValue": "2000000",35 "UMask": "0x2"36 },37 {38 "BriefDescription": "BACLEAR asserted, regardless of cause",39 "Counter": "0,1,2,3",40 "EventCode": "0xE6",41 "EventName": "BACLEAR.CLEAR",42 "SampleAfterValue": "2000000",43 "UMask": "0x1"44 },45 {46 "BriefDescription": "Instruction queue forced BACLEAR",47 "Counter": "0,1,2,3",48 "EventCode": "0xA7",49 "EventName": "BACLEAR_FORCE_IQ",50 "SampleAfterValue": "2000000",51 "UMask": "0x1"52 },53 {54 "BriefDescription": "Early Branch Prediciton Unit clears",55 "Counter": "0,1,2,3",56 "EventCode": "0xE8",57 "EventName": "BPU_CLEARS.EARLY",58 "SampleAfterValue": "2000000",59 "UMask": "0x1"60 },61 {62 "BriefDescription": "Late Branch Prediction Unit clears",63 "Counter": "0,1,2,3",64 "EventCode": "0xE8",65 "EventName": "BPU_CLEARS.LATE",66 "SampleAfterValue": "2000000",67 "UMask": "0x2"68 },69 {70 "BriefDescription": "Branch prediction unit missed call or return",71 "Counter": "0,1,2,3",72 "EventCode": "0xE5",73 "EventName": "BPU_MISSED_CALL_RET",74 "SampleAfterValue": "2000000",75 "UMask": "0x1"76 },77 {78 "BriefDescription": "Branch instructions decoded",79 "Counter": "0,1,2,3",80 "EventCode": "0xE0",81 "EventName": "BR_INST_DECODED",82 "SampleAfterValue": "2000000",83 "UMask": "0x1"84 },85 {86 "BriefDescription": "Branch instructions executed",87 "Counter": "0,1,2,3",88 "EventCode": "0x88",89 "EventName": "BR_INST_EXEC.ANY",90 "SampleAfterValue": "200000",91 "UMask": "0x7f"92 },93 {94 "BriefDescription": "Conditional branch instructions executed",95 "Counter": "0,1,2,3",96 "EventCode": "0x88",97 "EventName": "BR_INST_EXEC.COND",98 "SampleAfterValue": "200000",99 "UMask": "0x1"100 },101 {102 "BriefDescription": "Unconditional branches executed",103 "Counter": "0,1,2,3",104 "EventCode": "0x88",105 "EventName": "BR_INST_EXEC.DIRECT",106 "SampleAfterValue": "200000",107 "UMask": "0x2"108 },109 {110 "BriefDescription": "Unconditional call branches executed",111 "Counter": "0,1,2,3",112 "EventCode": "0x88",113 "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",114 "SampleAfterValue": "20000",115 "UMask": "0x10"116 },117 {118 "BriefDescription": "Indirect call branches executed",119 "Counter": "0,1,2,3",120 "EventCode": "0x88",121 "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",122 "SampleAfterValue": "20000",123 "UMask": "0x20"124 },125 {126 "BriefDescription": "Indirect non call branches executed",127 "Counter": "0,1,2,3",128 "EventCode": "0x88",129 "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",130 "SampleAfterValue": "20000",131 "UMask": "0x4"132 },133 {134 "BriefDescription": "Call branches executed",135 "Counter": "0,1,2,3",136 "EventCode": "0x88",137 "EventName": "BR_INST_EXEC.NEAR_CALLS",138 "SampleAfterValue": "20000",139 "UMask": "0x30"140 },141 {142 "BriefDescription": "All non call branches executed",143 "Counter": "0,1,2,3",144 "EventCode": "0x88",145 "EventName": "BR_INST_EXEC.NON_CALLS",146 "SampleAfterValue": "200000",147 "UMask": "0x7"148 },149 {150 "BriefDescription": "Indirect return branches executed",151 "Counter": "0,1,2,3",152 "EventCode": "0x88",153 "EventName": "BR_INST_EXEC.RETURN_NEAR",154 "SampleAfterValue": "20000",155 "UMask": "0x8"156 },157 {158 "BriefDescription": "Taken branches executed",159 "Counter": "0,1,2,3",160 "EventCode": "0x88",161 "EventName": "BR_INST_EXEC.TAKEN",162 "SampleAfterValue": "200000",163 "UMask": "0x40"164 },165 {166 "BriefDescription": "Retired branch instructions (Precise Event)",167 "Counter": "0,1,2,3",168 "EventCode": "0xC4",169 "EventName": "BR_INST_RETIRED.ALL_BRANCHES",170 "PEBS": "1",171 "SampleAfterValue": "200000",172 "UMask": "0x4"173 },174 {175 "BriefDescription": "Retired conditional branch instructions (Precise Event)",176 "Counter": "0,1,2,3",177 "EventCode": "0xC4",178 "EventName": "BR_INST_RETIRED.CONDITIONAL",179 "PEBS": "1",180 "SampleAfterValue": "200000",181 "UMask": "0x1"182 },183 {184 "BriefDescription": "Retired near call instructions (Precise Event)",185 "Counter": "0,1,2,3",186 "EventCode": "0xC4",187 "EventName": "BR_INST_RETIRED.NEAR_CALL",188 "PEBS": "1",189 "SampleAfterValue": "20000",190 "UMask": "0x2"191 },192 {193 "BriefDescription": "Mispredicted branches executed",194 "Counter": "0,1,2,3",195 "EventCode": "0x89",196 "EventName": "BR_MISP_EXEC.ANY",197 "SampleAfterValue": "20000",198 "UMask": "0x7f"199 },200 {201 "BriefDescription": "Mispredicted conditional branches executed",202 "Counter": "0,1,2,3",203 "EventCode": "0x89",204 "EventName": "BR_MISP_EXEC.COND",205 "SampleAfterValue": "20000",206 "UMask": "0x1"207 },208 {209 "BriefDescription": "Mispredicted unconditional branches executed",210 "Counter": "0,1,2,3",211 "EventCode": "0x89",212 "EventName": "BR_MISP_EXEC.DIRECT",213 "SampleAfterValue": "20000",214 "UMask": "0x2"215 },216 {217 "BriefDescription": "Mispredicted non call branches executed",218 "Counter": "0,1,2,3",219 "EventCode": "0x89",220 "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",221 "SampleAfterValue": "2000",222 "UMask": "0x10"223 },224 {225 "BriefDescription": "Mispredicted indirect call branches executed",226 "Counter": "0,1,2,3",227 "EventCode": "0x89",228 "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",229 "SampleAfterValue": "2000",230 "UMask": "0x20"231 },232 {233 "BriefDescription": "Mispredicted indirect non call branches executed",234 "Counter": "0,1,2,3",235 "EventCode": "0x89",236 "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",237 "SampleAfterValue": "2000",238 "UMask": "0x4"239 },240 {241 "BriefDescription": "Mispredicted call branches executed",242 "Counter": "0,1,2,3",243 "EventCode": "0x89",244 "EventName": "BR_MISP_EXEC.NEAR_CALLS",245 "SampleAfterValue": "2000",246 "UMask": "0x30"247 },248 {249 "BriefDescription": "Mispredicted non call branches executed",250 "Counter": "0,1,2,3",251 "EventCode": "0x89",252 "EventName": "BR_MISP_EXEC.NON_CALLS",253 "SampleAfterValue": "20000",254 "UMask": "0x7"255 },256 {257 "BriefDescription": "Mispredicted return branches executed",258 "Counter": "0,1,2,3",259 "EventCode": "0x89",260 "EventName": "BR_MISP_EXEC.RETURN_NEAR",261 "SampleAfterValue": "2000",262 "UMask": "0x8"263 },264 {265 "BriefDescription": "Mispredicted taken branches executed",266 "Counter": "0,1,2,3",267 "EventCode": "0x89",268 "EventName": "BR_MISP_EXEC.TAKEN",269 "SampleAfterValue": "20000",270 "UMask": "0x40"271 },272 {273 "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",274 "Counter": "0,1,2,3",275 "EventCode": "0xC5",276 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",277 "PEBS": "1",278 "SampleAfterValue": "20000",279 "UMask": "0x4"280 },281 {282 "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",283 "Counter": "0,1,2,3",284 "EventCode": "0xC5",285 "EventName": "BR_MISP_RETIRED.CONDITIONAL",286 "PEBS": "1",287 "SampleAfterValue": "20000",288 "UMask": "0x1"289 },290 {291 "BriefDescription": "Mispredicted near retired calls (Precise Event)",292 "Counter": "0,1,2,3",293 "EventCode": "0xC5",294 "EventName": "BR_MISP_RETIRED.NEAR_CALL",295 "PEBS": "1",296 "SampleAfterValue": "2000",297 "UMask": "0x2"298 },299 {300 "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",301 "Counter": "Fixed counter 3",302 "EventName": "CPU_CLK_UNHALTED.REF",303 "SampleAfterValue": "2000000"304 },305 {306 "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",307 "Counter": "0,1,2,3",308 "EventCode": "0x3C",309 "EventName": "CPU_CLK_UNHALTED.REF_P",310 "SampleAfterValue": "100000",311 "UMask": "0x1"312 },313 {314 "BriefDescription": "Cycles when thread is not halted (fixed counter)",315 "Counter": "Fixed counter 2",316 "EventName": "CPU_CLK_UNHALTED.THREAD",317 "SampleAfterValue": "2000000"318 },319 {320 "BriefDescription": "Cycles when thread is not halted (programmable counter)",321 "Counter": "0,1,2,3",322 "EventCode": "0x3C",323 "EventName": "CPU_CLK_UNHALTED.THREAD_P",324 "SampleAfterValue": "2000000"325 },326 {327 "BriefDescription": "Total CPU cycles",328 "Counter": "0,1,2,3",329 "CounterMask": "2",330 "EventCode": "0x3C",331 "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",332 "Invert": "1",333 "SampleAfterValue": "2000000"334 },335 {336 "BriefDescription": "Any Instruction Length Decoder stall cycles",337 "Counter": "0,1,2,3",338 "EventCode": "0x87",339 "EventName": "ILD_STALL.ANY",340 "SampleAfterValue": "2000000",341 "UMask": "0xf"342 },343 {344 "BriefDescription": "Instruction Queue full stall cycles",345 "Counter": "0,1,2,3",346 "EventCode": "0x87",347 "EventName": "ILD_STALL.IQ_FULL",348 "SampleAfterValue": "2000000",349 "UMask": "0x4"350 },351 {352 "BriefDescription": "Length Change Prefix stall cycles",353 "Counter": "0,1,2,3",354 "EventCode": "0x87",355 "EventName": "ILD_STALL.LCP",356 "SampleAfterValue": "2000000",357 "UMask": "0x1"358 },359 {360 "BriefDescription": "Stall cycles due to BPU MRU bypass",361 "Counter": "0,1,2,3",362 "EventCode": "0x87",363 "EventName": "ILD_STALL.MRU",364 "SampleAfterValue": "2000000",365 "UMask": "0x2"366 },367 {368 "BriefDescription": "Regen stall cycles",369 "Counter": "0,1,2,3",370 "EventCode": "0x87",371 "EventName": "ILD_STALL.REGEN",372 "SampleAfterValue": "2000000",373 "UMask": "0x8"374 },375 {376 "BriefDescription": "Instructions that must be decoded by decoder 0",377 "Counter": "0,1,2,3",378 "EventCode": "0x18",379 "EventName": "INST_DECODED.DEC0",380 "SampleAfterValue": "2000000",381 "UMask": "0x1"382 },383 {384 "BriefDescription": "Instructions written to instruction queue.",385 "Counter": "0,1,2,3",386 "EventCode": "0x17",387 "EventName": "INST_QUEUE_WRITES",388 "SampleAfterValue": "2000000",389 "UMask": "0x1"390 },391 {392 "BriefDescription": "Cycles instructions are written to the instruction queue",393 "Counter": "0,1,2,3",394 "EventCode": "0x1E",395 "EventName": "INST_QUEUE_WRITE_CYCLES",396 "SampleAfterValue": "2000000",397 "UMask": "0x1"398 },399 {400 "BriefDescription": "Instructions retired (fixed counter)",401 "Counter": "Fixed counter 1",402 "EventName": "INST_RETIRED.ANY",403 "SampleAfterValue": "2000000"404 },405 {406 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",407 "Counter": "0,1,2,3",408 "EventCode": "0xC0",409 "EventName": "INST_RETIRED.ANY_P",410 "PEBS": "1",411 "SampleAfterValue": "2000000",412 "UMask": "0x1"413 },414 {415 "BriefDescription": "Retired MMX instructions (Precise Event)",416 "Counter": "0,1,2,3",417 "EventCode": "0xC0",418 "EventName": "INST_RETIRED.MMX",419 "PEBS": "1",420 "SampleAfterValue": "2000000",421 "UMask": "0x4"422 },423 {424 "BriefDescription": "Total cycles (Precise Event)",425 "Counter": "0,1,2,3",426 "CounterMask": "16",427 "EventCode": "0xC0",428 "EventName": "INST_RETIRED.TOTAL_CYCLES",429 "Invert": "1",430 "PEBS": "1",431 "SampleAfterValue": "2000000",432 "UMask": "0x1"433 },434 {435 "BriefDescription": "Total cycles (Precise Event)",436 "Counter": "0,1,2,3",437 "CounterMask": "16",438 "EventCode": "0xC0",439 "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",440 "Invert": "1",441 "PEBS": "2",442 "SampleAfterValue": "2000000",443 "UMask": "0x1"444 },445 {446 "BriefDescription": "Retired floating-point operations (Precise Event)",447 "Counter": "0,1,2,3",448 "EventCode": "0xC0",449 "EventName": "INST_RETIRED.X87",450 "PEBS": "1",451 "SampleAfterValue": "2000000",452 "UMask": "0x2"453 },454 {455 "BriefDescription": "Load operations conflicting with software prefetches",456 "Counter": "0,1",457 "EventCode": "0x4C",458 "EventName": "LOAD_HIT_PRE",459 "SampleAfterValue": "200000",460 "UMask": "0x1"461 },462 {463 "BriefDescription": "Cycles when uops were delivered by the LSD",464 "Counter": "0,1,2,3",465 "CounterMask": "1",466 "EventCode": "0xA8",467 "EventName": "LSD.ACTIVE",468 "SampleAfterValue": "2000000",469 "UMask": "0x1"470 },471 {472 "BriefDescription": "Cycles no uops were delivered by the LSD",473 "Counter": "0,1,2,3",474 "CounterMask": "1",475 "EventCode": "0xA8",476 "EventName": "LSD.INACTIVE",477 "Invert": "1",478 "SampleAfterValue": "2000000",479 "UMask": "0x1"480 },481 {482 "BriefDescription": "Loops that can't stream from the instruction queue",483 "Counter": "0,1,2,3",484 "EventCode": "0x20",485 "EventName": "LSD_OVERFLOW",486 "SampleAfterValue": "2000000",487 "UMask": "0x1"488 },489 {490 "BriefDescription": "Cycles machine clear asserted",491 "Counter": "0,1,2,3",492 "EventCode": "0xC3",493 "EventName": "MACHINE_CLEARS.CYCLES",494 "SampleAfterValue": "20000",495 "UMask": "0x1"496 },497 {498 "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",499 "Counter": "0,1,2,3",500 "EventCode": "0xC3",501 "EventName": "MACHINE_CLEARS.MEM_ORDER",502 "SampleAfterValue": "20000",503 "UMask": "0x2"504 },505 {506 "BriefDescription": "Self-Modifying Code detected",507 "Counter": "0,1,2,3",508 "EventCode": "0xC3",509 "EventName": "MACHINE_CLEARS.SMC",510 "SampleAfterValue": "20000",511 "UMask": "0x4"512 },513 {514 "BriefDescription": "All RAT stall cycles",515 "Counter": "0,1,2,3",516 "EventCode": "0xD2",517 "EventName": "RAT_STALLS.ANY",518 "SampleAfterValue": "2000000",519 "UMask": "0xf"520 },521 {522 "BriefDescription": "Flag stall cycles",523 "Counter": "0,1,2,3",524 "EventCode": "0xD2",525 "EventName": "RAT_STALLS.FLAGS",526 "SampleAfterValue": "2000000",527 "UMask": "0x1"528 },529 {530 "BriefDescription": "Partial register stall cycles",531 "Counter": "0,1,2,3",532 "EventCode": "0xD2",533 "EventName": "RAT_STALLS.REGISTERS",534 "SampleAfterValue": "2000000",535 "UMask": "0x2"536 },537 {538 "BriefDescription": "ROB read port stalls cycles",539 "Counter": "0,1,2,3",540 "EventCode": "0xD2",541 "EventName": "RAT_STALLS.ROB_READ_PORT",542 "SampleAfterValue": "2000000",543 "UMask": "0x4"544 },545 {546 "BriefDescription": "Scoreboard stall cycles",547 "Counter": "0,1,2,3",548 "EventCode": "0xD2",549 "EventName": "RAT_STALLS.SCOREBOARD",550 "SampleAfterValue": "2000000",551 "UMask": "0x8"552 },553 {554 "BriefDescription": "Resource related stall cycles",555 "Counter": "0,1,2,3",556 "EventCode": "0xA2",557 "EventName": "RESOURCE_STALLS.ANY",558 "SampleAfterValue": "2000000",559 "UMask": "0x1"560 },561 {562 "BriefDescription": "FPU control word write stall cycles",563 "Counter": "0,1,2,3",564 "EventCode": "0xA2",565 "EventName": "RESOURCE_STALLS.FPCW",566 "SampleAfterValue": "2000000",567 "UMask": "0x20"568 },569 {570 "BriefDescription": "Load buffer stall cycles",571 "Counter": "0,1,2,3",572 "EventCode": "0xA2",573 "EventName": "RESOURCE_STALLS.LOAD",574 "SampleAfterValue": "2000000",575 "UMask": "0x2"576 },577 {578 "BriefDescription": "MXCSR rename stall cycles",579 "Counter": "0,1,2,3",580 "EventCode": "0xA2",581 "EventName": "RESOURCE_STALLS.MXCSR",582 "SampleAfterValue": "2000000",583 "UMask": "0x40"584 },585 {586 "BriefDescription": "Other Resource related stall cycles",587 "Counter": "0,1,2,3",588 "EventCode": "0xA2",589 "EventName": "RESOURCE_STALLS.OTHER",590 "SampleAfterValue": "2000000",591 "UMask": "0x80"592 },593 {594 "BriefDescription": "ROB full stall cycles",595 "Counter": "0,1,2,3",596 "EventCode": "0xA2",597 "EventName": "RESOURCE_STALLS.ROB_FULL",598 "SampleAfterValue": "2000000",599 "UMask": "0x10"600 },601 {602 "BriefDescription": "Reservation Station full stall cycles",603 "Counter": "0,1,2,3",604 "EventCode": "0xA2",605 "EventName": "RESOURCE_STALLS.RS_FULL",606 "SampleAfterValue": "2000000",607 "UMask": "0x4"608 },609 {610 "BriefDescription": "Store buffer stall cycles",611 "Counter": "0,1,2,3",612 "EventCode": "0xA2",613 "EventName": "RESOURCE_STALLS.STORE",614 "SampleAfterValue": "2000000",615 "UMask": "0x8"616 },617 {618 "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",619 "Counter": "0,1,2,3",620 "EventCode": "0xC7",621 "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",622 "PEBS": "1",623 "SampleAfterValue": "200000",624 "UMask": "0x4"625 },626 {627 "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",628 "Counter": "0,1,2,3",629 "EventCode": "0xC7",630 "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",631 "PEBS": "1",632 "SampleAfterValue": "200000",633 "UMask": "0x1"634 },635 {636 "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",637 "Counter": "0,1,2,3",638 "EventCode": "0xC7",639 "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",640 "PEBS": "1",641 "SampleAfterValue": "200000",642 "UMask": "0x8"643 },644 {645 "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",646 "Counter": "0,1,2,3",647 "EventCode": "0xC7",648 "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",649 "PEBS": "1",650 "SampleAfterValue": "200000",651 "UMask": "0x2"652 },653 {654 "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",655 "Counter": "0,1,2,3",656 "EventCode": "0xC7",657 "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",658 "PEBS": "1",659 "SampleAfterValue": "200000",660 "UMask": "0x10"661 },662 {663 "BriefDescription": "Stack pointer instructions decoded",664 "Counter": "0,1,2,3",665 "EventCode": "0xD1",666 "EventName": "UOPS_DECODED.ESP_FOLDING",667 "SampleAfterValue": "2000000",668 "UMask": "0x4"669 },670 {671 "BriefDescription": "Stack pointer sync operations",672 "Counter": "0,1,2,3",673 "EventCode": "0xD1",674 "EventName": "UOPS_DECODED.ESP_SYNC",675 "SampleAfterValue": "2000000",676 "UMask": "0x8"677 },678 {679 "BriefDescription": "Uops decoded by Microcode Sequencer",680 "Counter": "0,1,2,3",681 "CounterMask": "1",682 "EventCode": "0xD1",683 "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",684 "SampleAfterValue": "2000000",685 "UMask": "0x2"686 },687 {688 "BriefDescription": "Cycles no Uops are decoded",689 "Counter": "0,1,2,3",690 "CounterMask": "1",691 "EventCode": "0xD1",692 "EventName": "UOPS_DECODED.STALL_CYCLES",693 "Invert": "1",694 "SampleAfterValue": "2000000",695 "UMask": "0x1"696 },697 {698 "AnyThread": "1",699 "BriefDescription": "Cycles Uops executed on any port (core count)",700 "Counter": "0,1,2,3",701 "CounterMask": "1",702 "EventCode": "0xB1",703 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",704 "SampleAfterValue": "2000000",705 "UMask": "0x3f"706 },707 {708 "AnyThread": "1",709 "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",710 "Counter": "0,1,2,3",711 "CounterMask": "1",712 "EventCode": "0xB1",713 "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",714 "SampleAfterValue": "2000000",715 "UMask": "0x1f"716 },717 {718 "AnyThread": "1",719 "BriefDescription": "Uops executed on any port (core count)",720 "Counter": "0,1,2,3",721 "CounterMask": "1",722 "EdgeDetect": "1",723 "EventCode": "0xB1",724 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",725 "Invert": "1",726 "SampleAfterValue": "2000000",727 "UMask": "0x3f"728 },729 {730 "AnyThread": "1",731 "BriefDescription": "Uops executed on ports 0-4 (core count)",732 "Counter": "0,1,2,3",733 "CounterMask": "1",734 "EdgeDetect": "1",735 "EventCode": "0xB1",736 "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",737 "Invert": "1",738 "SampleAfterValue": "2000000",739 "UMask": "0x1f"740 },741 {742 "AnyThread": "1",743 "BriefDescription": "Cycles no Uops issued on any port (core count)",744 "Counter": "0,1,2,3",745 "CounterMask": "1",746 "EventCode": "0xB1",747 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",748 "Invert": "1",749 "SampleAfterValue": "2000000",750 "UMask": "0x3f"751 },752 {753 "AnyThread": "1",754 "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",755 "Counter": "0,1,2,3",756 "CounterMask": "1",757 "EventCode": "0xB1",758 "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",759 "Invert": "1",760 "SampleAfterValue": "2000000",761 "UMask": "0x1f"762 },763 {764 "BriefDescription": "Uops executed on port 0",765 "Counter": "0,1,2,3",766 "EventCode": "0xB1",767 "EventName": "UOPS_EXECUTED.PORT0",768 "SampleAfterValue": "2000000",769 "UMask": "0x1"770 },771 {772 "BriefDescription": "Uops issued on ports 0, 1 or 5",773 "Counter": "0,1,2,3",774 "EventCode": "0xB1",775 "EventName": "UOPS_EXECUTED.PORT015",776 "SampleAfterValue": "2000000",777 "UMask": "0x40"778 },779 {780 "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",781 "Counter": "0,1,2,3",782 "CounterMask": "1",783 "EventCode": "0xB1",784 "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",785 "Invert": "1",786 "SampleAfterValue": "2000000",787 "UMask": "0x40"788 },789 {790 "BriefDescription": "Uops executed on port 1",791 "Counter": "0,1,2,3",792 "EventCode": "0xB1",793 "EventName": "UOPS_EXECUTED.PORT1",794 "SampleAfterValue": "2000000",795 "UMask": "0x2"796 },797 {798 "AnyThread": "1",799 "BriefDescription": "Uops issued on ports 2, 3 or 4",800 "Counter": "0,1,2,3",801 "EventCode": "0xB1",802 "EventName": "UOPS_EXECUTED.PORT234_CORE",803 "SampleAfterValue": "2000000",804 "UMask": "0x80"805 },806 {807 "AnyThread": "1",808 "BriefDescription": "Uops executed on port 2 (core count)",809 "Counter": "0,1,2,3",810 "EventCode": "0xB1",811 "EventName": "UOPS_EXECUTED.PORT2_CORE",812 "SampleAfterValue": "2000000",813 "UMask": "0x4"814 },815 {816 "AnyThread": "1",817 "BriefDescription": "Uops executed on port 3 (core count)",818 "Counter": "0,1,2,3",819 "EventCode": "0xB1",820 "EventName": "UOPS_EXECUTED.PORT3_CORE",821 "SampleAfterValue": "2000000",822 "UMask": "0x8"823 },824 {825 "AnyThread": "1",826 "BriefDescription": "Uops executed on port 4 (core count)",827 "Counter": "0,1,2,3",828 "EventCode": "0xB1",829 "EventName": "UOPS_EXECUTED.PORT4_CORE",830 "SampleAfterValue": "2000000",831 "UMask": "0x10"832 },833 {834 "BriefDescription": "Uops executed on port 5",835 "Counter": "0,1,2,3",836 "EventCode": "0xB1",837 "EventName": "UOPS_EXECUTED.PORT5",838 "SampleAfterValue": "2000000",839 "UMask": "0x20"840 },841 {842 "BriefDescription": "Uops issued",843 "Counter": "0,1,2,3",844 "EventCode": "0xE",845 "EventName": "UOPS_ISSUED.ANY",846 "SampleAfterValue": "2000000",847 "UMask": "0x1"848 },849 {850 "AnyThread": "1",851 "BriefDescription": "Cycles no Uops were issued on any thread",852 "Counter": "0,1,2,3",853 "CounterMask": "1",854 "EventCode": "0xE",855 "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",856 "Invert": "1",857 "SampleAfterValue": "2000000",858 "UMask": "0x1"859 },860 {861 "AnyThread": "1",862 "BriefDescription": "Cycles Uops were issued on either thread",863 "Counter": "0,1,2,3",864 "CounterMask": "1",865 "EventCode": "0xE",866 "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",867 "SampleAfterValue": "2000000",868 "UMask": "0x1"869 },870 {871 "BriefDescription": "Fused Uops issued",872 "Counter": "0,1,2,3",873 "EventCode": "0xE",874 "EventName": "UOPS_ISSUED.FUSED",875 "SampleAfterValue": "2000000",876 "UMask": "0x2"877 },878 {879 "BriefDescription": "Cycles no Uops were issued",880 "Counter": "0,1,2,3",881 "CounterMask": "1",882 "EventCode": "0xE",883 "EventName": "UOPS_ISSUED.STALL_CYCLES",884 "Invert": "1",885 "SampleAfterValue": "2000000",886 "UMask": "0x1"887 },888 {889 "BriefDescription": "Cycles Uops are being retired",890 "Counter": "0,1,2,3",891 "CounterMask": "1",892 "EventCode": "0xC2",893 "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",894 "PEBS": "1",895 "SampleAfterValue": "2000000",896 "UMask": "0x1"897 },898 {899 "BriefDescription": "Uops retired (Precise Event)",900 "Counter": "0,1,2,3",901 "EventCode": "0xC2",902 "EventName": "UOPS_RETIRED.ANY",903 "PEBS": "1",904 "SampleAfterValue": "2000000",905 "UMask": "0x1"906 },907 {908 "BriefDescription": "Macro-fused Uops retired (Precise Event)",909 "Counter": "0,1,2,3",910 "EventCode": "0xC2",911 "EventName": "UOPS_RETIRED.MACRO_FUSED",912 "PEBS": "1",913 "SampleAfterValue": "2000000",914 "UMask": "0x4"915 },916 {917 "BriefDescription": "Retirement slots used (Precise Event)",918 "Counter": "0,1,2,3",919 "EventCode": "0xC2",920 "EventName": "UOPS_RETIRED.RETIRE_SLOTS",921 "PEBS": "1",922 "SampleAfterValue": "2000000",923 "UMask": "0x2"924 },925 {926 "BriefDescription": "Cycles Uops are not retiring (Precise Event)",927 "Counter": "0,1,2,3",928 "CounterMask": "1",929 "EventCode": "0xC2",930 "EventName": "UOPS_RETIRED.STALL_CYCLES",931 "Invert": "1",932 "PEBS": "1",933 "SampleAfterValue": "2000000",934 "UMask": "0x1"935 },936 {937 "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",938 "Counter": "0,1,2,3",939 "CounterMask": "16",940 "EventCode": "0xC2",941 "EventName": "UOPS_RETIRED.TOTAL_CYCLES",942 "Invert": "1",943 "PEBS": "1",944 "SampleAfterValue": "2000000",945 "UMask": "0x1"946 },947 {948 "BriefDescription": "Uop unfusions due to FP exceptions",949 "Counter": "0,1,2,3",950 "EventCode": "0xDB",951 "EventName": "UOP_UNFUSION",952 "SampleAfterValue": "2000000",953 "UMask": "0x1"954 }955]956