3030 lines · json
1[2 {3 "BriefDescription": "Cycles L1D locked",4 "Counter": "0,1",5 "EventCode": "0x63",6 "EventName": "CACHE_LOCK_CYCLES.L1D",7 "SampleAfterValue": "2000000",8 "UMask": "0x2"9 },10 {11 "BriefDescription": "Cycles L1D and L2 locked",12 "Counter": "0,1",13 "EventCode": "0x63",14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2",15 "SampleAfterValue": "2000000",16 "UMask": "0x1"17 },18 {19 "BriefDescription": "L1D cache lines replaced in M state",20 "Counter": "0,1",21 "EventCode": "0x51",22 "EventName": "L1D.M_EVICT",23 "SampleAfterValue": "2000000",24 "UMask": "0x4"25 },26 {27 "BriefDescription": "L1D cache lines allocated in the M state",28 "Counter": "0,1",29 "EventCode": "0x51",30 "EventName": "L1D.M_REPL",31 "SampleAfterValue": "2000000",32 "UMask": "0x2"33 },34 {35 "BriefDescription": "L1D snoop eviction of cache lines in M state",36 "Counter": "0,1",37 "EventCode": "0x51",38 "EventName": "L1D.M_SNOOP_EVICT",39 "SampleAfterValue": "2000000",40 "UMask": "0x8"41 },42 {43 "BriefDescription": "L1 data cache lines allocated",44 "Counter": "0,1",45 "EventCode": "0x51",46 "EventName": "L1D.REPL",47 "SampleAfterValue": "2000000",48 "UMask": "0x1"49 },50 {51 "BriefDescription": "L1D prefetch load lock accepted in fill buffer",52 "Counter": "0,1",53 "EventCode": "0x52",54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",55 "SampleAfterValue": "2000000",56 "UMask": "0x1"57 },58 {59 "BriefDescription": "L1D hardware prefetch misses",60 "Counter": "0,1",61 "EventCode": "0x4E",62 "EventName": "L1D_PREFETCH.MISS",63 "SampleAfterValue": "200000",64 "UMask": "0x2"65 },66 {67 "BriefDescription": "L1D hardware prefetch requests",68 "Counter": "0,1",69 "EventCode": "0x4E",70 "EventName": "L1D_PREFETCH.REQUESTS",71 "SampleAfterValue": "200000",72 "UMask": "0x1"73 },74 {75 "BriefDescription": "L1D hardware prefetch requests triggered",76 "Counter": "0,1",77 "EventCode": "0x4E",78 "EventName": "L1D_PREFETCH.TRIGGERS",79 "SampleAfterValue": "200000",80 "UMask": "0x4"81 },82 {83 "BriefDescription": "L1 writebacks to L2 in E state",84 "Counter": "0,1,2,3",85 "EventCode": "0x28",86 "EventName": "L1D_WB_L2.E_STATE",87 "SampleAfterValue": "100000",88 "UMask": "0x4"89 },90 {91 "BriefDescription": "L1 writebacks to L2 in I state (misses)",92 "Counter": "0,1,2,3",93 "EventCode": "0x28",94 "EventName": "L1D_WB_L2.I_STATE",95 "SampleAfterValue": "100000",96 "UMask": "0x1"97 },98 {99 "BriefDescription": "All L1 writebacks to L2",100 "Counter": "0,1,2,3",101 "EventCode": "0x28",102 "EventName": "L1D_WB_L2.MESI",103 "SampleAfterValue": "100000",104 "UMask": "0xf"105 },106 {107 "BriefDescription": "L1 writebacks to L2 in M state",108 "Counter": "0,1,2,3",109 "EventCode": "0x28",110 "EventName": "L1D_WB_L2.M_STATE",111 "SampleAfterValue": "100000",112 "UMask": "0x8"113 },114 {115 "BriefDescription": "L1 writebacks to L2 in S state",116 "Counter": "0,1,2,3",117 "EventCode": "0x28",118 "EventName": "L1D_WB_L2.S_STATE",119 "SampleAfterValue": "100000",120 "UMask": "0x2"121 },122 {123 "BriefDescription": "All L2 data requests",124 "Counter": "0,1,2,3",125 "EventCode": "0x26",126 "EventName": "L2_DATA_RQSTS.ANY",127 "SampleAfterValue": "200000",128 "UMask": "0xff"129 },130 {131 "BriefDescription": "L2 data demand loads in E state",132 "Counter": "0,1,2,3",133 "EventCode": "0x26",134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",135 "SampleAfterValue": "200000",136 "UMask": "0x4"137 },138 {139 "BriefDescription": "L2 data demand loads in I state (misses)",140 "Counter": "0,1,2,3",141 "EventCode": "0x26",142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",143 "SampleAfterValue": "200000",144 "UMask": "0x1"145 },146 {147 "BriefDescription": "L2 data demand requests",148 "Counter": "0,1,2,3",149 "EventCode": "0x26",150 "EventName": "L2_DATA_RQSTS.DEMAND.MESI",151 "SampleAfterValue": "200000",152 "UMask": "0xf"153 },154 {155 "BriefDescription": "L2 data demand loads in M state",156 "Counter": "0,1,2,3",157 "EventCode": "0x26",158 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",159 "SampleAfterValue": "200000",160 "UMask": "0x8"161 },162 {163 "BriefDescription": "L2 data demand loads in S state",164 "Counter": "0,1,2,3",165 "EventCode": "0x26",166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",167 "SampleAfterValue": "200000",168 "UMask": "0x2"169 },170 {171 "BriefDescription": "L2 data prefetches in E state",172 "Counter": "0,1,2,3",173 "EventCode": "0x26",174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",175 "SampleAfterValue": "200000",176 "UMask": "0x40"177 },178 {179 "BriefDescription": "L2 data prefetches in the I state (misses)",180 "Counter": "0,1,2,3",181 "EventCode": "0x26",182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",183 "SampleAfterValue": "200000",184 "UMask": "0x10"185 },186 {187 "BriefDescription": "All L2 data prefetches",188 "Counter": "0,1,2,3",189 "EventCode": "0x26",190 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",191 "SampleAfterValue": "200000",192 "UMask": "0xf0"193 },194 {195 "BriefDescription": "L2 data prefetches in M state",196 "Counter": "0,1,2,3",197 "EventCode": "0x26",198 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",199 "SampleAfterValue": "200000",200 "UMask": "0x80"201 },202 {203 "BriefDescription": "L2 data prefetches in the S state",204 "Counter": "0,1,2,3",205 "EventCode": "0x26",206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",207 "SampleAfterValue": "200000",208 "UMask": "0x20"209 },210 {211 "BriefDescription": "L2 lines allocated",212 "Counter": "0,1,2,3",213 "EventCode": "0xF1",214 "EventName": "L2_LINES_IN.ANY",215 "SampleAfterValue": "100000",216 "UMask": "0x7"217 },218 {219 "BriefDescription": "L2 lines allocated in the E state",220 "Counter": "0,1,2,3",221 "EventCode": "0xF1",222 "EventName": "L2_LINES_IN.E_STATE",223 "SampleAfterValue": "100000",224 "UMask": "0x4"225 },226 {227 "BriefDescription": "L2 lines allocated in the S state",228 "Counter": "0,1,2,3",229 "EventCode": "0xF1",230 "EventName": "L2_LINES_IN.S_STATE",231 "SampleAfterValue": "100000",232 "UMask": "0x2"233 },234 {235 "BriefDescription": "L2 lines evicted",236 "Counter": "0,1,2,3",237 "EventCode": "0xF2",238 "EventName": "L2_LINES_OUT.ANY",239 "SampleAfterValue": "100000",240 "UMask": "0xf"241 },242 {243 "BriefDescription": "L2 lines evicted by a demand request",244 "Counter": "0,1,2,3",245 "EventCode": "0xF2",246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",247 "SampleAfterValue": "100000",248 "UMask": "0x1"249 },250 {251 "BriefDescription": "L2 modified lines evicted by a demand request",252 "Counter": "0,1,2,3",253 "EventCode": "0xF2",254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",255 "SampleAfterValue": "100000",256 "UMask": "0x2"257 },258 {259 "BriefDescription": "L2 lines evicted by a prefetch request",260 "Counter": "0,1,2,3",261 "EventCode": "0xF2",262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",263 "SampleAfterValue": "100000",264 "UMask": "0x4"265 },266 {267 "BriefDescription": "L2 modified lines evicted by a prefetch request",268 "Counter": "0,1,2,3",269 "EventCode": "0xF2",270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",271 "SampleAfterValue": "100000",272 "UMask": "0x8"273 },274 {275 "BriefDescription": "L2 instruction fetches",276 "Counter": "0,1,2,3",277 "EventCode": "0x24",278 "EventName": "L2_RQSTS.IFETCHES",279 "SampleAfterValue": "200000",280 "UMask": "0x30"281 },282 {283 "BriefDescription": "L2 instruction fetch hits",284 "Counter": "0,1,2,3",285 "EventCode": "0x24",286 "EventName": "L2_RQSTS.IFETCH_HIT",287 "SampleAfterValue": "200000",288 "UMask": "0x10"289 },290 {291 "BriefDescription": "L2 instruction fetch misses",292 "Counter": "0,1,2,3",293 "EventCode": "0x24",294 "EventName": "L2_RQSTS.IFETCH_MISS",295 "SampleAfterValue": "200000",296 "UMask": "0x20"297 },298 {299 "BriefDescription": "L2 load hits",300 "Counter": "0,1,2,3",301 "EventCode": "0x24",302 "EventName": "L2_RQSTS.LD_HIT",303 "SampleAfterValue": "200000",304 "UMask": "0x1"305 },306 {307 "BriefDescription": "L2 load misses",308 "Counter": "0,1,2,3",309 "EventCode": "0x24",310 "EventName": "L2_RQSTS.LD_MISS",311 "SampleAfterValue": "200000",312 "UMask": "0x2"313 },314 {315 "BriefDescription": "L2 requests",316 "Counter": "0,1,2,3",317 "EventCode": "0x24",318 "EventName": "L2_RQSTS.LOADS",319 "SampleAfterValue": "200000",320 "UMask": "0x3"321 },322 {323 "BriefDescription": "All L2 misses",324 "Counter": "0,1,2,3",325 "EventCode": "0x24",326 "EventName": "L2_RQSTS.MISS",327 "SampleAfterValue": "200000",328 "UMask": "0xaa"329 },330 {331 "BriefDescription": "All L2 prefetches",332 "Counter": "0,1,2,3",333 "EventCode": "0x24",334 "EventName": "L2_RQSTS.PREFETCHES",335 "SampleAfterValue": "200000",336 "UMask": "0xc0"337 },338 {339 "BriefDescription": "L2 prefetch hits",340 "Counter": "0,1,2,3",341 "EventCode": "0x24",342 "EventName": "L2_RQSTS.PREFETCH_HIT",343 "SampleAfterValue": "200000",344 "UMask": "0x40"345 },346 {347 "BriefDescription": "L2 prefetch misses",348 "Counter": "0,1,2,3",349 "EventCode": "0x24",350 "EventName": "L2_RQSTS.PREFETCH_MISS",351 "SampleAfterValue": "200000",352 "UMask": "0x80"353 },354 {355 "BriefDescription": "All L2 requests",356 "Counter": "0,1,2,3",357 "EventCode": "0x24",358 "EventName": "L2_RQSTS.REFERENCES",359 "SampleAfterValue": "200000",360 "UMask": "0xff"361 },362 {363 "BriefDescription": "L2 RFO requests",364 "Counter": "0,1,2,3",365 "EventCode": "0x24",366 "EventName": "L2_RQSTS.RFOS",367 "SampleAfterValue": "200000",368 "UMask": "0xc"369 },370 {371 "BriefDescription": "L2 RFO hits",372 "Counter": "0,1,2,3",373 "EventCode": "0x24",374 "EventName": "L2_RQSTS.RFO_HIT",375 "SampleAfterValue": "200000",376 "UMask": "0x4"377 },378 {379 "BriefDescription": "L2 RFO misses",380 "Counter": "0,1,2,3",381 "EventCode": "0x24",382 "EventName": "L2_RQSTS.RFO_MISS",383 "SampleAfterValue": "200000",384 "UMask": "0x8"385 },386 {387 "BriefDescription": "All L2 transactions",388 "Counter": "0,1,2,3",389 "EventCode": "0xF0",390 "EventName": "L2_TRANSACTIONS.ANY",391 "SampleAfterValue": "200000",392 "UMask": "0x80"393 },394 {395 "BriefDescription": "L2 fill transactions",396 "Counter": "0,1,2,3",397 "EventCode": "0xF0",398 "EventName": "L2_TRANSACTIONS.FILL",399 "SampleAfterValue": "200000",400 "UMask": "0x20"401 },402 {403 "BriefDescription": "L2 instruction fetch transactions",404 "Counter": "0,1,2,3",405 "EventCode": "0xF0",406 "EventName": "L2_TRANSACTIONS.IFETCH",407 "SampleAfterValue": "200000",408 "UMask": "0x4"409 },410 {411 "BriefDescription": "L1D writeback to L2 transactions",412 "Counter": "0,1,2,3",413 "EventCode": "0xF0",414 "EventName": "L2_TRANSACTIONS.L1D_WB",415 "SampleAfterValue": "200000",416 "UMask": "0x10"417 },418 {419 "BriefDescription": "L2 Load transactions",420 "Counter": "0,1,2,3",421 "EventCode": "0xF0",422 "EventName": "L2_TRANSACTIONS.LOAD",423 "SampleAfterValue": "200000",424 "UMask": "0x1"425 },426 {427 "BriefDescription": "L2 prefetch transactions",428 "Counter": "0,1,2,3",429 "EventCode": "0xF0",430 "EventName": "L2_TRANSACTIONS.PREFETCH",431 "SampleAfterValue": "200000",432 "UMask": "0x8"433 },434 {435 "BriefDescription": "L2 RFO transactions",436 "Counter": "0,1,2,3",437 "EventCode": "0xF0",438 "EventName": "L2_TRANSACTIONS.RFO",439 "SampleAfterValue": "200000",440 "UMask": "0x2"441 },442 {443 "BriefDescription": "L2 writeback to LLC transactions",444 "Counter": "0,1,2,3",445 "EventCode": "0xF0",446 "EventName": "L2_TRANSACTIONS.WB",447 "SampleAfterValue": "200000",448 "UMask": "0x40"449 },450 {451 "BriefDescription": "L2 demand lock RFOs in E state",452 "Counter": "0,1,2,3",453 "EventCode": "0x27",454 "EventName": "L2_WRITE.LOCK.E_STATE",455 "SampleAfterValue": "100000",456 "UMask": "0x40"457 },458 {459 "BriefDescription": "All demand L2 lock RFOs that hit the cache",460 "Counter": "0,1,2,3",461 "EventCode": "0x27",462 "EventName": "L2_WRITE.LOCK.HIT",463 "SampleAfterValue": "100000",464 "UMask": "0xe0"465 },466 {467 "BriefDescription": "L2 demand lock RFOs in I state (misses)",468 "Counter": "0,1,2,3",469 "EventCode": "0x27",470 "EventName": "L2_WRITE.LOCK.I_STATE",471 "SampleAfterValue": "100000",472 "UMask": "0x10"473 },474 {475 "BriefDescription": "All demand L2 lock RFOs",476 "Counter": "0,1,2,3",477 "EventCode": "0x27",478 "EventName": "L2_WRITE.LOCK.MESI",479 "SampleAfterValue": "100000",480 "UMask": "0xf0"481 },482 {483 "BriefDescription": "L2 demand lock RFOs in M state",484 "Counter": "0,1,2,3",485 "EventCode": "0x27",486 "EventName": "L2_WRITE.LOCK.M_STATE",487 "SampleAfterValue": "100000",488 "UMask": "0x80"489 },490 {491 "BriefDescription": "L2 demand lock RFOs in S state",492 "Counter": "0,1,2,3",493 "EventCode": "0x27",494 "EventName": "L2_WRITE.LOCK.S_STATE",495 "SampleAfterValue": "100000",496 "UMask": "0x20"497 },498 {499 "BriefDescription": "All L2 demand store RFOs that hit the cache",500 "Counter": "0,1,2,3",501 "EventCode": "0x27",502 "EventName": "L2_WRITE.RFO.HIT",503 "SampleAfterValue": "100000",504 "UMask": "0xe"505 },506 {507 "BriefDescription": "L2 demand store RFOs in I state (misses)",508 "Counter": "0,1,2,3",509 "EventCode": "0x27",510 "EventName": "L2_WRITE.RFO.I_STATE",511 "SampleAfterValue": "100000",512 "UMask": "0x1"513 },514 {515 "BriefDescription": "All L2 demand store RFOs",516 "Counter": "0,1,2,3",517 "EventCode": "0x27",518 "EventName": "L2_WRITE.RFO.MESI",519 "SampleAfterValue": "100000",520 "UMask": "0xf"521 },522 {523 "BriefDescription": "L2 demand store RFOs in M state",524 "Counter": "0,1,2,3",525 "EventCode": "0x27",526 "EventName": "L2_WRITE.RFO.M_STATE",527 "SampleAfterValue": "100000",528 "UMask": "0x8"529 },530 {531 "BriefDescription": "L2 demand store RFOs in S state",532 "Counter": "0,1,2,3",533 "EventCode": "0x27",534 "EventName": "L2_WRITE.RFO.S_STATE",535 "SampleAfterValue": "100000",536 "UMask": "0x2"537 },538 {539 "BriefDescription": "Longest latency cache miss",540 "Counter": "0,1,2,3",541 "EventCode": "0x2E",542 "EventName": "LONGEST_LAT_CACHE.MISS",543 "SampleAfterValue": "100000",544 "UMask": "0x41"545 },546 {547 "BriefDescription": "Longest latency cache reference",548 "Counter": "0,1,2,3",549 "EventCode": "0x2E",550 "EventName": "LONGEST_LAT_CACHE.REFERENCE",551 "SampleAfterValue": "200000",552 "UMask": "0x4f"553 },554 {555 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)",556 "Counter": "3",557 "EventCode": "0xB",558 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",559 "MSRIndex": "0x3F6",560 "PEBS": "2",561 "SampleAfterValue": "2000000",562 "UMask": "0x10"563 },564 {565 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)",566 "Counter": "3",567 "EventCode": "0xB",568 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",569 "MSRIndex": "0x3F6",570 "MSRValue": "0x400",571 "PEBS": "2",572 "SampleAfterValue": "100",573 "UMask": "0x10"574 },575 {576 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)",577 "Counter": "3",578 "EventCode": "0xB",579 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",580 "MSRIndex": "0x3F6",581 "MSRValue": "0x80",582 "PEBS": "2",583 "SampleAfterValue": "1000",584 "UMask": "0x10"585 },586 {587 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)",588 "Counter": "3",589 "EventCode": "0xB",590 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",591 "MSRIndex": "0x3F6",592 "MSRValue": "0x10",593 "PEBS": "2",594 "SampleAfterValue": "10000",595 "UMask": "0x10"596 },597 {598 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)",599 "Counter": "3",600 "EventCode": "0xB",601 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",602 "MSRIndex": "0x3F6",603 "MSRValue": "0x4000",604 "PEBS": "2",605 "SampleAfterValue": "5",606 "UMask": "0x10"607 },608 {609 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)",610 "Counter": "3",611 "EventCode": "0xB",612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",613 "MSRIndex": "0x3F6",614 "MSRValue": "0x800",615 "PEBS": "2",616 "SampleAfterValue": "50",617 "UMask": "0x10"618 },619 {620 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)",621 "Counter": "3",622 "EventCode": "0xB",623 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",624 "MSRIndex": "0x3F6",625 "MSRValue": "0x100",626 "PEBS": "2",627 "SampleAfterValue": "500",628 "UMask": "0x10"629 },630 {631 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)",632 "Counter": "3",633 "EventCode": "0xB",634 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",635 "MSRIndex": "0x3F6",636 "MSRValue": "0x20",637 "PEBS": "2",638 "SampleAfterValue": "5000",639 "UMask": "0x10"640 },641 {642 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)",643 "Counter": "3",644 "EventCode": "0xB",645 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",646 "MSRIndex": "0x3F6",647 "MSRValue": "0x8000",648 "PEBS": "2",649 "SampleAfterValue": "3",650 "UMask": "0x10"651 },652 {653 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)",654 "Counter": "3",655 "EventCode": "0xB",656 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",657 "MSRIndex": "0x3F6",658 "MSRValue": "0x4",659 "PEBS": "2",660 "SampleAfterValue": "50000",661 "UMask": "0x10"662 },663 {664 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)",665 "Counter": "3",666 "EventCode": "0xB",667 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",668 "MSRIndex": "0x3F6",669 "MSRValue": "0x1000",670 "PEBS": "2",671 "SampleAfterValue": "20",672 "UMask": "0x10"673 },674 {675 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)",676 "Counter": "3",677 "EventCode": "0xB",678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",679 "MSRIndex": "0x3F6",680 "MSRValue": "0x200",681 "PEBS": "2",682 "SampleAfterValue": "200",683 "UMask": "0x10"684 },685 {686 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)",687 "Counter": "3",688 "EventCode": "0xB",689 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",690 "MSRIndex": "0x3F6",691 "MSRValue": "0x40",692 "PEBS": "2",693 "SampleAfterValue": "2000",694 "UMask": "0x10"695 },696 {697 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)",698 "Counter": "3",699 "EventCode": "0xB",700 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",701 "MSRIndex": "0x3F6",702 "MSRValue": "0x8",703 "PEBS": "2",704 "SampleAfterValue": "20000",705 "UMask": "0x10"706 },707 {708 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)",709 "Counter": "3",710 "EventCode": "0xB",711 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",712 "MSRIndex": "0x3F6",713 "MSRValue": "0x2000",714 "PEBS": "2",715 "SampleAfterValue": "10",716 "UMask": "0x10"717 },718 {719 "BriefDescription": "Instructions retired which contains a load (Precise Event)",720 "Counter": "0,1,2,3",721 "EventCode": "0xB",722 "EventName": "MEM_INST_RETIRED.LOADS",723 "PEBS": "1",724 "SampleAfterValue": "2000000",725 "UMask": "0x1"726 },727 {728 "BriefDescription": "Instructions retired which contains a store (Precise Event)",729 "Counter": "0,1,2,3",730 "EventCode": "0xB",731 "EventName": "MEM_INST_RETIRED.STORES",732 "PEBS": "1",733 "SampleAfterValue": "2000000",734 "UMask": "0x2"735 },736 {737 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)",738 "Counter": "0,1,2,3",739 "EventCode": "0xCB",740 "EventName": "MEM_LOAD_RETIRED.HIT_LFB",741 "PEBS": "1",742 "SampleAfterValue": "200000",743 "UMask": "0x40"744 },745 {746 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)",747 "Counter": "0,1,2,3",748 "EventCode": "0xCB",749 "EventName": "MEM_LOAD_RETIRED.L1D_HIT",750 "PEBS": "1",751 "SampleAfterValue": "2000000",752 "UMask": "0x1"753 },754 {755 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)",756 "Counter": "0,1,2,3",757 "EventCode": "0xCB",758 "EventName": "MEM_LOAD_RETIRED.L2_HIT",759 "PEBS": "1",760 "SampleAfterValue": "200000",761 "UMask": "0x2"762 },763 {764 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)",765 "Counter": "0,1,2,3",766 "EventCode": "0xCB",767 "EventName": "MEM_LOAD_RETIRED.LLC_MISS",768 "PEBS": "1",769 "SampleAfterValue": "10000",770 "UMask": "0x10"771 },772 {773 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)",774 "Counter": "0,1,2,3",775 "EventCode": "0xCB",776 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",777 "PEBS": "1",778 "SampleAfterValue": "40000",779 "UMask": "0x4"780 },781 {782 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)",783 "Counter": "0,1,2,3",784 "EventCode": "0xCB",785 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",786 "PEBS": "1",787 "SampleAfterValue": "40000",788 "UMask": "0x8"789 },790 {791 "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)",792 "Counter": "0,1,2,3",793 "EventCode": "0xF",794 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",795 "PEBS": "1",796 "SampleAfterValue": "20000",797 "UMask": "0x8"798 },799 {800 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)",801 "Counter": "0,1,2,3",802 "EventCode": "0xF",803 "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM",804 "PEBS": "1",805 "SampleAfterValue": "40000",806 "UMask": "0x2"807 },808 {809 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)",810 "Counter": "0,1,2,3",811 "EventCode": "0xF",812 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM",813 "PEBS": "1",814 "SampleAfterValue": "10000",815 "UMask": "0x20"816 },817 {818 "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)",819 "Counter": "0,1,2,3",820 "EventCode": "0xF",821 "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM",822 "PEBS": "1",823 "SampleAfterValue": "40000",824 "UMask": "0x4"825 },826 {827 "BriefDescription": "Load instructions retired IO (Precise Event)",828 "Counter": "0,1,2,3",829 "EventCode": "0xF",830 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE",831 "PEBS": "1",832 "SampleAfterValue": "4000",833 "UMask": "0x80"834 },835 {836 "BriefDescription": "All offcore requests",837 "Counter": "0,1,2,3",838 "EventCode": "0xB0",839 "EventName": "OFFCORE_REQUESTS.ANY",840 "SampleAfterValue": "100000",841 "UMask": "0x80"842 },843 {844 "BriefDescription": "Offcore read requests",845 "Counter": "0,1,2,3",846 "EventCode": "0xB0",847 "EventName": "OFFCORE_REQUESTS.ANY.READ",848 "SampleAfterValue": "100000",849 "UMask": "0x8"850 },851 {852 "BriefDescription": "Offcore RFO requests",853 "Counter": "0,1,2,3",854 "EventCode": "0xB0",855 "EventName": "OFFCORE_REQUESTS.ANY.RFO",856 "SampleAfterValue": "100000",857 "UMask": "0x10"858 },859 {860 "BriefDescription": "Offcore demand code read requests",861 "Counter": "0,1,2,3",862 "EventCode": "0xB0",863 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",864 "SampleAfterValue": "100000",865 "UMask": "0x2"866 },867 {868 "BriefDescription": "Offcore demand data read requests",869 "Counter": "0,1,2,3",870 "EventCode": "0xB0",871 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",872 "SampleAfterValue": "100000",873 "UMask": "0x1"874 },875 {876 "BriefDescription": "Offcore demand RFO requests",877 "Counter": "0,1,2,3",878 "EventCode": "0xB0",879 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",880 "SampleAfterValue": "100000",881 "UMask": "0x4"882 },883 {884 "BriefDescription": "Offcore L1 data cache writebacks",885 "Counter": "0,1,2,3",886 "EventCode": "0xB0",887 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",888 "SampleAfterValue": "100000",889 "UMask": "0x40"890 },891 {892 "BriefDescription": "Outstanding offcore reads",893 "Counter": "0",894 "EventCode": "0x60",895 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",896 "SampleAfterValue": "2000000",897 "UMask": "0x8"898 },899 {900 "BriefDescription": "Cycles offcore reads busy",901 "Counter": "0",902 "CounterMask": "1",903 "EventCode": "0x60",904 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",905 "SampleAfterValue": "2000000",906 "UMask": "0x8"907 },908 {909 "BriefDescription": "Outstanding offcore demand code reads",910 "Counter": "0",911 "EventCode": "0x60",912 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",913 "SampleAfterValue": "2000000",914 "UMask": "0x2"915 },916 {917 "BriefDescription": "Cycles offcore demand code read busy",918 "Counter": "0",919 "CounterMask": "1",920 "EventCode": "0x60",921 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",922 "SampleAfterValue": "2000000",923 "UMask": "0x2"924 },925 {926 "BriefDescription": "Outstanding offcore demand data reads",927 "Counter": "0",928 "EventCode": "0x60",929 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",930 "SampleAfterValue": "2000000",931 "UMask": "0x1"932 },933 {934 "BriefDescription": "Cycles offcore demand data read busy",935 "Counter": "0",936 "CounterMask": "1",937 "EventCode": "0x60",938 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",939 "SampleAfterValue": "2000000",940 "UMask": "0x1"941 },942 {943 "BriefDescription": "Outstanding offcore demand RFOs",944 "Counter": "0",945 "EventCode": "0x60",946 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",947 "SampleAfterValue": "2000000",948 "UMask": "0x4"949 },950 {951 "BriefDescription": "Cycles offcore demand RFOs busy",952 "Counter": "0",953 "CounterMask": "1",954 "EventCode": "0x60",955 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",956 "SampleAfterValue": "2000000",957 "UMask": "0x4"958 },959 {960 "BriefDescription": "Offcore requests blocked due to Super Queue full",961 "Counter": "0,1,2,3",962 "EventCode": "0xB2",963 "EventName": "OFFCORE_REQUESTS_SQ_FULL",964 "SampleAfterValue": "100000",965 "UMask": "0x1"966 },967 {968 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM",969 "Counter": "2",970 "EventCode": "0xB7",971 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",972 "MSRIndex": "0x1A6",973 "MSRValue": "0x7F11",974 "SampleAfterValue": "100000",975 "UMask": "0x1"976 },977 {978 "BriefDescription": "All offcore data reads",979 "Counter": "2",980 "EventCode": "0xB7",981 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",982 "MSRIndex": "0x1A6",983 "MSRValue": "0xFF11",984 "SampleAfterValue": "100000",985 "UMask": "0x1"986 },987 {988 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit",989 "Counter": "2",990 "EventCode": "0xB7",991 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",992 "MSRIndex": "0x1A6",993 "MSRValue": "0x8011",994 "SampleAfterValue": "100000",995 "UMask": "0x1"996 },997 {998 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core",999 "Counter": "2",1000 "EventCode": "0xB7",1001 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",1002 "MSRIndex": "0x1A6",1003 "MSRValue": "0x111",1004 "SampleAfterValue": "100000",1005 "UMask": "0x1"1006 },1007 {1008 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core",1009 "Counter": "2",1010 "EventCode": "0xB7",1011 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",1012 "MSRIndex": "0x1A6",1013 "MSRValue": "0x211",1014 "SampleAfterValue": "100000",1015 "UMask": "0x1"1016 },1017 {1018 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core",1019 "Counter": "2",1020 "EventCode": "0xB7",1021 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",1022 "MSRIndex": "0x1A6",1023 "MSRValue": "0x411",1024 "SampleAfterValue": "100000",1025 "UMask": "0x1"1026 },1027 {1028 "BriefDescription": "Offcore data reads satisfied by the LLC",1029 "Counter": "2",1030 "EventCode": "0xB7",1031 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",1032 "MSRIndex": "0x1A6",1033 "MSRValue": "0x711",1034 "SampleAfterValue": "100000",1035 "UMask": "0x1"1036 },1037 {1038 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM",1039 "Counter": "2",1040 "EventCode": "0xB7",1041 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM",1042 "MSRIndex": "0x1A6",1043 "MSRValue": "0x4711",1044 "SampleAfterValue": "100000",1045 "UMask": "0x1"1046 },1047 {1048 "BriefDescription": "Offcore data reads satisfied by a remote cache",1049 "Counter": "2",1050 "EventCode": "0xB7",1051 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE",1052 "MSRIndex": "0x1A6",1053 "MSRValue": "0x1811",1054 "SampleAfterValue": "100000",1055 "UMask": "0x1"1056 },1057 {1058 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM",1059 "Counter": "2",1060 "EventCode": "0xB7",1061 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM",1062 "MSRIndex": "0x1A6",1063 "MSRValue": "0x3811",1064 "SampleAfterValue": "100000",1065 "UMask": "0x1"1066 },1067 {1068 "BriefDescription": "Offcore data reads that HIT in a remote cache",1069 "Counter": "2",1070 "EventCode": "0xB7",1071 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT",1072 "MSRIndex": "0x1A6",1073 "MSRValue": "0x1011",1074 "SampleAfterValue": "100000",1075 "UMask": "0x1"1076 },1077 {1078 "BriefDescription": "Offcore data reads that HITM in a remote cache",1079 "Counter": "2",1080 "EventCode": "0xB7",1081 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",1082 "MSRIndex": "0x1A6",1083 "MSRValue": "0x811",1084 "SampleAfterValue": "100000",1085 "UMask": "0x1"1086 },1087 {1088 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM",1089 "Counter": "2",1090 "EventCode": "0xB7",1091 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",1092 "MSRIndex": "0x1A6",1093 "MSRValue": "0x7F44",1094 "SampleAfterValue": "100000",1095 "UMask": "0x1"1096 },1097 {1098 "BriefDescription": "All offcore code reads",1099 "Counter": "2",1100 "EventCode": "0xB7",1101 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",1102 "MSRIndex": "0x1A6",1103 "MSRValue": "0xFF44",1104 "SampleAfterValue": "100000",1105 "UMask": "0x1"1106 },1107 {1108 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit",1109 "Counter": "2",1110 "EventCode": "0xB7",1111 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",1112 "MSRIndex": "0x1A6",1113 "MSRValue": "0x8044",1114 "SampleAfterValue": "100000",1115 "UMask": "0x1"1116 },1117 {1118 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core",1119 "Counter": "2",1120 "EventCode": "0xB7",1121 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",1122 "MSRIndex": "0x1A6",1123 "MSRValue": "0x144",1124 "SampleAfterValue": "100000",1125 "UMask": "0x1"1126 },1127 {1128 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core",1129 "Counter": "2",1130 "EventCode": "0xB7",1131 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",1132 "MSRIndex": "0x1A6",1133 "MSRValue": "0x244",1134 "SampleAfterValue": "100000",1135 "UMask": "0x1"1136 },1137 {1138 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core",1139 "Counter": "2",1140 "EventCode": "0xB7",1141 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",1142 "MSRIndex": "0x1A6",1143 "MSRValue": "0x444",1144 "SampleAfterValue": "100000",1145 "UMask": "0x1"1146 },1147 {1148 "BriefDescription": "Offcore code reads satisfied by the LLC",1149 "Counter": "2",1150 "EventCode": "0xB7",1151 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",1152 "MSRIndex": "0x1A6",1153 "MSRValue": "0x744",1154 "SampleAfterValue": "100000",1155 "UMask": "0x1"1156 },1157 {1158 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM",1159 "Counter": "2",1160 "EventCode": "0xB7",1161 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM",1162 "MSRIndex": "0x1A6",1163 "MSRValue": "0x4744",1164 "SampleAfterValue": "100000",1165 "UMask": "0x1"1166 },1167 {1168 "BriefDescription": "Offcore code reads satisfied by a remote cache",1169 "Counter": "2",1170 "EventCode": "0xB7",1171 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE",1172 "MSRIndex": "0x1A6",1173 "MSRValue": "0x1844",1174 "SampleAfterValue": "100000",1175 "UMask": "0x1"1176 },1177 {1178 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM",1179 "Counter": "2",1180 "EventCode": "0xB7",1181 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM",1182 "MSRIndex": "0x1A6",1183 "MSRValue": "0x3844",1184 "SampleAfterValue": "100000",1185 "UMask": "0x1"1186 },1187 {1188 "BriefDescription": "Offcore code reads that HIT in a remote cache",1189 "Counter": "2",1190 "EventCode": "0xB7",1191 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT",1192 "MSRIndex": "0x1A6",1193 "MSRValue": "0x1044",1194 "SampleAfterValue": "100000",1195 "UMask": "0x1"1196 },1197 {1198 "BriefDescription": "Offcore code reads that HITM in a remote cache",1199 "Counter": "2",1200 "EventCode": "0xB7",1201 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",1202 "MSRIndex": "0x1A6",1203 "MSRValue": "0x844",1204 "SampleAfterValue": "100000",1205 "UMask": "0x1"1206 },1207 {1208 "BriefDescription": "Offcore requests satisfied by any cache or DRAM",1209 "Counter": "2",1210 "EventCode": "0xB7",1211 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",1212 "MSRIndex": "0x1A6",1213 "MSRValue": "0x7FFF",1214 "SampleAfterValue": "100000",1215 "UMask": "0x1"1216 },1217 {1218 "BriefDescription": "All offcore requests",1219 "Counter": "2",1220 "EventCode": "0xB7",1221 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",1222 "MSRIndex": "0x1A6",1223 "MSRValue": "0xFFFF",1224 "SampleAfterValue": "100000",1225 "UMask": "0x1"1226 },1227 {1228 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit",1229 "Counter": "2",1230 "EventCode": "0xB7",1231 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",1232 "MSRIndex": "0x1A6",1233 "MSRValue": "0x80FF",1234 "SampleAfterValue": "100000",1235 "UMask": "0x1"1236 },1237 {1238 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core",1239 "Counter": "2",1240 "EventCode": "0xB7",1241 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",1242 "MSRIndex": "0x1A6",1243 "MSRValue": "0x1FF",1244 "SampleAfterValue": "100000",1245 "UMask": "0x1"1246 },1247 {1248 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core",1249 "Counter": "2",1250 "EventCode": "0xB7",1251 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",1252 "MSRIndex": "0x1A6",1253 "MSRValue": "0x2FF",1254 "SampleAfterValue": "100000",1255 "UMask": "0x1"1256 },1257 {1258 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core",1259 "Counter": "2",1260 "EventCode": "0xB7",1261 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",1262 "MSRIndex": "0x1A6",1263 "MSRValue": "0x4FF",1264 "SampleAfterValue": "100000",1265 "UMask": "0x1"1266 },1267 {1268 "BriefDescription": "Offcore requests satisfied by the LLC",1269 "Counter": "2",1270 "EventCode": "0xB7",1271 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",1272 "MSRIndex": "0x1A6",1273 "MSRValue": "0x7FF",1274 "SampleAfterValue": "100000",1275 "UMask": "0x1"1276 },1277 {1278 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM",1279 "Counter": "2",1280 "EventCode": "0xB7",1281 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM",1282 "MSRIndex": "0x1A6",1283 "MSRValue": "0x47FF",1284 "SampleAfterValue": "100000",1285 "UMask": "0x1"1286 },1287 {1288 "BriefDescription": "Offcore requests satisfied by a remote cache",1289 "Counter": "2",1290 "EventCode": "0xB7",1291 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE",1292 "MSRIndex": "0x1A6",1293 "MSRValue": "0x18FF",1294 "SampleAfterValue": "100000",1295 "UMask": "0x1"1296 },1297 {1298 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM",1299 "Counter": "2",1300 "EventCode": "0xB7",1301 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM",1302 "MSRIndex": "0x1A6",1303 "MSRValue": "0x38FF",1304 "SampleAfterValue": "100000",1305 "UMask": "0x1"1306 },1307 {1308 "BriefDescription": "Offcore requests that HIT in a remote cache",1309 "Counter": "2",1310 "EventCode": "0xB7",1311 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT",1312 "MSRIndex": "0x1A6",1313 "MSRValue": "0x10FF",1314 "SampleAfterValue": "100000",1315 "UMask": "0x1"1316 },1317 {1318 "BriefDescription": "Offcore requests that HITM in a remote cache",1319 "Counter": "2",1320 "EventCode": "0xB7",1321 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",1322 "MSRIndex": "0x1A6",1323 "MSRValue": "0x8FF",1324 "SampleAfterValue": "100000",1325 "UMask": "0x1"1326 },1327 {1328 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM",1329 "Counter": "2",1330 "EventCode": "0xB7",1331 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",1332 "MSRIndex": "0x1A6",1333 "MSRValue": "0x7F22",1334 "SampleAfterValue": "100000",1335 "UMask": "0x1"1336 },1337 {1338 "BriefDescription": "All offcore RFO requests",1339 "Counter": "2",1340 "EventCode": "0xB7",1341 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",1342 "MSRIndex": "0x1A6",1343 "MSRValue": "0xFF22",1344 "SampleAfterValue": "100000",1345 "UMask": "0x1"1346 },1347 {1348 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit",1349 "Counter": "2",1350 "EventCode": "0xB7",1351 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",1352 "MSRIndex": "0x1A6",1353 "MSRValue": "0x8022",1354 "SampleAfterValue": "100000",1355 "UMask": "0x1"1356 },1357 {1358 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core",1359 "Counter": "2",1360 "EventCode": "0xB7",1361 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",1362 "MSRIndex": "0x1A6",1363 "MSRValue": "0x122",1364 "SampleAfterValue": "100000",1365 "UMask": "0x1"1366 },1367 {1368 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core",1369 "Counter": "2",1370 "EventCode": "0xB7",1371 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",1372 "MSRIndex": "0x1A6",1373 "MSRValue": "0x222",1374 "SampleAfterValue": "100000",1375 "UMask": "0x1"1376 },1377 {1378 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core",1379 "Counter": "2",1380 "EventCode": "0xB7",1381 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",1382 "MSRIndex": "0x1A6",1383 "MSRValue": "0x422",1384 "SampleAfterValue": "100000",1385 "UMask": "0x1"1386 },1387 {1388 "BriefDescription": "Offcore RFO requests satisfied by the LLC",1389 "Counter": "2",1390 "EventCode": "0xB7",1391 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",1392 "MSRIndex": "0x1A6",1393 "MSRValue": "0x722",1394 "SampleAfterValue": "100000",1395 "UMask": "0x1"1396 },1397 {1398 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM",1399 "Counter": "2",1400 "EventCode": "0xB7",1401 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM",1402 "MSRIndex": "0x1A6",1403 "MSRValue": "0x4722",1404 "SampleAfterValue": "100000",1405 "UMask": "0x1"1406 },1407 {1408 "BriefDescription": "Offcore RFO requests satisfied by a remote cache",1409 "Counter": "2",1410 "EventCode": "0xB7",1411 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE",1412 "MSRIndex": "0x1A6",1413 "MSRValue": "0x1822",1414 "SampleAfterValue": "100000",1415 "UMask": "0x1"1416 },1417 {1418 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM",1419 "Counter": "2",1420 "EventCode": "0xB7",1421 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM",1422 "MSRIndex": "0x1A6",1423 "MSRValue": "0x3822",1424 "SampleAfterValue": "100000",1425 "UMask": "0x1"1426 },1427 {1428 "BriefDescription": "Offcore RFO requests that HIT in a remote cache",1429 "Counter": "2",1430 "EventCode": "0xB7",1431 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT",1432 "MSRIndex": "0x1A6",1433 "MSRValue": "0x1022",1434 "SampleAfterValue": "100000",1435 "UMask": "0x1"1436 },1437 {1438 "BriefDescription": "Offcore RFO requests that HITM in a remote cache",1439 "Counter": "2",1440 "EventCode": "0xB7",1441 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",1442 "MSRIndex": "0x1A6",1443 "MSRValue": "0x822",1444 "SampleAfterValue": "100000",1445 "UMask": "0x1"1446 },1447 {1448 "BriefDescription": "Offcore writebacks to any cache or DRAM.",1449 "Counter": "2",1450 "EventCode": "0xB7",1451 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",1452 "MSRIndex": "0x1A6",1453 "MSRValue": "0x7F08",1454 "SampleAfterValue": "100000",1455 "UMask": "0x1"1456 },1457 {1458 "BriefDescription": "All offcore writebacks",1459 "Counter": "2",1460 "EventCode": "0xB7",1461 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",1462 "MSRIndex": "0x1A6",1463 "MSRValue": "0xFF08",1464 "SampleAfterValue": "100000",1465 "UMask": "0x1"1466 },1467 {1468 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.",1469 "Counter": "2",1470 "EventCode": "0xB7",1471 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",1472 "MSRIndex": "0x1A6",1473 "MSRValue": "0x8008",1474 "SampleAfterValue": "100000",1475 "UMask": "0x1"1476 },1477 {1478 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core",1479 "Counter": "2",1480 "EventCode": "0xB7",1481 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",1482 "MSRIndex": "0x1A6",1483 "MSRValue": "0x108",1484 "SampleAfterValue": "100000",1485 "UMask": "0x1"1486 },1487 {1488 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core",1489 "Counter": "2",1490 "EventCode": "0xB7",1491 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",1492 "MSRIndex": "0x1A6",1493 "MSRValue": "0x408",1494 "SampleAfterValue": "100000",1495 "UMask": "0x1"1496 },1497 {1498 "BriefDescription": "Offcore writebacks to the LLC",1499 "Counter": "2",1500 "EventCode": "0xB7",1501 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",1502 "MSRIndex": "0x1A6",1503 "MSRValue": "0x708",1504 "SampleAfterValue": "100000",1505 "UMask": "0x1"1506 },1507 {1508 "BriefDescription": "Offcore writebacks to the LLC or local DRAM",1509 "Counter": "2",1510 "EventCode": "0xB7",1511 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM",1512 "MSRIndex": "0x1A6",1513 "MSRValue": "0x4708",1514 "SampleAfterValue": "100000",1515 "UMask": "0x1"1516 },1517 {1518 "BriefDescription": "Offcore writebacks to a remote cache",1519 "Counter": "2",1520 "EventCode": "0xB7",1521 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE",1522 "MSRIndex": "0x1A6",1523 "MSRValue": "0x1808",1524 "SampleAfterValue": "100000",1525 "UMask": "0x1"1526 },1527 {1528 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM",1529 "Counter": "2",1530 "EventCode": "0xB7",1531 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM",1532 "MSRIndex": "0x1A6",1533 "MSRValue": "0x3808",1534 "SampleAfterValue": "100000",1535 "UMask": "0x1"1536 },1537 {1538 "BriefDescription": "Offcore writebacks that HIT in a remote cache",1539 "Counter": "2",1540 "EventCode": "0xB7",1541 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT",1542 "MSRIndex": "0x1A6",1543 "MSRValue": "0x1008",1544 "SampleAfterValue": "100000",1545 "UMask": "0x1"1546 },1547 {1548 "BriefDescription": "Offcore writebacks that HITM in a remote cache",1549 "Counter": "2",1550 "EventCode": "0xB7",1551 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",1552 "MSRIndex": "0x1A6",1553 "MSRValue": "0x808",1554 "SampleAfterValue": "100000",1555 "UMask": "0x1"1556 },1557 {1558 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.",1559 "Counter": "2",1560 "EventCode": "0xB7",1561 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",1562 "MSRIndex": "0x1A6",1563 "MSRValue": "0x7F77",1564 "SampleAfterValue": "100000",1565 "UMask": "0x1"1566 },1567 {1568 "BriefDescription": "All offcore code or data read requests",1569 "Counter": "2",1570 "EventCode": "0xB7",1571 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",1572 "MSRIndex": "0x1A6",1573 "MSRValue": "0xFF77",1574 "SampleAfterValue": "100000",1575 "UMask": "0x1"1576 },1577 {1578 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.",1579 "Counter": "2",1580 "EventCode": "0xB7",1581 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",1582 "MSRIndex": "0x1A6",1583 "MSRValue": "0x8077",1584 "SampleAfterValue": "100000",1585 "UMask": "0x1"1586 },1587 {1588 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core",1589 "Counter": "2",1590 "EventCode": "0xB7",1591 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",1592 "MSRIndex": "0x1A6",1593 "MSRValue": "0x177",1594 "SampleAfterValue": "100000",1595 "UMask": "0x1"1596 },1597 {1598 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core",1599 "Counter": "2",1600 "EventCode": "0xB7",1601 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",1602 "MSRIndex": "0x1A6",1603 "MSRValue": "0x277",1604 "SampleAfterValue": "100000",1605 "UMask": "0x1"1606 },1607 {1608 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core",1609 "Counter": "2",1610 "EventCode": "0xB7",1611 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",1612 "MSRIndex": "0x1A6",1613 "MSRValue": "0x477",1614 "SampleAfterValue": "100000",1615 "UMask": "0x1"1616 },1617 {1618 "BriefDescription": "Offcore code or data read requests satisfied by the LLC",1619 "Counter": "2",1620 "EventCode": "0xB7",1621 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",1622 "MSRIndex": "0x1A6",1623 "MSRValue": "0x777",1624 "SampleAfterValue": "100000",1625 "UMask": "0x1"1626 },1627 {1628 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM",1629 "Counter": "2",1630 "EventCode": "0xB7",1631 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM",1632 "MSRIndex": "0x1A6",1633 "MSRValue": "0x4777",1634 "SampleAfterValue": "100000",1635 "UMask": "0x1"1636 },1637 {1638 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache",1639 "Counter": "2",1640 "EventCode": "0xB7",1641 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE",1642 "MSRIndex": "0x1A6",1643 "MSRValue": "0x1877",1644 "SampleAfterValue": "100000",1645 "UMask": "0x1"1646 },1647 {1648 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM",1649 "Counter": "2",1650 "EventCode": "0xB7",1651 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM",1652 "MSRIndex": "0x1A6",1653 "MSRValue": "0x3877",1654 "SampleAfterValue": "100000",1655 "UMask": "0x1"1656 },1657 {1658 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache",1659 "Counter": "2",1660 "EventCode": "0xB7",1661 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT",1662 "MSRIndex": "0x1A6",1663 "MSRValue": "0x1077",1664 "SampleAfterValue": "100000",1665 "UMask": "0x1"1666 },1667 {1668 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache",1669 "Counter": "2",1670 "EventCode": "0xB7",1671 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",1672 "MSRIndex": "0x1A6",1673 "MSRValue": "0x877",1674 "SampleAfterValue": "100000",1675 "UMask": "0x1"1676 },1677 {1678 "BriefDescription": "Offcore request = all data, response = any cache_dram",1679 "Counter": "2",1680 "EventCode": "0xB7",1681 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",1682 "MSRIndex": "0x1A6",1683 "MSRValue": "0x7F33",1684 "SampleAfterValue": "100000",1685 "UMask": "0x1"1686 },1687 {1688 "BriefDescription": "Offcore request = all data, response = any location",1689 "Counter": "2",1690 "EventCode": "0xB7",1691 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",1692 "MSRIndex": "0x1A6",1693 "MSRValue": "0xFF33",1694 "SampleAfterValue": "100000",1695 "UMask": "0x1"1696 },1697 {1698 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit",1699 "Counter": "2",1700 "EventCode": "0xB7",1701 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",1702 "MSRIndex": "0x1A6",1703 "MSRValue": "0x8033",1704 "SampleAfterValue": "100000",1705 "UMask": "0x1"1706 },1707 {1708 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core",1709 "Counter": "2",1710 "EventCode": "0xB7",1711 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",1712 "MSRIndex": "0x1A6",1713 "MSRValue": "0x133",1714 "SampleAfterValue": "100000",1715 "UMask": "0x1"1716 },1717 {1718 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core",1719 "Counter": "2",1720 "EventCode": "0xB7",1721 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",1722 "MSRIndex": "0x1A6",1723 "MSRValue": "0x233",1724 "SampleAfterValue": "100000",1725 "UMask": "0x1"1726 },1727 {1728 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core",1729 "Counter": "2",1730 "EventCode": "0xB7",1731 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",1732 "MSRIndex": "0x1A6",1733 "MSRValue": "0x433",1734 "SampleAfterValue": "100000",1735 "UMask": "0x1"1736 },1737 {1738 "BriefDescription": "Offcore request = all data, response = local cache",1739 "Counter": "2",1740 "EventCode": "0xB7",1741 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",1742 "MSRIndex": "0x1A6",1743 "MSRValue": "0x733",1744 "SampleAfterValue": "100000",1745 "UMask": "0x1"1746 },1747 {1748 "BriefDescription": "Offcore request = all data, response = local cache or dram",1749 "Counter": "2",1750 "EventCode": "0xB7",1751 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM",1752 "MSRIndex": "0x1A6",1753 "MSRValue": "0x4733",1754 "SampleAfterValue": "100000",1755 "UMask": "0x1"1756 },1757 {1758 "BriefDescription": "Offcore request = all data, response = remote cache",1759 "Counter": "2",1760 "EventCode": "0xB7",1761 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE",1762 "MSRIndex": "0x1A6",1763 "MSRValue": "0x1833",1764 "SampleAfterValue": "100000",1765 "UMask": "0x1"1766 },1767 {1768 "BriefDescription": "Offcore request = all data, response = remote cache or dram",1769 "Counter": "2",1770 "EventCode": "0xB7",1771 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM",1772 "MSRIndex": "0x1A6",1773 "MSRValue": "0x3833",1774 "SampleAfterValue": "100000",1775 "UMask": "0x1"1776 },1777 {1778 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache",1779 "Counter": "2",1780 "EventCode": "0xB7",1781 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT",1782 "MSRIndex": "0x1A6",1783 "MSRValue": "0x1033",1784 "SampleAfterValue": "100000",1785 "UMask": "0x1"1786 },1787 {1788 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache",1789 "Counter": "2",1790 "EventCode": "0xB7",1791 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",1792 "MSRIndex": "0x1A6",1793 "MSRValue": "0x833",1794 "SampleAfterValue": "100000",1795 "UMask": "0x1"1796 },1797 {1798 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM",1799 "Counter": "2",1800 "EventCode": "0xB7",1801 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",1802 "MSRIndex": "0x1A6",1803 "MSRValue": "0x7F03",1804 "SampleAfterValue": "100000",1805 "UMask": "0x1"1806 },1807 {1808 "BriefDescription": "All offcore demand data requests",1809 "Counter": "2",1810 "EventCode": "0xB7",1811 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",1812 "MSRIndex": "0x1A6",1813 "MSRValue": "0xFF03",1814 "SampleAfterValue": "100000",1815 "UMask": "0x1"1816 },1817 {1818 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.",1819 "Counter": "2",1820 "EventCode": "0xB7",1821 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",1822 "MSRIndex": "0x1A6",1823 "MSRValue": "0x8003",1824 "SampleAfterValue": "100000",1825 "UMask": "0x1"1826 },1827 {1828 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core",1829 "Counter": "2",1830 "EventCode": "0xB7",1831 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",1832 "MSRIndex": "0x1A6",1833 "MSRValue": "0x103",1834 "SampleAfterValue": "100000",1835 "UMask": "0x1"1836 },1837 {1838 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core",1839 "Counter": "2",1840 "EventCode": "0xB7",1841 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",1842 "MSRIndex": "0x1A6",1843 "MSRValue": "0x203",1844 "SampleAfterValue": "100000",1845 "UMask": "0x1"1846 },1847 {1848 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core",1849 "Counter": "2",1850 "EventCode": "0xB7",1851 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",1852 "MSRIndex": "0x1A6",1853 "MSRValue": "0x403",1854 "SampleAfterValue": "100000",1855 "UMask": "0x1"1856 },1857 {1858 "BriefDescription": "Offcore demand data requests satisfied by the LLC",1859 "Counter": "2",1860 "EventCode": "0xB7",1861 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",1862 "MSRIndex": "0x1A6",1863 "MSRValue": "0x703",1864 "SampleAfterValue": "100000",1865 "UMask": "0x1"1866 },1867 {1868 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM",1869 "Counter": "2",1870 "EventCode": "0xB7",1871 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM",1872 "MSRIndex": "0x1A6",1873 "MSRValue": "0x4703",1874 "SampleAfterValue": "100000",1875 "UMask": "0x1"1876 },1877 {1878 "BriefDescription": "Offcore demand data requests satisfied by a remote cache",1879 "Counter": "2",1880 "EventCode": "0xB7",1881 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE",1882 "MSRIndex": "0x1A6",1883 "MSRValue": "0x1803",1884 "SampleAfterValue": "100000",1885 "UMask": "0x1"1886 },1887 {1888 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM",1889 "Counter": "2",1890 "EventCode": "0xB7",1891 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM",1892 "MSRIndex": "0x1A6",1893 "MSRValue": "0x3803",1894 "SampleAfterValue": "100000",1895 "UMask": "0x1"1896 },1897 {1898 "BriefDescription": "Offcore demand data requests that HIT in a remote cache",1899 "Counter": "2",1900 "EventCode": "0xB7",1901 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT",1902 "MSRIndex": "0x1A6",1903 "MSRValue": "0x1003",1904 "SampleAfterValue": "100000",1905 "UMask": "0x1"1906 },1907 {1908 "BriefDescription": "Offcore demand data requests that HITM in a remote cache",1909 "Counter": "2",1910 "EventCode": "0xB7",1911 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",1912 "MSRIndex": "0x1A6",1913 "MSRValue": "0x803",1914 "SampleAfterValue": "100000",1915 "UMask": "0x1"1916 },1917 {1918 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.",1919 "Counter": "2",1920 "EventCode": "0xB7",1921 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",1922 "MSRIndex": "0x1A6",1923 "MSRValue": "0x7F01",1924 "SampleAfterValue": "100000",1925 "UMask": "0x1"1926 },1927 {1928 "BriefDescription": "All offcore demand data reads",1929 "Counter": "2",1930 "EventCode": "0xB7",1931 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",1932 "MSRIndex": "0x1A6",1933 "MSRValue": "0xFF01",1934 "SampleAfterValue": "100000",1935 "UMask": "0x1"1936 },1937 {1938 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit",1939 "Counter": "2",1940 "EventCode": "0xB7",1941 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",1942 "MSRIndex": "0x1A6",1943 "MSRValue": "0x8001",1944 "SampleAfterValue": "100000",1945 "UMask": "0x1"1946 },1947 {1948 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core",1949 "Counter": "2",1950 "EventCode": "0xB7",1951 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",1952 "MSRIndex": "0x1A6",1953 "MSRValue": "0x101",1954 "SampleAfterValue": "100000",1955 "UMask": "0x1"1956 },1957 {1958 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core",1959 "Counter": "2",1960 "EventCode": "0xB7",1961 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",1962 "MSRIndex": "0x1A6",1963 "MSRValue": "0x201",1964 "SampleAfterValue": "100000",1965 "UMask": "0x1"1966 },1967 {1968 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core",1969 "Counter": "2",1970 "EventCode": "0xB7",1971 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",1972 "MSRIndex": "0x1A6",1973 "MSRValue": "0x401",1974 "SampleAfterValue": "100000",1975 "UMask": "0x1"1976 },1977 {1978 "BriefDescription": "Offcore demand data reads satisfied by the LLC",1979 "Counter": "2",1980 "EventCode": "0xB7",1981 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",1982 "MSRIndex": "0x1A6",1983 "MSRValue": "0x701",1984 "SampleAfterValue": "100000",1985 "UMask": "0x1"1986 },1987 {1988 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM",1989 "Counter": "2",1990 "EventCode": "0xB7",1991 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM",1992 "MSRIndex": "0x1A6",1993 "MSRValue": "0x4701",1994 "SampleAfterValue": "100000",1995 "UMask": "0x1"1996 },1997 {1998 "BriefDescription": "Offcore demand data reads satisfied by a remote cache",1999 "Counter": "2",2000 "EventCode": "0xB7",2001 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE",2002 "MSRIndex": "0x1A6",2003 "MSRValue": "0x1801",2004 "SampleAfterValue": "100000",2005 "UMask": "0x1"2006 },2007 {2008 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM",2009 "Counter": "2",2010 "EventCode": "0xB7",2011 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM",2012 "MSRIndex": "0x1A6",2013 "MSRValue": "0x3801",2014 "SampleAfterValue": "100000",2015 "UMask": "0x1"2016 },2017 {2018 "BriefDescription": "Offcore demand data reads that HIT in a remote cache",2019 "Counter": "2",2020 "EventCode": "0xB7",2021 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT",2022 "MSRIndex": "0x1A6",2023 "MSRValue": "0x1001",2024 "SampleAfterValue": "100000",2025 "UMask": "0x1"2026 },2027 {2028 "BriefDescription": "Offcore demand data reads that HITM in a remote cache",2029 "Counter": "2",2030 "EventCode": "0xB7",2031 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",2032 "MSRIndex": "0x1A6",2033 "MSRValue": "0x801",2034 "SampleAfterValue": "100000",2035 "UMask": "0x1"2036 },2037 {2038 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.",2039 "Counter": "2",2040 "EventCode": "0xB7",2041 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",2042 "MSRIndex": "0x1A6",2043 "MSRValue": "0x7F04",2044 "SampleAfterValue": "100000",2045 "UMask": "0x1"2046 },2047 {2048 "BriefDescription": "All offcore demand code reads",2049 "Counter": "2",2050 "EventCode": "0xB7",2051 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",2052 "MSRIndex": "0x1A6",2053 "MSRValue": "0xFF04",2054 "SampleAfterValue": "100000",2055 "UMask": "0x1"2056 },2057 {2058 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit",2059 "Counter": "2",2060 "EventCode": "0xB7",2061 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",2062 "MSRIndex": "0x1A6",2063 "MSRValue": "0x8004",2064 "SampleAfterValue": "100000",2065 "UMask": "0x1"2066 },2067 {2068 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core",2069 "Counter": "2",2070 "EventCode": "0xB7",2071 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",2072 "MSRIndex": "0x1A6",2073 "MSRValue": "0x104",2074 "SampleAfterValue": "100000",2075 "UMask": "0x1"2076 },2077 {2078 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core",2079 "Counter": "2",2080 "EventCode": "0xB7",2081 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",2082 "MSRIndex": "0x1A6",2083 "MSRValue": "0x204",2084 "SampleAfterValue": "100000",2085 "UMask": "0x1"2086 },2087 {2088 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core",2089 "Counter": "2",2090 "EventCode": "0xB7",2091 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",2092 "MSRIndex": "0x1A6",2093 "MSRValue": "0x404",2094 "SampleAfterValue": "100000",2095 "UMask": "0x1"2096 },2097 {2098 "BriefDescription": "Offcore demand code reads satisfied by the LLC",2099 "Counter": "2",2100 "EventCode": "0xB7",2101 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",2102 "MSRIndex": "0x1A6",2103 "MSRValue": "0x704",2104 "SampleAfterValue": "100000",2105 "UMask": "0x1"2106 },2107 {2108 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM",2109 "Counter": "2",2110 "EventCode": "0xB7",2111 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM",2112 "MSRIndex": "0x1A6",2113 "MSRValue": "0x4704",2114 "SampleAfterValue": "100000",2115 "UMask": "0x1"2116 },2117 {2118 "BriefDescription": "Offcore demand code reads satisfied by a remote cache",2119 "Counter": "2",2120 "EventCode": "0xB7",2121 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE",2122 "MSRIndex": "0x1A6",2123 "MSRValue": "0x1804",2124 "SampleAfterValue": "100000",2125 "UMask": "0x1"2126 },2127 {2128 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM",2129 "Counter": "2",2130 "EventCode": "0xB7",2131 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM",2132 "MSRIndex": "0x1A6",2133 "MSRValue": "0x3804",2134 "SampleAfterValue": "100000",2135 "UMask": "0x1"2136 },2137 {2138 "BriefDescription": "Offcore demand code reads that HIT in a remote cache",2139 "Counter": "2",2140 "EventCode": "0xB7",2141 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT",2142 "MSRIndex": "0x1A6",2143 "MSRValue": "0x1004",2144 "SampleAfterValue": "100000",2145 "UMask": "0x1"2146 },2147 {2148 "BriefDescription": "Offcore demand code reads that HITM in a remote cache",2149 "Counter": "2",2150 "EventCode": "0xB7",2151 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",2152 "MSRIndex": "0x1A6",2153 "MSRValue": "0x804",2154 "SampleAfterValue": "100000",2155 "UMask": "0x1"2156 },2157 {2158 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.",2159 "Counter": "2",2160 "EventCode": "0xB7",2161 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",2162 "MSRIndex": "0x1A6",2163 "MSRValue": "0x7F02",2164 "SampleAfterValue": "100000",2165 "UMask": "0x1"2166 },2167 {2168 "BriefDescription": "All offcore demand RFO requests",2169 "Counter": "2",2170 "EventCode": "0xB7",2171 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",2172 "MSRIndex": "0x1A6",2173 "MSRValue": "0xFF02",2174 "SampleAfterValue": "100000",2175 "UMask": "0x1"2176 },2177 {2178 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit",2179 "Counter": "2",2180 "EventCode": "0xB7",2181 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",2182 "MSRIndex": "0x1A6",2183 "MSRValue": "0x8002",2184 "SampleAfterValue": "100000",2185 "UMask": "0x1"2186 },2187 {2188 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core",2189 "Counter": "2",2190 "EventCode": "0xB7",2191 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",2192 "MSRIndex": "0x1A6",2193 "MSRValue": "0x102",2194 "SampleAfterValue": "100000",2195 "UMask": "0x1"2196 },2197 {2198 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core",2199 "Counter": "2",2200 "EventCode": "0xB7",2201 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",2202 "MSRIndex": "0x1A6",2203 "MSRValue": "0x202",2204 "SampleAfterValue": "100000",2205 "UMask": "0x1"2206 },2207 {2208 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core",2209 "Counter": "2",2210 "EventCode": "0xB7",2211 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",2212 "MSRIndex": "0x1A6",2213 "MSRValue": "0x402",2214 "SampleAfterValue": "100000",2215 "UMask": "0x1"2216 },2217 {2218 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC",2219 "Counter": "2",2220 "EventCode": "0xB7",2221 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",2222 "MSRIndex": "0x1A6",2223 "MSRValue": "0x702",2224 "SampleAfterValue": "100000",2225 "UMask": "0x1"2226 },2227 {2228 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM",2229 "Counter": "2",2230 "EventCode": "0xB7",2231 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM",2232 "MSRIndex": "0x1A6",2233 "MSRValue": "0x4702",2234 "SampleAfterValue": "100000",2235 "UMask": "0x1"2236 },2237 {2238 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache",2239 "Counter": "2",2240 "EventCode": "0xB7",2241 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE",2242 "MSRIndex": "0x1A6",2243 "MSRValue": "0x1802",2244 "SampleAfterValue": "100000",2245 "UMask": "0x1"2246 },2247 {2248 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM",2249 "Counter": "2",2250 "EventCode": "0xB7",2251 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM",2252 "MSRIndex": "0x1A6",2253 "MSRValue": "0x3802",2254 "SampleAfterValue": "100000",2255 "UMask": "0x1"2256 },2257 {2258 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache",2259 "Counter": "2",2260 "EventCode": "0xB7",2261 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT",2262 "MSRIndex": "0x1A6",2263 "MSRValue": "0x1002",2264 "SampleAfterValue": "100000",2265 "UMask": "0x1"2266 },2267 {2268 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache",2269 "Counter": "2",2270 "EventCode": "0xB7",2271 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",2272 "MSRIndex": "0x1A6",2273 "MSRValue": "0x802",2274 "SampleAfterValue": "100000",2275 "UMask": "0x1"2276 },2277 {2278 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.",2279 "Counter": "2",2280 "EventCode": "0xB7",2281 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",2282 "MSRIndex": "0x1A6",2283 "MSRValue": "0x7F80",2284 "SampleAfterValue": "100000",2285 "UMask": "0x1"2286 },2287 {2288 "BriefDescription": "All offcore other requests",2289 "Counter": "2",2290 "EventCode": "0xB7",2291 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",2292 "MSRIndex": "0x1A6",2293 "MSRValue": "0xFF80",2294 "SampleAfterValue": "100000",2295 "UMask": "0x1"2296 },2297 {2298 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit",2299 "Counter": "2",2300 "EventCode": "0xB7",2301 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",2302 "MSRIndex": "0x1A6",2303 "MSRValue": "0x8080",2304 "SampleAfterValue": "100000",2305 "UMask": "0x1"2306 },2307 {2308 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core",2309 "Counter": "2",2310 "EventCode": "0xB7",2311 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",2312 "MSRIndex": "0x1A6",2313 "MSRValue": "0x180",2314 "SampleAfterValue": "100000",2315 "UMask": "0x1"2316 },2317 {2318 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core",2319 "Counter": "2",2320 "EventCode": "0xB7",2321 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",2322 "MSRIndex": "0x1A6",2323 "MSRValue": "0x280",2324 "SampleAfterValue": "100000",2325 "UMask": "0x1"2326 },2327 {2328 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core",2329 "Counter": "2",2330 "EventCode": "0xB7",2331 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",2332 "MSRIndex": "0x1A6",2333 "MSRValue": "0x480",2334 "SampleAfterValue": "100000",2335 "UMask": "0x1"2336 },2337 {2338 "BriefDescription": "Offcore other requests satisfied by the LLC",2339 "Counter": "2",2340 "EventCode": "0xB7",2341 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",2342 "MSRIndex": "0x1A6",2343 "MSRValue": "0x780",2344 "SampleAfterValue": "100000",2345 "UMask": "0x1"2346 },2347 {2348 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM",2349 "Counter": "2",2350 "EventCode": "0xB7",2351 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM",2352 "MSRIndex": "0x1A6",2353 "MSRValue": "0x4780",2354 "SampleAfterValue": "100000",2355 "UMask": "0x1"2356 },2357 {2358 "BriefDescription": "Offcore other requests satisfied by a remote cache",2359 "Counter": "2",2360 "EventCode": "0xB7",2361 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE",2362 "MSRIndex": "0x1A6",2363 "MSRValue": "0x1880",2364 "SampleAfterValue": "100000",2365 "UMask": "0x1"2366 },2367 {2368 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM",2369 "Counter": "2",2370 "EventCode": "0xB7",2371 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM",2372 "MSRIndex": "0x1A6",2373 "MSRValue": "0x3880",2374 "SampleAfterValue": "100000",2375 "UMask": "0x1"2376 },2377 {2378 "BriefDescription": "Offcore other requests that HIT in a remote cache",2379 "Counter": "2",2380 "EventCode": "0xB7",2381 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT",2382 "MSRIndex": "0x1A6",2383 "MSRValue": "0x1080",2384 "SampleAfterValue": "100000",2385 "UMask": "0x1"2386 },2387 {2388 "BriefDescription": "Offcore other requests that HITM in a remote cache",2389 "Counter": "2",2390 "EventCode": "0xB7",2391 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",2392 "MSRIndex": "0x1A6",2393 "MSRValue": "0x880",2394 "SampleAfterValue": "100000",2395 "UMask": "0x1"2396 },2397 {2398 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM",2399 "Counter": "2",2400 "EventCode": "0xB7",2401 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",2402 "MSRIndex": "0x1A6",2403 "MSRValue": "0x7F30",2404 "SampleAfterValue": "100000",2405 "UMask": "0x1"2406 },2407 {2408 "BriefDescription": "All offcore prefetch data requests",2409 "Counter": "2",2410 "EventCode": "0xB7",2411 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",2412 "MSRIndex": "0x1A6",2413 "MSRValue": "0xFF30",2414 "SampleAfterValue": "100000",2415 "UMask": "0x1"2416 },2417 {2418 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.",2419 "Counter": "2",2420 "EventCode": "0xB7",2421 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",2422 "MSRIndex": "0x1A6",2423 "MSRValue": "0x8030",2424 "SampleAfterValue": "100000",2425 "UMask": "0x1"2426 },2427 {2428 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core",2429 "Counter": "2",2430 "EventCode": "0xB7",2431 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",2432 "MSRIndex": "0x1A6",2433 "MSRValue": "0x130",2434 "SampleAfterValue": "100000",2435 "UMask": "0x1"2436 },2437 {2438 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core",2439 "Counter": "2",2440 "EventCode": "0xB7",2441 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",2442 "MSRIndex": "0x1A6",2443 "MSRValue": "0x230",2444 "SampleAfterValue": "100000",2445 "UMask": "0x1"2446 },2447 {2448 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core",2449 "Counter": "2",2450 "EventCode": "0xB7",2451 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",2452 "MSRIndex": "0x1A6",2453 "MSRValue": "0x430",2454 "SampleAfterValue": "100000",2455 "UMask": "0x1"2456 },2457 {2458 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC",2459 "Counter": "2",2460 "EventCode": "0xB7",2461 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",2462 "MSRIndex": "0x1A6",2463 "MSRValue": "0x730",2464 "SampleAfterValue": "100000",2465 "UMask": "0x1"2466 },2467 {2468 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM",2469 "Counter": "2",2470 "EventCode": "0xB7",2471 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM",2472 "MSRIndex": "0x1A6",2473 "MSRValue": "0x4730",2474 "SampleAfterValue": "100000",2475 "UMask": "0x1"2476 },2477 {2478 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache",2479 "Counter": "2",2480 "EventCode": "0xB7",2481 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE",2482 "MSRIndex": "0x1A6",2483 "MSRValue": "0x1830",2484 "SampleAfterValue": "100000",2485 "UMask": "0x1"2486 },2487 {2488 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM",2489 "Counter": "2",2490 "EventCode": "0xB7",2491 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM",2492 "MSRIndex": "0x1A6",2493 "MSRValue": "0x3830",2494 "SampleAfterValue": "100000",2495 "UMask": "0x1"2496 },2497 {2498 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache",2499 "Counter": "2",2500 "EventCode": "0xB7",2501 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT",2502 "MSRIndex": "0x1A6",2503 "MSRValue": "0x1030",2504 "SampleAfterValue": "100000",2505 "UMask": "0x1"2506 },2507 {2508 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache",2509 "Counter": "2",2510 "EventCode": "0xB7",2511 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",2512 "MSRIndex": "0x1A6",2513 "MSRValue": "0x830",2514 "SampleAfterValue": "100000",2515 "UMask": "0x1"2516 },2517 {2518 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.",2519 "Counter": "2",2520 "EventCode": "0xB7",2521 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",2522 "MSRIndex": "0x1A6",2523 "MSRValue": "0x7F10",2524 "SampleAfterValue": "100000",2525 "UMask": "0x1"2526 },2527 {2528 "BriefDescription": "All offcore prefetch data reads",2529 "Counter": "2",2530 "EventCode": "0xB7",2531 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",2532 "MSRIndex": "0x1A6",2533 "MSRValue": "0xFF10",2534 "SampleAfterValue": "100000",2535 "UMask": "0x1"2536 },2537 {2538 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit",2539 "Counter": "2",2540 "EventCode": "0xB7",2541 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",2542 "MSRIndex": "0x1A6",2543 "MSRValue": "0x8010",2544 "SampleAfterValue": "100000",2545 "UMask": "0x1"2546 },2547 {2548 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core",2549 "Counter": "2",2550 "EventCode": "0xB7",2551 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",2552 "MSRIndex": "0x1A6",2553 "MSRValue": "0x110",2554 "SampleAfterValue": "100000",2555 "UMask": "0x1"2556 },2557 {2558 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core",2559 "Counter": "2",2560 "EventCode": "0xB7",2561 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",2562 "MSRIndex": "0x1A6",2563 "MSRValue": "0x210",2564 "SampleAfterValue": "100000",2565 "UMask": "0x1"2566 },2567 {2568 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core",2569 "Counter": "2",2570 "EventCode": "0xB7",2571 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",2572 "MSRIndex": "0x1A6",2573 "MSRValue": "0x410",2574 "SampleAfterValue": "100000",2575 "UMask": "0x1"2576 },2577 {2578 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC",2579 "Counter": "2",2580 "EventCode": "0xB7",2581 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",2582 "MSRIndex": "0x1A6",2583 "MSRValue": "0x710",2584 "SampleAfterValue": "100000",2585 "UMask": "0x1"2586 },2587 {2588 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM",2589 "Counter": "2",2590 "EventCode": "0xB7",2591 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM",2592 "MSRIndex": "0x1A6",2593 "MSRValue": "0x4710",2594 "SampleAfterValue": "100000",2595 "UMask": "0x1"2596 },2597 {2598 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache",2599 "Counter": "2",2600 "EventCode": "0xB7",2601 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE",2602 "MSRIndex": "0x1A6",2603 "MSRValue": "0x1810",2604 "SampleAfterValue": "100000",2605 "UMask": "0x1"2606 },2607 {2608 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM",2609 "Counter": "2",2610 "EventCode": "0xB7",2611 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM",2612 "MSRIndex": "0x1A6",2613 "MSRValue": "0x3810",2614 "SampleAfterValue": "100000",2615 "UMask": "0x1"2616 },2617 {2618 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache",2619 "Counter": "2",2620 "EventCode": "0xB7",2621 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT",2622 "MSRIndex": "0x1A6",2623 "MSRValue": "0x1010",2624 "SampleAfterValue": "100000",2625 "UMask": "0x1"2626 },2627 {2628 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache",2629 "Counter": "2",2630 "EventCode": "0xB7",2631 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",2632 "MSRIndex": "0x1A6",2633 "MSRValue": "0x810",2634 "SampleAfterValue": "100000",2635 "UMask": "0x1"2636 },2637 {2638 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.",2639 "Counter": "2",2640 "EventCode": "0xB7",2641 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",2642 "MSRIndex": "0x1A6",2643 "MSRValue": "0x7F40",2644 "SampleAfterValue": "100000",2645 "UMask": "0x1"2646 },2647 {2648 "BriefDescription": "All offcore prefetch code reads",2649 "Counter": "2",2650 "EventCode": "0xB7",2651 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",2652 "MSRIndex": "0x1A6",2653 "MSRValue": "0xFF40",2654 "SampleAfterValue": "100000",2655 "UMask": "0x1"2656 },2657 {2658 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit",2659 "Counter": "2",2660 "EventCode": "0xB7",2661 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",2662 "MSRIndex": "0x1A6",2663 "MSRValue": "0x8040",2664 "SampleAfterValue": "100000",2665 "UMask": "0x1"2666 },2667 {2668 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core",2669 "Counter": "2",2670 "EventCode": "0xB7",2671 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",2672 "MSRIndex": "0x1A6",2673 "MSRValue": "0x140",2674 "SampleAfterValue": "100000",2675 "UMask": "0x1"2676 },2677 {2678 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core",2679 "Counter": "2",2680 "EventCode": "0xB7",2681 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",2682 "MSRIndex": "0x1A6",2683 "MSRValue": "0x240",2684 "SampleAfterValue": "100000",2685 "UMask": "0x1"2686 },2687 {2688 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core",2689 "Counter": "2",2690 "EventCode": "0xB7",2691 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",2692 "MSRIndex": "0x1A6",2693 "MSRValue": "0x440",2694 "SampleAfterValue": "100000",2695 "UMask": "0x1"2696 },2697 {2698 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC",2699 "Counter": "2",2700 "EventCode": "0xB7",2701 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",2702 "MSRIndex": "0x1A6",2703 "MSRValue": "0x740",2704 "SampleAfterValue": "100000",2705 "UMask": "0x1"2706 },2707 {2708 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM",2709 "Counter": "2",2710 "EventCode": "0xB7",2711 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM",2712 "MSRIndex": "0x1A6",2713 "MSRValue": "0x4740",2714 "SampleAfterValue": "100000",2715 "UMask": "0x1"2716 },2717 {2718 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache",2719 "Counter": "2",2720 "EventCode": "0xB7",2721 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE",2722 "MSRIndex": "0x1A6",2723 "MSRValue": "0x1840",2724 "SampleAfterValue": "100000",2725 "UMask": "0x1"2726 },2727 {2728 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM",2729 "Counter": "2",2730 "EventCode": "0xB7",2731 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM",2732 "MSRIndex": "0x1A6",2733 "MSRValue": "0x3840",2734 "SampleAfterValue": "100000",2735 "UMask": "0x1"2736 },2737 {2738 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache",2739 "Counter": "2",2740 "EventCode": "0xB7",2741 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT",2742 "MSRIndex": "0x1A6",2743 "MSRValue": "0x1040",2744 "SampleAfterValue": "100000",2745 "UMask": "0x1"2746 },2747 {2748 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache",2749 "Counter": "2",2750 "EventCode": "0xB7",2751 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",2752 "MSRIndex": "0x1A6",2753 "MSRValue": "0x840",2754 "SampleAfterValue": "100000",2755 "UMask": "0x1"2756 },2757 {2758 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.",2759 "Counter": "2",2760 "EventCode": "0xB7",2761 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",2762 "MSRIndex": "0x1A6",2763 "MSRValue": "0x7F20",2764 "SampleAfterValue": "100000",2765 "UMask": "0x1"2766 },2767 {2768 "BriefDescription": "All offcore prefetch RFO requests",2769 "Counter": "2",2770 "EventCode": "0xB7",2771 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",2772 "MSRIndex": "0x1A6",2773 "MSRValue": "0xFF20",2774 "SampleAfterValue": "100000",2775 "UMask": "0x1"2776 },2777 {2778 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit",2779 "Counter": "2",2780 "EventCode": "0xB7",2781 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",2782 "MSRIndex": "0x1A6",2783 "MSRValue": "0x8020",2784 "SampleAfterValue": "100000",2785 "UMask": "0x1"2786 },2787 {2788 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core",2789 "Counter": "2",2790 "EventCode": "0xB7",2791 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",2792 "MSRIndex": "0x1A6",2793 "MSRValue": "0x120",2794 "SampleAfterValue": "100000",2795 "UMask": "0x1"2796 },2797 {2798 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core",2799 "Counter": "2",2800 "EventCode": "0xB7",2801 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",2802 "MSRIndex": "0x1A6",2803 "MSRValue": "0x220",2804 "SampleAfterValue": "100000",2805 "UMask": "0x1"2806 },2807 {2808 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core",2809 "Counter": "2",2810 "EventCode": "0xB7",2811 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",2812 "MSRIndex": "0x1A6",2813 "MSRValue": "0x420",2814 "SampleAfterValue": "100000",2815 "UMask": "0x1"2816 },2817 {2818 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC",2819 "Counter": "2",2820 "EventCode": "0xB7",2821 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",2822 "MSRIndex": "0x1A6",2823 "MSRValue": "0x720",2824 "SampleAfterValue": "100000",2825 "UMask": "0x1"2826 },2827 {2828 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM",2829 "Counter": "2",2830 "EventCode": "0xB7",2831 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM",2832 "MSRIndex": "0x1A6",2833 "MSRValue": "0x4720",2834 "SampleAfterValue": "100000",2835 "UMask": "0x1"2836 },2837 {2838 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache",2839 "Counter": "2",2840 "EventCode": "0xB7",2841 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE",2842 "MSRIndex": "0x1A6",2843 "MSRValue": "0x1820",2844 "SampleAfterValue": "100000",2845 "UMask": "0x1"2846 },2847 {2848 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM",2849 "Counter": "2",2850 "EventCode": "0xB7",2851 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM",2852 "MSRIndex": "0x1A6",2853 "MSRValue": "0x3820",2854 "SampleAfterValue": "100000",2855 "UMask": "0x1"2856 },2857 {2858 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache",2859 "Counter": "2",2860 "EventCode": "0xB7",2861 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT",2862 "MSRIndex": "0x1A6",2863 "MSRValue": "0x1020",2864 "SampleAfterValue": "100000",2865 "UMask": "0x1"2866 },2867 {2868 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache",2869 "Counter": "2",2870 "EventCode": "0xB7",2871 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",2872 "MSRIndex": "0x1A6",2873 "MSRValue": "0x820",2874 "SampleAfterValue": "100000",2875 "UMask": "0x1"2876 },2877 {2878 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.",2879 "Counter": "2",2880 "EventCode": "0xB7",2881 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",2882 "MSRIndex": "0x1A6",2883 "MSRValue": "0x7F70",2884 "SampleAfterValue": "100000",2885 "UMask": "0x1"2886 },2887 {2888 "BriefDescription": "All offcore prefetch requests",2889 "Counter": "2",2890 "EventCode": "0xB7",2891 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",2892 "MSRIndex": "0x1A6",2893 "MSRValue": "0xFF70",2894 "SampleAfterValue": "100000",2895 "UMask": "0x1"2896 },2897 {2898 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit",2899 "Counter": "2",2900 "EventCode": "0xB7",2901 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",2902 "MSRIndex": "0x1A6",2903 "MSRValue": "0x8070",2904 "SampleAfterValue": "100000",2905 "UMask": "0x1"2906 },2907 {2908 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core",2909 "Counter": "2",2910 "EventCode": "0xB7",2911 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",2912 "MSRIndex": "0x1A6",2913 "MSRValue": "0x170",2914 "SampleAfterValue": "100000",2915 "UMask": "0x1"2916 },2917 {2918 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core",2919 "Counter": "2",2920 "EventCode": "0xB7",2921 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",2922 "MSRIndex": "0x1A6",2923 "MSRValue": "0x270",2924 "SampleAfterValue": "100000",2925 "UMask": "0x1"2926 },2927 {2928 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core",2929 "Counter": "2",2930 "EventCode": "0xB7",2931 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",2932 "MSRIndex": "0x1A6",2933 "MSRValue": "0x470",2934 "SampleAfterValue": "100000",2935 "UMask": "0x1"2936 },2937 {2938 "BriefDescription": "Offcore prefetch requests satisfied by the LLC",2939 "Counter": "2",2940 "EventCode": "0xB7",2941 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",2942 "MSRIndex": "0x1A6",2943 "MSRValue": "0x770",2944 "SampleAfterValue": "100000",2945 "UMask": "0x1"2946 },2947 {2948 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM",2949 "Counter": "2",2950 "EventCode": "0xB7",2951 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM",2952 "MSRIndex": "0x1A6",2953 "MSRValue": "0x4770",2954 "SampleAfterValue": "100000",2955 "UMask": "0x1"2956 },2957 {2958 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache",2959 "Counter": "2",2960 "EventCode": "0xB7",2961 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE",2962 "MSRIndex": "0x1A6",2963 "MSRValue": "0x1870",2964 "SampleAfterValue": "100000",2965 "UMask": "0x1"2966 },2967 {2968 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM",2969 "Counter": "2",2970 "EventCode": "0xB7",2971 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM",2972 "MSRIndex": "0x1A6",2973 "MSRValue": "0x3870",2974 "SampleAfterValue": "100000",2975 "UMask": "0x1"2976 },2977 {2978 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache",2979 "Counter": "2",2980 "EventCode": "0xB7",2981 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT",2982 "MSRIndex": "0x1A6",2983 "MSRValue": "0x1070",2984 "SampleAfterValue": "100000",2985 "UMask": "0x1"2986 },2987 {2988 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache",2989 "Counter": "2",2990 "EventCode": "0xB7",2991 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",2992 "MSRIndex": "0x1A6",2993 "MSRValue": "0x870",2994 "SampleAfterValue": "100000",2995 "UMask": "0x1"2996 },2997 {2998 "BriefDescription": "Super Queue LRU hints sent to LLC",2999 "Counter": "0,1,2,3",3000 "EventCode": "0xF4",3001 "EventName": "SQ_MISC.LRU_HINTS",3002 "SampleAfterValue": "2000000",3003 "UMask": "0x4"3004 },3005 {3006 "BriefDescription": "Super Queue lock splits across a cache line",3007 "Counter": "0,1,2,3",3008 "EventCode": "0xF4",3009 "EventName": "SQ_MISC.SPLIT_LOCK",3010 "SampleAfterValue": "2000000",3011 "UMask": "0x10"3012 },3013 {3014 "BriefDescription": "Loads delayed with at-Retirement block code",3015 "Counter": "0,1,2,3",3016 "EventCode": "0x6",3017 "EventName": "STORE_BLOCKS.AT_RET",3018 "SampleAfterValue": "200000",3019 "UMask": "0x4"3020 },3021 {3022 "BriefDescription": "Cacheable loads delayed with L1D block code",3023 "Counter": "0,1,2,3",3024 "EventCode": "0x6",3025 "EventName": "STORE_BLOCKS.L1D_BLOCK",3026 "SampleAfterValue": "200000",3027 "UMask": "0x8"3028 }3029]3030