121 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tools/testing/selftests/kvm/include/x86_64/apic.h4 *5 * Copyright (C) 2021, Google LLC.6 */7 8#ifndef SELFTEST_KVM_APIC_H9#define SELFTEST_KVM_APIC_H10 11#include <stdint.h>12 13#include "processor.h"14#include "ucall_common.h"15 16#define APIC_DEFAULT_GPA 0xfee00000ULL17 18/* APIC base address MSR and fields */19#define MSR_IA32_APICBASE 0x0000001b20#define MSR_IA32_APICBASE_BSP (1<<8)21#define MSR_IA32_APICBASE_EXTD (1<<10)22#define MSR_IA32_APICBASE_ENABLE (1<<11)23#define MSR_IA32_APICBASE_BASE (0xfffff<<12)24#define GET_APIC_BASE(x) (((x) >> 12) << 12)25 26#define APIC_BASE_MSR 0x80027#define X2APIC_ENABLE (1UL << 10)28#define APIC_ID 0x2029#define APIC_LVR 0x3030#define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)31#define APIC_TASKPRI 0x8032#define APIC_PROCPRI 0xA033#define APIC_EOI 0xB034#define APIC_SPIV 0xF035#define APIC_SPIV_FOCUS_DISABLED (1 << 9)36#define APIC_SPIV_APIC_ENABLED (1 << 8)37#define APIC_IRR 0x20038#define APIC_ICR 0x30039#define APIC_LVTCMCI 0x2f040#define APIC_DEST_SELF 0x4000041#define APIC_DEST_ALLINC 0x8000042#define APIC_DEST_ALLBUT 0xC000043#define APIC_ICR_RR_MASK 0x3000044#define APIC_ICR_RR_INVALID 0x0000045#define APIC_ICR_RR_INPROG 0x1000046#define APIC_ICR_RR_VALID 0x2000047#define APIC_INT_LEVELTRIG 0x0800048#define APIC_INT_ASSERT 0x0400049#define APIC_ICR_BUSY 0x0100050#define APIC_DEST_LOGICAL 0x0080051#define APIC_DEST_PHYSICAL 0x0000052#define APIC_DM_FIXED 0x0000053#define APIC_DM_FIXED_MASK 0x0070054#define APIC_DM_LOWEST 0x0010055#define APIC_DM_SMI 0x0020056#define APIC_DM_REMRD 0x0030057#define APIC_DM_NMI 0x0040058#define APIC_DM_INIT 0x0050059#define APIC_DM_STARTUP 0x0060060#define APIC_DM_EXTINT 0x0070061#define APIC_VECTOR_MASK 0x000FF62#define APIC_ICR2 0x31063#define SET_APIC_DEST_FIELD(x) ((x) << 24)64#define APIC_LVTT 0x32065#define APIC_LVT_TIMER_ONESHOT (0 << 17)66#define APIC_LVT_TIMER_PERIODIC (1 << 17)67#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)68#define APIC_LVT_MASKED (1 << 16)69#define APIC_TMICT 0x38070#define APIC_TMCCT 0x39071#define APIC_TDCR 0x3E072 73void apic_disable(void);74void xapic_enable(void);75void x2apic_enable(void);76 77static inline uint32_t get_bsp_flag(void)78{79 return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP;80}81 82static inline uint32_t xapic_read_reg(unsigned int reg)83{84 return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2];85}86 87static inline void xapic_write_reg(unsigned int reg, uint32_t val)88{89 ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val;90}91 92static inline uint64_t x2apic_read_reg(unsigned int reg)93{94 return rdmsr(APIC_BASE_MSR + (reg >> 4));95}96 97static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value)98{99 return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value);100}101 102static inline void x2apic_write_reg(unsigned int reg, uint64_t value)103{104 uint8_t fault = x2apic_write_reg_safe(reg, value);105 106 __GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n",107 fault, APIC_BASE_MSR + (reg >> 4), value);108}109 110static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value)111{112 uint8_t fault = x2apic_write_reg_safe(reg, value);113 114 __GUEST_ASSERT(fault == GP_VECTOR,115 "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n",116 APIC_BASE_MSR + (reg >> 4), value, fault);117}118 119 120#endif /* SELFTEST_KVM_APIC_H */121