1067 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Check for KVM_GET_REG_LIST regressions.4 *5 * Copyright (c) 2023 Intel Corporation6 *7 */8#include <stdio.h>9#include "kvm_util.h"10#include "test_util.h"11#include "processor.h"12 13#define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)14 15enum {16 VCPU_FEATURE_ISA_EXT = 0,17 VCPU_FEATURE_SBI_EXT,18};19 20static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX];21 22bool filter_reg(__u64 reg)23{24 switch (reg & ~REG_MASK) {25 /*26 * Same set of ISA_EXT registers are not present on all host because27 * ISA_EXT registers are visible to the KVM user space based on the28 * ISA extensions available on the host. Also, disabling an ISA29 * extension using corresponding ISA_EXT register does not affect30 * the visibility of the ISA_EXT register itself.31 *32 * Based on above, we should filter-out all ISA_EXT registers.33 *34 * Note: The below list is alphabetically sorted.35 */36 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A:37 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C:38 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D:39 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F:40 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H:41 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I:42 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M:43 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V:44 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN:45 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:46 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:47 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:48 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:49 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:50 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:51 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:52 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:53 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:54 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:55 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC:56 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB:57 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC:58 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX:59 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:60 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA:61 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:62 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:63 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:64 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:65 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:66 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:67 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:68 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:69 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:70 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:71 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:72 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:73 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI:74 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:75 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:76 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:77 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP:78 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:79 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:80 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH:81 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR:82 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:83 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:84 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:85 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:86 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:87 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:88 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:89 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:90 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:91 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:92 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:93 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:94 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:95 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:96 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:97 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:98 /*99 * Like ISA_EXT registers, SBI_EXT registers are only visible when the100 * host supports them and disabling them does not affect the visibility101 * of the SBI_EXT register itself.102 */103 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01:104 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME:105 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI:106 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE:107 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST:108 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM:109 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU:110 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN:111 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA:112 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL:113 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR:114 return true;115 /* AIA registers are always available when Ssaia can't be disabled */116 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):117 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1):118 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2):119 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh):120 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph):121 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h):122 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h):123 return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA];124 default:125 break;126 }127 128 return false;129}130 131bool check_reject_set(int err)132{133 return err == EINVAL;134}135 136void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)137{138 unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };139 struct vcpu_reg_sublist *s;140 uint64_t feature;141 int rc;142 143 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)144 __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]);145 146 /*147 * Disable all extensions which were enabled by default148 * if they were available in the risc-v host.149 */150 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {151 rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);152 if (rc && isa_ext_state[i])153 isa_ext_cant_disable[i] = true;154 }155 156 for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {157 rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0);158 TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error");159 }160 161 for_each_sublist(c, s) {162 if (!s->feature)163 continue;164 165 switch (s->feature_type) {166 case VCPU_FEATURE_ISA_EXT:167 feature = RISCV_ISA_EXT_REG(s->feature);168 break;169 case VCPU_FEATURE_SBI_EXT:170 feature = RISCV_SBI_EXT_REG(s->feature);171 break;172 default:173 TEST_FAIL("Unknown feature type");174 }175 176 /* Try to enable the desired extension */177 __vcpu_set_reg(vcpu, feature, 1);178 179 /* Double check whether the desired extension was enabled */180 __TEST_REQUIRE(__vcpu_has_ext(vcpu, feature),181 "%s not available, skipping tests", s->name);182 }183}184 185static const char *config_id_to_str(const char *prefix, __u64 id)186{187 /* reg_off is the offset into struct kvm_riscv_config */188 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG);189 190 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG);191 192 switch (reg_off) {193 case KVM_REG_RISCV_CONFIG_REG(isa):194 return "KVM_REG_RISCV_CONFIG_REG(isa)";195 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):196 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";197 case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):198 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";199 case KVM_REG_RISCV_CONFIG_REG(mvendorid):200 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)";201 case KVM_REG_RISCV_CONFIG_REG(marchid):202 return "KVM_REG_RISCV_CONFIG_REG(marchid)";203 case KVM_REG_RISCV_CONFIG_REG(mimpid):204 return "KVM_REG_RISCV_CONFIG_REG(mimpid)";205 case KVM_REG_RISCV_CONFIG_REG(satp_mode):206 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)";207 }208 209 return strdup_printf("%lld /* UNKNOWN */", reg_off);210}211 212static const char *core_id_to_str(const char *prefix, __u64 id)213{214 /* reg_off is the offset into struct kvm_riscv_core */215 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE);216 217 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE);218 219 switch (reg_off) {220 case KVM_REG_RISCV_CORE_REG(regs.pc):221 return "KVM_REG_RISCV_CORE_REG(regs.pc)";222 case KVM_REG_RISCV_CORE_REG(regs.ra):223 return "KVM_REG_RISCV_CORE_REG(regs.ra)";224 case KVM_REG_RISCV_CORE_REG(regs.sp):225 return "KVM_REG_RISCV_CORE_REG(regs.sp)";226 case KVM_REG_RISCV_CORE_REG(regs.gp):227 return "KVM_REG_RISCV_CORE_REG(regs.gp)";228 case KVM_REG_RISCV_CORE_REG(regs.tp):229 return "KVM_REG_RISCV_CORE_REG(regs.tp)";230 case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2):231 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",232 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0));233 case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1):234 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",235 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0));236 case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7):237 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)",238 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0));239 case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11):240 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",241 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2);242 case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6):243 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",244 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3);245 case KVM_REG_RISCV_CORE_REG(mode):246 return "KVM_REG_RISCV_CORE_REG(mode)";247 }248 249 return strdup_printf("%lld /* UNKNOWN */", reg_off);250}251 252#define RISCV_CSR_GENERAL(csr) \253 "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"254#define RISCV_CSR_AIA(csr) \255 "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"256#define RISCV_CSR_SMSTATEEN(csr) \257 "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"258 259static const char *general_csr_id_to_str(__u64 reg_off)260{261 /* reg_off is the offset into struct kvm_riscv_csr */262 switch (reg_off) {263 case KVM_REG_RISCV_CSR_REG(sstatus):264 return RISCV_CSR_GENERAL(sstatus);265 case KVM_REG_RISCV_CSR_REG(sie):266 return RISCV_CSR_GENERAL(sie);267 case KVM_REG_RISCV_CSR_REG(stvec):268 return RISCV_CSR_GENERAL(stvec);269 case KVM_REG_RISCV_CSR_REG(sscratch):270 return RISCV_CSR_GENERAL(sscratch);271 case KVM_REG_RISCV_CSR_REG(sepc):272 return RISCV_CSR_GENERAL(sepc);273 case KVM_REG_RISCV_CSR_REG(scause):274 return RISCV_CSR_GENERAL(scause);275 case KVM_REG_RISCV_CSR_REG(stval):276 return RISCV_CSR_GENERAL(stval);277 case KVM_REG_RISCV_CSR_REG(sip):278 return RISCV_CSR_GENERAL(sip);279 case KVM_REG_RISCV_CSR_REG(satp):280 return RISCV_CSR_GENERAL(satp);281 case KVM_REG_RISCV_CSR_REG(scounteren):282 return RISCV_CSR_GENERAL(scounteren);283 case KVM_REG_RISCV_CSR_REG(senvcfg):284 return RISCV_CSR_GENERAL(senvcfg);285 }286 287 return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off);288}289 290static const char *aia_csr_id_to_str(__u64 reg_off)291{292 /* reg_off is the offset into struct kvm_riscv_aia_csr */293 switch (reg_off) {294 case KVM_REG_RISCV_CSR_AIA_REG(siselect):295 return RISCV_CSR_AIA(siselect);296 case KVM_REG_RISCV_CSR_AIA_REG(iprio1):297 return RISCV_CSR_AIA(iprio1);298 case KVM_REG_RISCV_CSR_AIA_REG(iprio2):299 return RISCV_CSR_AIA(iprio2);300 case KVM_REG_RISCV_CSR_AIA_REG(sieh):301 return RISCV_CSR_AIA(sieh);302 case KVM_REG_RISCV_CSR_AIA_REG(siph):303 return RISCV_CSR_AIA(siph);304 case KVM_REG_RISCV_CSR_AIA_REG(iprio1h):305 return RISCV_CSR_AIA(iprio1h);306 case KVM_REG_RISCV_CSR_AIA_REG(iprio2h):307 return RISCV_CSR_AIA(iprio2h);308 }309 310 return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off);311}312 313static const char *smstateen_csr_id_to_str(__u64 reg_off)314{315 /* reg_off is the offset into struct kvm_riscv_smstateen_csr */316 switch (reg_off) {317 case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):318 return RISCV_CSR_SMSTATEEN(sstateen0);319 }320 321 TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);322 return NULL;323}324 325static const char *csr_id_to_str(const char *prefix, __u64 id)326{327 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);328 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;329 330 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR);331 332 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;333 334 switch (reg_subtype) {335 case KVM_REG_RISCV_CSR_GENERAL:336 return general_csr_id_to_str(reg_off);337 case KVM_REG_RISCV_CSR_AIA:338 return aia_csr_id_to_str(reg_off);339 case KVM_REG_RISCV_CSR_SMSTATEEN:340 return smstateen_csr_id_to_str(reg_off);341 }342 343 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);344}345 346static const char *timer_id_to_str(const char *prefix, __u64 id)347{348 /* reg_off is the offset into struct kvm_riscv_timer */349 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER);350 351 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER);352 353 switch (reg_off) {354 case KVM_REG_RISCV_TIMER_REG(frequency):355 return "KVM_REG_RISCV_TIMER_REG(frequency)";356 case KVM_REG_RISCV_TIMER_REG(time):357 return "KVM_REG_RISCV_TIMER_REG(time)";358 case KVM_REG_RISCV_TIMER_REG(compare):359 return "KVM_REG_RISCV_TIMER_REG(compare)";360 case KVM_REG_RISCV_TIMER_REG(state):361 return "KVM_REG_RISCV_TIMER_REG(state)";362 }363 364 return strdup_printf("%lld /* UNKNOWN */", reg_off);365}366 367static const char *fp_f_id_to_str(const char *prefix, __u64 id)368{369 /* reg_off is the offset into struct __riscv_f_ext_state */370 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F);371 372 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F);373 374 switch (reg_off) {375 case KVM_REG_RISCV_FP_F_REG(f[0]) ...376 KVM_REG_RISCV_FP_F_REG(f[31]):377 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off);378 case KVM_REG_RISCV_FP_F_REG(fcsr):379 return "KVM_REG_RISCV_FP_F_REG(fcsr)";380 }381 382 return strdup_printf("%lld /* UNKNOWN */", reg_off);383}384 385static const char *fp_d_id_to_str(const char *prefix, __u64 id)386{387 /* reg_off is the offset into struct __riscv_d_ext_state */388 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D);389 390 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D);391 392 switch (reg_off) {393 case KVM_REG_RISCV_FP_D_REG(f[0]) ...394 KVM_REG_RISCV_FP_D_REG(f[31]):395 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off);396 case KVM_REG_RISCV_FP_D_REG(fcsr):397 return "KVM_REG_RISCV_FP_D_REG(fcsr)";398 }399 400 return strdup_printf("%lld /* UNKNOWN */", reg_off);401}402 403#define KVM_ISA_EXT_ARR(ext) \404[KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext405 406static const char *isa_ext_single_id_to_str(__u64 reg_off)407{408 static const char * const kvm_isa_ext_reg_name[] = {409 KVM_ISA_EXT_ARR(A),410 KVM_ISA_EXT_ARR(C),411 KVM_ISA_EXT_ARR(D),412 KVM_ISA_EXT_ARR(F),413 KVM_ISA_EXT_ARR(H),414 KVM_ISA_EXT_ARR(I),415 KVM_ISA_EXT_ARR(M),416 KVM_ISA_EXT_ARR(V),417 KVM_ISA_EXT_ARR(SMSTATEEN),418 KVM_ISA_EXT_ARR(SSAIA),419 KVM_ISA_EXT_ARR(SSCOFPMF),420 KVM_ISA_EXT_ARR(SSTC),421 KVM_ISA_EXT_ARR(SVINVAL),422 KVM_ISA_EXT_ARR(SVNAPOT),423 KVM_ISA_EXT_ARR(SVPBMT),424 KVM_ISA_EXT_ARR(ZACAS),425 KVM_ISA_EXT_ARR(ZAWRS),426 KVM_ISA_EXT_ARR(ZBA),427 KVM_ISA_EXT_ARR(ZBB),428 KVM_ISA_EXT_ARR(ZBC),429 KVM_ISA_EXT_ARR(ZBKB),430 KVM_ISA_EXT_ARR(ZBKC),431 KVM_ISA_EXT_ARR(ZBKX),432 KVM_ISA_EXT_ARR(ZBS),433 KVM_ISA_EXT_ARR(ZCA),434 KVM_ISA_EXT_ARR(ZCB),435 KVM_ISA_EXT_ARR(ZCD),436 KVM_ISA_EXT_ARR(ZCF),437 KVM_ISA_EXT_ARR(ZCMOP),438 KVM_ISA_EXT_ARR(ZFA),439 KVM_ISA_EXT_ARR(ZFH),440 KVM_ISA_EXT_ARR(ZFHMIN),441 KVM_ISA_EXT_ARR(ZICBOM),442 KVM_ISA_EXT_ARR(ZICBOZ),443 KVM_ISA_EXT_ARR(ZICNTR),444 KVM_ISA_EXT_ARR(ZICOND),445 KVM_ISA_EXT_ARR(ZICSR),446 KVM_ISA_EXT_ARR(ZIFENCEI),447 KVM_ISA_EXT_ARR(ZIHINTNTL),448 KVM_ISA_EXT_ARR(ZIHINTPAUSE),449 KVM_ISA_EXT_ARR(ZIHPM),450 KVM_ISA_EXT_ARR(ZIMOP),451 KVM_ISA_EXT_ARR(ZKND),452 KVM_ISA_EXT_ARR(ZKNE),453 KVM_ISA_EXT_ARR(ZKNH),454 KVM_ISA_EXT_ARR(ZKR),455 KVM_ISA_EXT_ARR(ZKSED),456 KVM_ISA_EXT_ARR(ZKSH),457 KVM_ISA_EXT_ARR(ZKT),458 KVM_ISA_EXT_ARR(ZTSO),459 KVM_ISA_EXT_ARR(ZVBB),460 KVM_ISA_EXT_ARR(ZVBC),461 KVM_ISA_EXT_ARR(ZVFH),462 KVM_ISA_EXT_ARR(ZVFHMIN),463 KVM_ISA_EXT_ARR(ZVKB),464 KVM_ISA_EXT_ARR(ZVKG),465 KVM_ISA_EXT_ARR(ZVKNED),466 KVM_ISA_EXT_ARR(ZVKNHA),467 KVM_ISA_EXT_ARR(ZVKNHB),468 KVM_ISA_EXT_ARR(ZVKSED),469 KVM_ISA_EXT_ARR(ZVKSH),470 KVM_ISA_EXT_ARR(ZVKT),471 };472 473 if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))474 return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off);475 476 return kvm_isa_ext_reg_name[reg_off];477}478 479static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)480{481 const char *unknown = "";482 483 if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST)484 unknown = " /* UNKNOWN */";485 486 switch (reg_subtype) {487 case KVM_REG_RISCV_ISA_MULTI_EN:488 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown);489 case KVM_REG_RISCV_ISA_MULTI_DIS:490 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown);491 }492 493 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);494}495 496static const char *isa_ext_id_to_str(const char *prefix, __u64 id)497{498 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);499 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;500 501 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT);502 503 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;504 505 switch (reg_subtype) {506 case KVM_REG_RISCV_ISA_SINGLE:507 return isa_ext_single_id_to_str(reg_off);508 case KVM_REG_RISCV_ISA_MULTI_EN:509 case KVM_REG_RISCV_ISA_MULTI_DIS:510 return isa_ext_multi_id_to_str(reg_subtype, reg_off);511 }512 513 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);514}515 516#define KVM_SBI_EXT_ARR(ext) \517[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext518 519static const char *sbi_ext_single_id_to_str(__u64 reg_off)520{521 /* reg_off is KVM_RISCV_SBI_EXT_ID */522 static const char * const kvm_sbi_ext_reg_name[] = {523 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01),524 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME),525 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI),526 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE),527 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST),528 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM),529 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU),530 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA),531 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL),532 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR),533 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN),534 };535 536 if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name))537 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off);538 539 return kvm_sbi_ext_reg_name[reg_off];540}541 542static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)543{544 const char *unknown = "";545 546 if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST)547 unknown = " /* UNKNOWN */";548 549 switch (reg_subtype) {550 case KVM_REG_RISCV_SBI_MULTI_EN:551 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown);552 case KVM_REG_RISCV_SBI_MULTI_DIS:553 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown);554 }555 556 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);557}558 559static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)560{561 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT);562 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;563 564 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT);565 566 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;567 568 switch (reg_subtype) {569 case KVM_REG_RISCV_SBI_SINGLE:570 return sbi_ext_single_id_to_str(reg_off);571 case KVM_REG_RISCV_SBI_MULTI_EN:572 case KVM_REG_RISCV_SBI_MULTI_DIS:573 return sbi_ext_multi_id_to_str(reg_subtype, reg_off);574 }575 576 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);577}578 579static const char *sbi_sta_id_to_str(__u64 reg_off)580{581 switch (reg_off) {582 case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)";583 case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)";584 }585 return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off);586}587 588static const char *sbi_id_to_str(const char *prefix, __u64 id)589{590 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE);591 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;592 593 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE);594 595 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;596 597 switch (reg_subtype) {598 case KVM_REG_RISCV_SBI_STA:599 return sbi_sta_id_to_str(reg_off);600 }601 602 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);603}604 605void print_reg(const char *prefix, __u64 id)606{607 const char *reg_size = NULL;608 609 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV,610 "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id);611 612 switch (id & KVM_REG_SIZE_MASK) {613 case KVM_REG_SIZE_U32:614 reg_size = "KVM_REG_SIZE_U32";615 break;616 case KVM_REG_SIZE_U64:617 reg_size = "KVM_REG_SIZE_U64";618 break;619 case KVM_REG_SIZE_U128:620 reg_size = "KVM_REG_SIZE_U128";621 break;622 default:623 printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n",624 (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK);625 return;626 }627 628 switch (id & KVM_REG_RISCV_TYPE_MASK) {629 case KVM_REG_RISCV_CONFIG:630 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n",631 reg_size, config_id_to_str(prefix, id));632 break;633 case KVM_REG_RISCV_CORE:634 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n",635 reg_size, core_id_to_str(prefix, id));636 break;637 case KVM_REG_RISCV_CSR:638 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n",639 reg_size, csr_id_to_str(prefix, id));640 break;641 case KVM_REG_RISCV_TIMER:642 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n",643 reg_size, timer_id_to_str(prefix, id));644 break;645 case KVM_REG_RISCV_FP_F:646 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n",647 reg_size, fp_f_id_to_str(prefix, id));648 break;649 case KVM_REG_RISCV_FP_D:650 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n",651 reg_size, fp_d_id_to_str(prefix, id));652 break;653 case KVM_REG_RISCV_ISA_EXT:654 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n",655 reg_size, isa_ext_id_to_str(prefix, id));656 break;657 case KVM_REG_RISCV_SBI_EXT:658 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n",659 reg_size, sbi_ext_id_to_str(prefix, id));660 break;661 case KVM_REG_RISCV_SBI_STATE:662 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n",663 reg_size, sbi_id_to_str(prefix, id));664 break;665 default:666 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n",667 reg_size, id & ~REG_MASK);668 return;669 }670}671 672/*673 * The current blessed list was primed with the output of kernel version674 * v6.5-rc3 and then later updated with new registers.675 */676static __u64 base_regs[] = {677 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),678 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),679 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),680 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),681 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),682 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc),683 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra),684 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp),685 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp),686 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp),687 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0),688 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1),689 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2),690 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0),691 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1),692 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0),693 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1),694 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2),695 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3),696 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4),697 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5),698 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6),699 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7),700 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2),701 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3),702 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4),703 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5),704 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6),705 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7),706 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8),707 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9),708 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10),709 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11),710 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3),711 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4),712 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5),713 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6),714 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode),715 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus),716 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie),717 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec),718 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch),719 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc),720 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause),721 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval),722 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),723 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),724 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),725 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),726 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),727 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),728 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),729 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),730};731 732/*733 * The skips_set list registers that should skip set test.734 * - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly.735 */736static __u64 base_skips_set[] = {737 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),738};739 740static __u64 sbi_base_regs[] = {741 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01,742 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME,743 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI,744 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE,745 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST,746 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM,747 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL,748 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR,749};750 751static __u64 sbi_sta_regs[] = {752 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA,753 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo),754 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi),755};756 757static __u64 zicbom_regs[] = {758 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),759 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,760};761 762static __u64 zicboz_regs[] = {763 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),764 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,765};766 767static __u64 aia_regs[] = {768 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),769 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),770 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2),771 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh),772 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph),773 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h),774 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h),775 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA,776};777 778static __u64 smstateen_regs[] = {779 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),780 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN,781};782 783static __u64 fp_f_regs[] = {784 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),785 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),786 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]),787 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]),788 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]),789 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]),790 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]),791 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]),792 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]),793 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]),794 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]),795 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]),796 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]),797 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]),798 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]),799 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]),800 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]),801 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]),802 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]),803 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]),804 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]),805 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]),806 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]),807 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]),808 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]),809 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]),810 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]),811 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]),812 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]),813 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]),814 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]),815 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]),816 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr),817 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F,818};819 820static __u64 fp_d_regs[] = {821 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]),822 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]),823 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]),824 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]),825 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]),826 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]),827 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]),828 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]),829 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]),830 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]),831 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]),832 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]),833 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]),834 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]),835 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]),836 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]),837 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]),838 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]),839 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]),840 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]),841 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]),842 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]),843 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]),844 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]),845 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]),846 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]),847 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]),848 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]),849 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]),850 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]),851 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]),852 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]),853 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr),854 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D,855};856 857#define SUBLIST_BASE \858 {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \859 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}860#define SUBLIST_SBI_BASE \861 {"sbi-base", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_V01, \862 .regs = sbi_base_regs, .regs_n = ARRAY_SIZE(sbi_base_regs),}863#define SUBLIST_SBI_STA \864 {"sbi-sta", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_STA, \865 .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}866#define SUBLIST_ZICBOM \867 {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}868#define SUBLIST_ZICBOZ \869 {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}870#define SUBLIST_AIA \871 {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}872#define SUBLIST_SMSTATEEN \873 {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}874#define SUBLIST_FP_F \875 {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \876 .regs_n = ARRAY_SIZE(fp_f_regs),}877#define SUBLIST_FP_D \878 {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \879 .regs_n = ARRAY_SIZE(fp_d_regs),}880 881#define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \882static __u64 regs_##ext[] = { \883 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \884 KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \885 KVM_RISCV_ISA_EXT_##extu, \886}; \887static struct vcpu_reg_list config_##ext = { \888 .sublists = { \889 SUBLIST_BASE, \890 { \891 .name = #ext, \892 .feature = KVM_RISCV_ISA_EXT_##extu, \893 .regs = regs_##ext, \894 .regs_n = ARRAY_SIZE(regs_##ext), \895 }, \896 {0}, \897 }, \898} \899 900#define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \901static __u64 regs_sbi_##ext[] = { \902 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \903 KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \904 KVM_RISCV_SBI_EXT_##extu, \905}; \906static struct vcpu_reg_list config_sbi_##ext = { \907 .sublists = { \908 SUBLIST_BASE, \909 { \910 .name = "sbi-"#ext, \911 .feature_type = VCPU_FEATURE_SBI_EXT, \912 .feature = KVM_RISCV_SBI_EXT_##extu, \913 .regs = regs_sbi_##ext, \914 .regs_n = ARRAY_SIZE(regs_sbi_##ext), \915 }, \916 {0}, \917 }, \918} \919 920#define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \921static struct vcpu_reg_list config_##ext = { \922 .sublists = { \923 SUBLIST_BASE, \924 SUBLIST_##extu, \925 {0}, \926 }, \927} \928 929#define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu) \930static struct vcpu_reg_list config_sbi_##ext = { \931 .sublists = { \932 SUBLIST_BASE, \933 SUBLIST_SBI_##extu, \934 {0}, \935 }, \936} \937 938/* Note: The below list is alphabetically sorted. */939 940KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);941KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA);942KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU);943KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN);944 945KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);946KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);947KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);948KVM_ISA_EXT_SIMPLE_CONFIG(h, H);949KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);950KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);951KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);952KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);953KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);954KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);955KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);956KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);957KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);958KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);959KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);960KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);961KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);962KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);963KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);964KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);965KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);966KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);967KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);968KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);969KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);970KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);971KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);972KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);973KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);974KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);975KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);976KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);977KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);978KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);979KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);980KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);981KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP);982KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);983KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);984KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH);985KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);986KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);987KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);988KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);989KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);990KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);991KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);992KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);993KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);994KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);995KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);996KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);997KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);998KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);999KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);1000KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);1001KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);1002 1003struct vcpu_reg_list *vcpu_configs[] = {1004 &config_sbi_base,1005 &config_sbi_sta,1006 &config_sbi_pmu,1007 &config_sbi_dbcn,1008 &config_aia,1009 &config_fp_f,1010 &config_fp_d,1011 &config_h,1012 &config_smstateen,1013 &config_sscofpmf,1014 &config_sstc,1015 &config_svinval,1016 &config_svnapot,1017 &config_svpbmt,1018 &config_zacas,1019 &config_zawrs,1020 &config_zba,1021 &config_zbb,1022 &config_zbc,1023 &config_zbkb,1024 &config_zbkc,1025 &config_zbkx,1026 &config_zbs,1027 &config_zca,1028 &config_zcb,1029 &config_zcd,1030 &config_zcf,1031 &config_zcmop,1032 &config_zfa,1033 &config_zfh,1034 &config_zfhmin,1035 &config_zicbom,1036 &config_zicboz,1037 &config_zicntr,1038 &config_zicond,1039 &config_zicsr,1040 &config_zifencei,1041 &config_zihintntl,1042 &config_zihintpause,1043 &config_zihpm,1044 &config_zimop,1045 &config_zknd,1046 &config_zkne,1047 &config_zknh,1048 &config_zkr,1049 &config_zksed,1050 &config_zksh,1051 &config_zkt,1052 &config_ztso,1053 &config_zvbb,1054 &config_zvbc,1055 &config_zvfh,1056 &config_zvfhmin,1057 &config_zvkb,1058 &config_zvkg,1059 &config_zvkned,1060 &config_zvknha,1061 &config_zvknhb,1062 &config_zvksed,1063 &config_zvksh,1064 &config_zvkt,1065};1066int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);1067