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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2014, Michael Ellerman, IBM Corp.4 */5 6#ifndef _SELFTESTS_POWERPC_REG_H7#define _SELFTESTS_POWERPC_REG_H8 9#define __stringify_1(x) #x10#define __stringify(x) __stringify_1(x)11 12#define mfspr(rn) ({unsigned long rval; \13 asm volatile("mfspr %0," _str(rn) \14 : "=r" (rval)); rval; })15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \16 : "r" ((unsigned long)(v)) \17 : "memory")18 19#define mb() asm volatile("sync" : : : "memory");20#define barrier() asm volatile("" : : : "memory");21 22#define SPRN_HDEXCR_RO 455 /* Userspace readonly view of SPRN_HDEXCR (471) */23 24#define SPRN_MMCR2 76925#define SPRN_MMCRA 77026#define SPRN_MMCR0 77927#define MMCR0_PMAO 0x0000008028#define MMCR0_PMAE 0x0400000029#define MMCR0_FC 0x8000000030#define SPRN_EBBHR 80431#define SPRN_EBBRR 80532#define SPRN_BESCR 806 /* Branch event status & control register */33#define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */34#define SPRN_BESCRSU 801 /* Branch event status & control set upper */35#define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */36#define SPRN_BESCRRU 803 /* Branch event status & control REset upper */37 38#define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */39#define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */40 41#define SPRN_PMC1 77142#define SPRN_PMC2 77243#define SPRN_PMC3 77344#define SPRN_PMC4 77445#define SPRN_PMC5 77546#define SPRN_PMC6 77647 48#define SPRN_SIAR 78049#define SPRN_SDAR 78150#define SPRN_SIER 76851 52#define SPRN_DEXCR_RO 812 /* Userspace readonly view of SPRN_DEXCR (828) */53 54#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */55#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */56#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */57#define SPRN_TAR 0x32f /* Target Address Register */58 59#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)60#define SPRN_PVR 0x11F61 62#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */63#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */64#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */65 66#define SPRN_DSCR_PRIV 0x11 /* Privilege State DSCR */67#define SPRN_DSCR 0x03 /* Data Stream Control Register */68#define SPRN_PPR 896 /* Program Priority Register */69#define SPRN_AMR 13 /* Authority Mask Register - problem state */70 71#define set_amr(v) asm volatile("isync;" \72 "mtspr " __stringify(SPRN_AMR) ",%0;" \73 "isync" : \74 : "r" ((unsigned long)(v)) \75 : "memory")76 77/* TEXASR register bits */78#define TEXASR_FC 0xFE0000000000000079#define TEXASR_FP 0x010000000000000080#define TEXASR_DA 0x008000000000000081#define TEXASR_NO 0x004000000000000082#define TEXASR_FO 0x002000000000000083#define TEXASR_SIC 0x001000000000000084#define TEXASR_NTC 0x000800000000000085#define TEXASR_TC 0x000400000000000086#define TEXASR_TIC 0x000200000000000087#define TEXASR_IC 0x000100000000000088#define TEXASR_IFC 0x000080000000000089#define TEXASR_ABT 0x000000010000000090#define TEXASR_SPD 0x000000008000000091#define TEXASR_HV 0x000000002000000092#define TEXASR_PR 0x000000001000000093#define TEXASR_FS 0x000000000800000094#define TEXASR_TE 0x000000000400000095#define TEXASR_ROT 0x000000000200000096 97/* MSR register bits */98#define MSR_HV (1ul << 60) /* Hypervisor state */99#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */100#define MSR_TS_T_LG 34 /* Trans Mem state: Active */101 102#define __MASK(X) (1UL<<(X))103 104/* macro to check TM MSR bits */105#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */106#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */107 108/* Vector Instructions */109#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \110 ((rb) << 11) | (((xs) >> 5)))111#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))112#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))113 114#define ASM_LOAD_GPR_IMMED(_asm_symbol_name_immed) \115 "li 14, %[" #_asm_symbol_name_immed "];" \116 "li 15, %[" #_asm_symbol_name_immed "];" \117 "li 16, %[" #_asm_symbol_name_immed "];" \118 "li 17, %[" #_asm_symbol_name_immed "];" \119 "li 18, %[" #_asm_symbol_name_immed "];" \120 "li 19, %[" #_asm_symbol_name_immed "];" \121 "li 20, %[" #_asm_symbol_name_immed "];" \122 "li 21, %[" #_asm_symbol_name_immed "];" \123 "li 22, %[" #_asm_symbol_name_immed "];" \124 "li 23, %[" #_asm_symbol_name_immed "];" \125 "li 24, %[" #_asm_symbol_name_immed "];" \126 "li 25, %[" #_asm_symbol_name_immed "];" \127 "li 26, %[" #_asm_symbol_name_immed "];" \128 "li 27, %[" #_asm_symbol_name_immed "];" \129 "li 28, %[" #_asm_symbol_name_immed "];" \130 "li 29, %[" #_asm_symbol_name_immed "];" \131 "li 30, %[" #_asm_symbol_name_immed "];" \132 "li 31, %[" #_asm_symbol_name_immed "];"133 134#define ASM_LOAD_FPR(_asm_symbol_name_addr) \135 "lfd 0, 0(%[" #_asm_symbol_name_addr "]);" \136 "lfd 1, 0(%[" #_asm_symbol_name_addr "]);" \137 "lfd 2, 0(%[" #_asm_symbol_name_addr "]);" \138 "lfd 3, 0(%[" #_asm_symbol_name_addr "]);" \139 "lfd 4, 0(%[" #_asm_symbol_name_addr "]);" \140 "lfd 5, 0(%[" #_asm_symbol_name_addr "]);" \141 "lfd 6, 0(%[" #_asm_symbol_name_addr "]);" \142 "lfd 7, 0(%[" #_asm_symbol_name_addr "]);" \143 "lfd 8, 0(%[" #_asm_symbol_name_addr "]);" \144 "lfd 9, 0(%[" #_asm_symbol_name_addr "]);" \145 "lfd 10, 0(%[" #_asm_symbol_name_addr "]);" \146 "lfd 11, 0(%[" #_asm_symbol_name_addr "]);" \147 "lfd 12, 0(%[" #_asm_symbol_name_addr "]);" \148 "lfd 13, 0(%[" #_asm_symbol_name_addr "]);" \149 "lfd 14, 0(%[" #_asm_symbol_name_addr "]);" \150 "lfd 15, 0(%[" #_asm_symbol_name_addr "]);" \151 "lfd 16, 0(%[" #_asm_symbol_name_addr "]);" \152 "lfd 17, 0(%[" #_asm_symbol_name_addr "]);" \153 "lfd 18, 0(%[" #_asm_symbol_name_addr "]);" \154 "lfd 19, 0(%[" #_asm_symbol_name_addr "]);" \155 "lfd 20, 0(%[" #_asm_symbol_name_addr "]);" \156 "lfd 21, 0(%[" #_asm_symbol_name_addr "]);" \157 "lfd 22, 0(%[" #_asm_symbol_name_addr "]);" \158 "lfd 23, 0(%[" #_asm_symbol_name_addr "]);" \159 "lfd 24, 0(%[" #_asm_symbol_name_addr "]);" \160 "lfd 25, 0(%[" #_asm_symbol_name_addr "]);" \161 "lfd 26, 0(%[" #_asm_symbol_name_addr "]);" \162 "lfd 27, 0(%[" #_asm_symbol_name_addr "]);" \163 "lfd 28, 0(%[" #_asm_symbol_name_addr "]);" \164 "lfd 29, 0(%[" #_asm_symbol_name_addr "]);" \165 "lfd 30, 0(%[" #_asm_symbol_name_addr "]);" \166 "lfd 31, 0(%[" #_asm_symbol_name_addr "]);"167 168#ifndef __ASSEMBLER__169void store_gpr(unsigned long *addr);170void load_gpr(unsigned long *addr);171void store_fpr(double *addr);172#endif /* end of __ASSEMBLER__ */173 174#endif /* _SELFTESTS_POWERPC_REG_H */175