56 lines · cpp
1// RUN: %check_clang_tidy %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction2// RUN: %check_clang_tidy -check-suffix=UPPERCASE %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction/uppercase -DUPPERCASE3 4#ifdef UPPERCASE5// The warning should be triggered regardless of capitalization6#include "KERNEL.cl"7// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'KERNEL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]8#include "vERILOG.cl"9// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'vERILOG.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]10#include "VHDL.cl"11// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'VHDL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]12#else 13// These are the banned kernel filenames, and should trigger warnings14#include "kernel.cl"15// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]16#include "Verilog.cl"17// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'Verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]18#include "vhdl.CL"19// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.CL' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]20 21 22// The warning should be triggered if the names are within a directory23#include "some/dir/kernel.cl"24// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]25#include "somedir/verilog.cl"26// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]27#include "otherdir/vhdl.cl"28// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]29 30// There are no FIX-ITs for the altera-kernel-name-restriction lint check31 32// The following include directives shouldn't trigger the warning33#include "otherthing.cl"34#include "thing.h"35 36// It doesn't make sense to have kernel.h, verilog.h, or vhdl.h as filenames37// without the corresponding .cl files, but the Altera Programming Guide doesn't38// explicitly forbid it.39#include "kernel.h"40#include "verilog.h"41#include "vhdl.h"42 43// The files can still have the forbidden names in them, so long as they're not44// the entire file name, and are not the kernel source file name.45#include "some_kernel.cl"46#include "other_Verilog.cl"47#include "vhdl_number_two.cl"48 49// Naming a directory kernel.cl, verilog.cl, or vhdl.cl is not explicitly50// forbidden in the Altera Programming Guide either.51#include "some/kernel.cl/foo.h"52#include "some/verilog.cl/foo.h"53#include "some/vhdl.cl/foo.h"54#endif55 56