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1//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares AMDGPU TargetInfo objects.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H14#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H15 16#include "clang/Basic/TargetID.h"17#include "clang/Basic/TargetInfo.h"18#include "clang/Basic/TargetOptions.h"19#include "llvm/ADT/StringSet.h"20#include "llvm/Support/AMDGPUAddrSpace.h"21#include "llvm/Support/Compiler.h"22#include "llvm/TargetParser/TargetParser.h"23#include "llvm/TargetParser/Triple.h"24#include <optional>25 26namespace clang {27namespace targets {28 29class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {30 31 static const char *const GCCRegNames[];32 33 static const LangASMap AMDGPUDefIsGenMap;34 static const LangASMap AMDGPUDefIsPrivMap;35 36 llvm::AMDGPU::GPUKind GPUKind;37 unsigned GPUFeatures;38 unsigned WavefrontSize;39 40 /// Whether to use cumode or WGP mode. True for cumode. False for WGP mode.41 bool CUMode;42 43 /// Whether having image instructions.44 bool HasImage = false;45 46 /// Target ID is device name followed by optional feature name postfixed47 /// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-.48 /// If the target ID contains feature+, map it to true.49 /// If the target ID contains feature-, map it to false.50 /// If the target ID does not contain a feature (default), do not map it.51 llvm::StringMap<bool> OffloadArchFeatures;52 std::string TargetID;53 54 bool hasFP64() const {55 return getTriple().isAMDGCN() ||56 !!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);57 }58 59 /// Has fast fma f3260 bool hasFastFMAF() const {61 return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32);62 }63 64 /// Has fast fma f6465 bool hasFastFMA() const { return getTriple().isAMDGCN(); }66 67 bool hasFMAF() const {68 return getTriple().isAMDGCN() ||69 !!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);70 }71 72 bool hasFullRateDenormalsF32() const {73 return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32);74 }75 76 bool hasLDEXPF() const {77 return getTriple().isAMDGCN() ||78 !!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);79 }80 81 static bool isAMDGCN(const llvm::Triple &TT) { return TT.isAMDGCN(); }82 83 static bool isR600(const llvm::Triple &TT) {84 return TT.getArch() == llvm::Triple::r600;85 }86 87public:88 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);89 90 void setAddressSpaceMap(bool DefaultIsPrivate);91 92 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts,93 const TargetInfo *Aux) override;94 95 uint64_t getPointerWidthV(LangAS AS) const override {96 if (isR600(getTriple()))97 return 32;98 unsigned TargetAS = getTargetAddressSpace(AS);99 100 if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS ||101 TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS)102 return 32;103 104 return 64;105 }106 107 uint64_t getPointerAlignV(LangAS AddrSpace) const override {108 return getPointerWidthV(AddrSpace);109 }110 111 virtual bool isAddressSpaceSupersetOf(LangAS A, LangAS B) const override {112 // The flat address space AS(0) is a superset of all the other address113 // spaces used by the backend target.114 return A == B ||115 ((A == LangAS::Default ||116 (isTargetAddressSpace(A) &&117 toTargetAddressSpace(A) == llvm::AMDGPUAS::FLAT_ADDRESS)) &&118 isTargetAddressSpace(B) &&119 toTargetAddressSpace(B) >= llvm::AMDGPUAS::FLAT_ADDRESS &&120 toTargetAddressSpace(B) <= llvm::AMDGPUAS::PRIVATE_ADDRESS &&121 toTargetAddressSpace(B) != llvm::AMDGPUAS::REGION_ADDRESS);122 }123 124 uint64_t getMaxPointerWidth() const override {125 return getTriple().isAMDGCN() ? 64 : 32;126 }127 128 bool hasBFloat16Type() const override { return isAMDGCN(getTriple()); }129 130 std::string_view getClobbers() const override { return ""; }131 132 ArrayRef<const char *> getGCCRegNames() const override;133 134 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {135 return {};136 }137 138 /// Accepted register names: (n, m is unsigned integer, n < m)139 /// v140 /// s141 /// a142 /// {vn}, {v[n]}143 /// {sn}, {s[n]}144 /// {an}, {a[n]}145 /// {S} , where S is a special register name146 ////{v[n:m]}147 /// {s[n:m]}148 /// {a[n:m]}149 bool validateAsmConstraint(const char *&Name,150 TargetInfo::ConstraintInfo &Info) const override {151 static const ::llvm::StringSet<> SpecialRegs({152 "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",153 "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",154 "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",155 });156 157 switch (*Name) {158 case 'I':159 Info.setRequiresImmediate(-16, 64);160 return true;161 case 'J':162 Info.setRequiresImmediate(-32768, 32767);163 return true;164 case 'A':165 case 'B':166 case 'C':167 Info.setRequiresImmediate();168 return true;169 default:170 break;171 }172 173 StringRef S(Name);174 175 if (S == "DA" || S == "DB") {176 Name++;177 Info.setRequiresImmediate();178 return true;179 }180 181 bool HasLeftParen = S.consume_front("{");182 if (S.empty())183 return false;184 if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') {185 if (!HasLeftParen)186 return false;187 auto E = S.find('}');188 if (!SpecialRegs.count(S.substr(0, E)))189 return false;190 S = S.drop_front(E + 1);191 if (!S.empty())192 return false;193 // Found {S} where S is a special register.194 Info.setAllowsRegister();195 Name = S.data() - 1;196 return true;197 }198 S = S.drop_front();199 if (!HasLeftParen) {200 if (!S.empty())201 return false;202 // Found s, v or a.203 Info.setAllowsRegister();204 Name = S.data() - 1;205 return true;206 }207 bool HasLeftBracket = S.consume_front("[");208 unsigned long long N;209 if (S.empty() || consumeUnsignedInteger(S, 10, N))210 return false;211 if (S.consume_front(":")) {212 if (!HasLeftBracket)213 return false;214 unsigned long long M;215 if (consumeUnsignedInteger(S, 10, M) || N >= M)216 return false;217 }218 if (HasLeftBracket) {219 if (!S.consume_front("]"))220 return false;221 }222 if (!S.consume_front("}"))223 return false;224 if (!S.empty())225 return false;226 // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}227 // or {a[n:m]}.228 Info.setAllowsRegister();229 Name = S.data() - 1;230 return true;231 }232 233 // \p Constraint will be left pointing at the last character of234 // the constraint. In practice, it won't be changed unless the235 // constraint is longer than one character.236 std::string convertConstraint(const char *&Constraint) const override {237 238 StringRef S(Constraint);239 if (S == "DA" || S == "DB") {240 return std::string("^") + std::string(Constraint++, 2);241 }242 243 const char *Begin = Constraint;244 TargetInfo::ConstraintInfo Info("", "");245 if (validateAsmConstraint(Constraint, Info))246 return std::string(Begin).substr(0, Constraint - Begin + 1);247 248 Constraint = Begin;249 return std::string(1, *Constraint);250 }251 252 bool253 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,254 StringRef CPU,255 const std::vector<std::string> &FeatureVec) const override;256 257 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;258 259 bool useFP16ConversionIntrinsics() const override { return false; }260 261 void getTargetDefines(const LangOptions &Opts,262 MacroBuilder &Builder) const override;263 264 BuiltinVaListKind getBuiltinVaListKind() const override {265 return TargetInfo::CharPtrBuiltinVaList;266 }267 268 bool isValidCPUName(StringRef Name) const override {269 if (getTriple().isAMDGCN())270 return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;271 return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;272 }273 274 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;275 276 bool setCPU(const std::string &Name) override {277 if (getTriple().isAMDGCN()) {278 GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);279 GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);280 } else {281 GPUKind = llvm::AMDGPU::parseArchR600(Name);282 GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind);283 }284 285 return GPUKind != llvm::AMDGPU::GK_NONE;286 }287 288 void setSupportedOpenCLOpts() override {289 auto &Opts = getSupportedOpenCLOpts();290 Opts["cl_clang_storage_class_specifiers"] = true;291 Opts["__cl_clang_variadic_functions"] = true;292 Opts["__cl_clang_function_pointers"] = true;293 Opts["__cl_clang_non_portable_kernel_param_types"] = true;294 Opts["__cl_clang_bitfields"] = true;295 296 bool IsAMDGCN = isAMDGCN(getTriple());297 298 Opts["cl_khr_fp64"] = hasFP64();299 Opts["__opencl_c_fp64"] = hasFP64();300 301 if (IsAMDGCN || GPUKind >= llvm::AMDGPU::GK_CEDAR) {302 Opts["cl_khr_byte_addressable_store"] = true;303 Opts["cl_khr_global_int32_base_atomics"] = true;304 Opts["cl_khr_global_int32_extended_atomics"] = true;305 Opts["cl_khr_local_int32_base_atomics"] = true;306 Opts["cl_khr_local_int32_extended_atomics"] = true;307 }308 309 if (IsAMDGCN) {310 Opts["cl_khr_fp16"] = true;311 Opts["cl_khr_int64_base_atomics"] = true;312 Opts["cl_khr_int64_extended_atomics"] = true;313 Opts["cl_khr_mipmap_image"] = true;314 Opts["cl_khr_mipmap_image_writes"] = true;315 Opts["cl_khr_subgroups"] = true;316 Opts["cl_amd_media_ops"] = true;317 Opts["cl_amd_media_ops2"] = true;318 319 Opts["__opencl_c_images"] = true;320 Opts["__opencl_c_3d_image_writes"] = true;321 Opts["cl_khr_3d_image_writes"] = true;322 Opts["__opencl_c_program_scope_global_variables"] = true;323 Opts["__opencl_c_atomic_order_seq_cst"] = true;324 Opts["__opencl_c_atomic_scope_all_devices"] = true;325 326 if (GPUKind >= llvm::AMDGPU::GK_GFX700) {327 Opts["__opencl_c_generic_address_space"] = true;328 Opts["__opencl_c_device_enqueue"] = true;329 }330 }331 }332 333 LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {334 switch (TK) {335 case OCLTK_Image:336 return LangAS::opencl_constant;337 338 case OCLTK_ClkEvent:339 case OCLTK_Queue:340 case OCLTK_ReserveID:341 return LangAS::opencl_global;342 343 default:344 return TargetInfo::getOpenCLTypeAddrSpace(TK);345 }346 }347 348 LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {349 switch (AS) {350 case 0:351 return LangAS::opencl_generic;352 case 1:353 return LangAS::opencl_global;354 case 3:355 return LangAS::opencl_local;356 case 4:357 return LangAS::opencl_constant;358 case 5:359 return LangAS::opencl_private;360 default:361 return getLangASFromTargetAS(AS);362 }363 }364 365 LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {366 switch (AS) {367 case 0:368 return LangAS::Default;369 case 1:370 return LangAS::cuda_device;371 case 3:372 return LangAS::cuda_shared;373 case 4:374 return LangAS::cuda_constant;375 default:376 return getLangASFromTargetAS(AS);377 }378 }379 380 std::optional<LangAS> getConstantAddressSpace() const override {381 return getLangASFromTargetAS(llvm::AMDGPUAS::CONSTANT_ADDRESS);382 }383 384 const llvm::omp::GV &getGridValue() const override {385 switch (WavefrontSize) {386 case 32:387 return llvm::omp::getAMDGPUGridValues<32>();388 case 64:389 return llvm::omp::getAMDGPUGridValues<64>();390 default:391 llvm_unreachable("getGridValue not implemented for this wavesize");392 }393 }394 395 /// \returns Target specific vtbl ptr address space.396 unsigned getVtblPtrAddressSpace() const override {397 return static_cast<unsigned>(llvm::AMDGPUAS::CONSTANT_ADDRESS);398 }399 400 /// \returns If a target requires an address within a target specific address401 /// space \p AddressSpace to be converted in order to be used, then return the402 /// corresponding target specific DWARF address space.403 ///404 /// \returns Otherwise return std::nullopt and no conversion will be emitted405 /// in the DWARF.406 std::optional<unsigned>407 getDWARFAddressSpace(unsigned AddressSpace) const override {408 int DWARFAS = llvm::AMDGPU::mapToDWARFAddrSpace(AddressSpace);409 // If there is no corresponding address space identifier, or it would be410 // the default, then don't emit the attribute.411 if (DWARFAS == -1 || DWARFAS == llvm::AMDGPU::DWARFAS::DEFAULT)412 return std::nullopt;413 return DWARFAS;414 }415 416 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {417 switch (CC) {418 default:419 return CCCR_Warning;420 case CC_C:421 case CC_DeviceKernel:422 return CCCR_OK;423 }424 }425 426 // In amdgcn target the null pointer in global, constant, and generic427 // address space has value 0 but in private and local address space has428 // value ~0.429 uint64_t getNullPointerValue(LangAS AS) const override {430 // FIXME: Also should handle region.431 return (AS == LangAS::opencl_local || AS == LangAS::opencl_private ||432 AS == LangAS::sycl_local || AS == LangAS::sycl_private)433 ? ~0434 : 0;435 }436 437 void setAuxTarget(const TargetInfo *Aux) override;438 439 bool hasBitIntType() const override { return true; }440 441 // Record offload arch features since they are needed for defining the442 // pre-defined macros.443 bool handleTargetFeatures(std::vector<std::string> &Features,444 DiagnosticsEngine &Diags) override {445 HasFullBFloat16 = true;446 auto TargetIDFeatures =447 getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind));448 for (const auto &F : Features) {449 assert(F.front() == '+' || F.front() == '-');450 if (F == "+wavefrontsize64")451 WavefrontSize = 64;452 else if (F == "+cumode")453 CUMode = true;454 else if (F == "-cumode")455 CUMode = false;456 else if (F == "+image-insts")457 HasImage = true;458 bool IsOn = F.front() == '+';459 StringRef Name = StringRef(F).drop_front();460 if (!llvm::is_contained(TargetIDFeatures, Name))461 continue;462 assert(!OffloadArchFeatures.contains(Name));463 OffloadArchFeatures[Name] = IsOn;464 }465 return true;466 }467 468 std::optional<std::string> getTargetID() const override {469 if (!isAMDGCN(getTriple()))470 return std::nullopt;471 // When -target-cpu is not set, we assume generic code that it is valid472 // for all GPU and use an empty string as target ID to represent that.473 if (GPUKind == llvm::AMDGPU::GK_NONE)474 return std::string("");475 return getCanonicalTargetID(getArchNameAMDGCN(GPUKind),476 OffloadArchFeatures);477 }478 479 bool hasHIPImageSupport() const override { return HasImage; }480 481 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {482 // This is imprecise as the value can vary between 64, 128 (even 256!) bytes483 // depending on the level of cache and the target architecture. We select484 // the size that corresponds to the largest L1 cache line for all485 // architectures.486 return std::make_pair(128, 128);487 }488};489 490} // namespace targets491} // namespace clang492 493#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H494