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1//===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares ARM TargetInfo objects.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H14#define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H15 16#include "OSTargets.h"17#include "clang/Basic/TargetInfo.h"18#include "clang/Basic/TargetOptions.h"19#include "llvm/Support/Compiler.h"20#include "llvm/TargetParser/ARMTargetParser.h"21#include "llvm/TargetParser/ARMTargetParserCommon.h"22#include "llvm/TargetParser/Triple.h"23 24namespace clang {25namespace targets {26 27class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {28 // Possible FPU choices.29 enum FPUMode {30 VFP2FPU = (1 << 0),31 VFP3FPU = (1 << 1),32 VFP4FPU = (1 << 2),33 NeonFPU = (1 << 3),34 FPARMV8 = (1 << 4)35 };36 37 enum MVEMode {38 MVE_INT = (1 << 0),39 MVE_FP = (1 << 1)40 };41 42 // Possible HWDiv features.43 enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };44 45 static bool FPUModeIsVFP(FPUMode Mode) {46 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);47 }48 49 static const TargetInfo::GCCRegAlias GCCRegAliases[];50 static const char *const GCCRegNames[];51 52 std::string ABI, CPU;53 54 StringRef CPUProfile;55 StringRef CPUAttr;56 57 enum { FP_Default, FP_VFP, FP_Neon } FPMath;58 59 llvm::ARM::ISAKind ArchISA;60 llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;61 llvm::ARM::ProfileKind ArchProfile;62 unsigned ArchVersion;63 64 LLVM_PREFERRED_TYPE(FPUMode)65 unsigned FPU : 5;66 LLVM_PREFERRED_TYPE(MVEMode)67 unsigned MVE : 2;68 69 LLVM_PREFERRED_TYPE(bool)70 unsigned IsAAPCS : 1;71 LLVM_PREFERRED_TYPE(HWDivMode)72 unsigned HWDiv : 2;73 74 // Initialized via features.75 LLVM_PREFERRED_TYPE(bool)76 unsigned SoftFloat : 1;77 LLVM_PREFERRED_TYPE(bool)78 unsigned SoftFloatABI : 1;79 80 LLVM_PREFERRED_TYPE(bool)81 unsigned CRC : 1;82 LLVM_PREFERRED_TYPE(bool)83 unsigned Crypto : 1;84 LLVM_PREFERRED_TYPE(bool)85 unsigned SHA2 : 1;86 LLVM_PREFERRED_TYPE(bool)87 unsigned AES : 1;88 LLVM_PREFERRED_TYPE(bool)89 unsigned DSP : 1;90 LLVM_PREFERRED_TYPE(bool)91 unsigned DotProd : 1;92 LLVM_PREFERRED_TYPE(bool)93 unsigned HasMatMul : 1;94 LLVM_PREFERRED_TYPE(bool)95 unsigned FPRegsDisabled : 1;96 LLVM_PREFERRED_TYPE(bool)97 unsigned HasPAC : 1;98 LLVM_PREFERRED_TYPE(bool)99 unsigned HasBTI : 1;100 101 uint32_t LDREX;102 103 // ACLE 6.5.1 Hardware floating point104 enum {105 HW_FP_HP = (1 << 1), /// half (16-bit)106 HW_FP_SP = (1 << 2), /// single (32-bit)107 HW_FP_DP = (1 << 3), /// double (64-bit)108 };109 uint32_t HW_FP;110 111 enum {112 /// __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc,113 /// __arm_stcl, __arm_mcr and __arm_mrc114 FEATURE_COPROC_B1 = (1 << 0),115 /// __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l,116 /// __arm_stc2l, __arm_mcr2 and __arm_mrc2117 FEATURE_COPROC_B2 = (1 << 1),118 /// __arm_mcrr, __arm_mrrc119 FEATURE_COPROC_B3 = (1 << 2),120 /// __arm_mcrr2, __arm_mrrc2121 FEATURE_COPROC_B4 = (1 << 3),122 };123 124 void setABIAAPCS();125 void setABIAPCS(bool IsAAPCS16);126 127 void setArchInfo();128 void setArchInfo(llvm::ARM::ArchKind Kind);129 130 void setAtomic();131 132 bool isThumb() const;133 bool supportsThumb() const;134 bool supportsThumb2() const;135 bool hasMVE() const;136 bool hasMVEFloat() const;137 bool hasCDE() const;138 139 StringRef getCPUAttr() const;140 StringRef getCPUProfile() const;141 142public:143 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);144 145 StringRef getABI() const override;146 bool setABI(const std::string &Name) override;147 148 bool isBranchProtectionSupportedArch(StringRef Arch) const override;149 bool validateBranchProtection(StringRef Spec, StringRef Arch,150 BranchProtectionInfo &BPI,151 const LangOptions &LO,152 StringRef &Err) const override;153 154 // FIXME: This should be based on Arch attributes, not CPU names.155 bool156 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,157 StringRef CPU,158 const std::vector<std::string> &FeaturesVec) const override;159 160 bool isValidFeatureName(StringRef Feature) const override {161 // We pass soft-float-abi in as a -target-feature, but the backend figures162 // this out through other means.163 return Feature != "soft-float-abi";164 }165 166 bool handleTargetFeatures(std::vector<std::string> &Features,167 DiagnosticsEngine &Diags) override;168 169 bool hasFeature(StringRef Feature) const override;170 171 bool hasBFloat16Type() const override;172 173 bool isValidCPUName(StringRef Name) const override;174 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;175 176 bool setCPU(const std::string &Name) override;177 178 bool setFPMath(StringRef Name) override;179 180 bool useFP16ConversionIntrinsics() const override {181 return false;182 }183 184 void getTargetDefinesARMV81A(const LangOptions &Opts,185 MacroBuilder &Builder) const;186 void getTargetDefinesARMV82A(const LangOptions &Opts,187 MacroBuilder &Builder) const;188 void getTargetDefinesARMV83A(const LangOptions &Opts,189 MacroBuilder &Builder) const;190 void getTargetDefines(const LangOptions &Opts,191 MacroBuilder &Builder) const override;192 193 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;194 195 bool isCLZForZeroUndef() const override;196 BuiltinVaListKind getBuiltinVaListKind() const override;197 198 ArrayRef<const char *> getGCCRegNames() const override;199 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;200 bool validateAsmConstraint(const char *&Name,201 TargetInfo::ConstraintInfo &Info) const override;202 std::string convertConstraint(const char *&Constraint) const override;203 bool204 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,205 std::string &SuggestedModifier) const override;206 std::string_view getClobbers() const override;207 208 StringRef getConstraintRegister(StringRef Constraint,209 StringRef Expression) const override {210 return Expression;211 }212 213 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;214 215 int getEHDataRegisterNumber(unsigned RegNo) const override;216 217 bool hasSjLjLowering() const override;218 219 bool hasBitIntType() const override { return true; }220 221 unsigned getARMLDREXMask() const override { return LDREX; }222 223 const char *getBFloat16Mangling() const override { return "u6__bf16"; };224 225 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {226 return std::make_pair(64, 64);227 }228};229 230class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo {231public:232 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);233 void getTargetDefines(const LangOptions &Opts,234 MacroBuilder &Builder) const override;235};236 237class LLVM_LIBRARY_VISIBILITY ARMbeTargetInfo : public ARMTargetInfo {238public:239 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);240 void getTargetDefines(const LangOptions &Opts,241 MacroBuilder &Builder) const override;242};243 244class LLVM_LIBRARY_VISIBILITY WindowsARMTargetInfo245 : public WindowsTargetInfo<ARMleTargetInfo> {246 const llvm::Triple Triple;247 248public:249 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);250 251 void getVisualStudioDefines(const LangOptions &Opts,252 MacroBuilder &Builder) const;253 254 BuiltinVaListKind getBuiltinVaListKind() const override;255 256 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;257};258 259// Windows ARM + Itanium C++ ABI Target260class LLVM_LIBRARY_VISIBILITY ItaniumWindowsARMleTargetInfo261 : public WindowsARMTargetInfo {262public:263 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple,264 const TargetOptions &Opts);265 266 void getTargetDefines(const LangOptions &Opts,267 MacroBuilder &Builder) const override;268};269 270// Windows ARM, MS (C++) ABI271class LLVM_LIBRARY_VISIBILITY MicrosoftARMleTargetInfo272 : public WindowsARMTargetInfo {273public:274 MicrosoftARMleTargetInfo(const llvm::Triple &Triple,275 const TargetOptions &Opts);276 277 void getTargetDefines(const LangOptions &Opts,278 MacroBuilder &Builder) const override;279};280 281// ARM MinGW target282class LLVM_LIBRARY_VISIBILITY MinGWARMTargetInfo : public WindowsARMTargetInfo {283public:284 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);285 286 void getTargetDefines(const LangOptions &Opts,287 MacroBuilder &Builder) const override;288};289 290// ARM Cygwin target291class LLVM_LIBRARY_VISIBILITY CygwinARMTargetInfo : public ARMleTargetInfo {292public:293 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);294 295 void getTargetDefines(const LangOptions &Opts,296 MacroBuilder &Builder) const override;297};298 299class LLVM_LIBRARY_VISIBILITY AppleMachOARMTargetInfo300 : public AppleMachOTargetInfo<ARMleTargetInfo> {301protected:302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,303 MacroBuilder &Builder) const override;304 305public:306 AppleMachOARMTargetInfo(const llvm::Triple &Triple,307 const TargetOptions &Opts);308};309 310class LLVM_LIBRARY_VISIBILITY DarwinARMTargetInfo311 : public DarwinTargetInfo<ARMleTargetInfo> {312protected:313 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,314 MacroBuilder &Builder) const override;315 316public:317 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);318};319 320} // namespace targets321} // namespace clang322 323#endif // LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H324