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1//===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file declares Hexagon TargetInfo objects.10//11//===----------------------------------------------------------------------===//12 13#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H14#define LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H15 16#include "clang/Basic/TargetInfo.h"17#include "clang/Basic/TargetOptions.h"18#include "llvm/Support/Compiler.h"19#include "llvm/TargetParser/Triple.h"20#include <optional>21 22namespace clang {23namespace targets {24 25// Hexagon abstract base class26class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {27 28 static const char *const GCCRegNames[];29 static const TargetInfo::GCCRegAlias GCCRegAliases[];30 std::string CPU;31 std::string HVXVersion;32 bool HasHVX = false;33 bool HasHVX64B = false;34 bool HasHVX128B = false;35 bool HasAudio = false;36 bool UseLongCalls = false;37 38public:39 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &)40 : TargetInfo(Triple) {41 // Specify the vector alignment explicitly. For v512x1, the calculated42 // alignment would be 512*alignment(i1), which is 512 bytes, instead of43 // the required minimum of 64 bytes.44 resetDataLayout(45 "e-m:e-p:32:32:32-a:0-n16:32-"46 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"47 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048");48 SizeType = UnsignedInt;49 PtrDiffType = SignedInt;50 IntPtrType = SignedInt;51 52 // {} in inline assembly are packet specifiers, not assembly variant53 // specifiers.54 NoAsmVariants = true;55 56 LargeArrayMinWidth = 64;57 LargeArrayAlign = 64;58 UseBitFieldTypeAlignment = true;59 ZeroLengthBitfieldBoundary = 32;60 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;61 62 // These are the default values anyway, but explicitly make sure63 // that the size of the boolean type is 8 bits. Bool vectors are used64 // for modeling predicate registers in HVX, and the bool -> byte65 // correspondence matches the HVX architecture.66 BoolWidth = BoolAlign = 8;67 BFloat16Width = BFloat16Align = 16;68 BFloat16Format = &llvm::APFloat::BFloat();69 }70 71 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;72 73 bool validateAsmConstraint(const char *&Name,74 TargetInfo::ConstraintInfo &Info) const override {75 switch (*Name) {76 case 'v':77 case 'q':78 if (HasHVX) {79 Info.setAllowsRegister();80 return true;81 }82 break;83 case 'a': // Modifier register m0-m1.84 Info.setAllowsRegister();85 return true;86 case 's':87 // Relocatable constant.88 return true;89 }90 return false;91 }92 93 void getTargetDefines(const LangOptions &Opts,94 MacroBuilder &Builder) const override;95 96 bool isCLZForZeroUndef() const override { return false; }97 98 bool hasFeature(StringRef Feature) const override;99 100 bool hasBFloat16Type() const override;101 102 bool103 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,104 StringRef CPU,105 const std::vector<std::string> &FeaturesVec) const override;106 107 bool handleTargetFeatures(std::vector<std::string> &Features,108 DiagnosticsEngine &Diags) override;109 110 BuiltinVaListKind getBuiltinVaListKind() const override {111 if (getTriple().isMusl())112 return TargetInfo::HexagonBuiltinVaList;113 return TargetInfo::CharPtrBuiltinVaList;114 }115 116 ArrayRef<const char *> getGCCRegNames() const override;117 118 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;119 120 std::string_view getClobbers() const override { return ""; }121 122 static const char *getHexagonCPUSuffix(StringRef Name);123 static std::optional<unsigned> getHexagonCPURev(StringRef Name);124 125 bool isValidCPUName(StringRef Name) const override {126 return getHexagonCPUSuffix(Name);127 }128 129 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;130 131 bool setCPU(const std::string &Name) override {132 if (!isValidCPUName(Name))133 return false;134 CPU = Name;135 return true;136 }137 138 int getEHDataRegisterNumber(unsigned RegNo) const override {139 return RegNo < 2 ? RegNo : -1;140 }141 142 bool isTinyCore() const {143 // We can write more stricter checks later.144 return CPU.find('t') != std::string::npos;145 }146 147 bool hasBitIntType() const override { return true; }148 149 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {150 std::optional<unsigned> Rev = getHexagonCPURev(CPU);151 152 // V73 and later have 64-byte cache lines.153 unsigned CacheLineSizeBytes = Rev >= 73U ? 64 : 32;154 return std::make_pair(CacheLineSizeBytes, CacheLineSizeBytes);155 }156};157} // namespace targets158} // namespace clang159#endif // LLVM_CLANG_LIB_BASIC_TARGETS_HEXAGON_H160