195 lines · cpp
1//===--- Sparc.cpp - Implement Sparc target feature support ---------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8//9// This file implements Sparc TargetInfo objects.10//11//===----------------------------------------------------------------------===//12 13#include "Sparc.h"14#include "Targets.h"15#include "clang/Basic/MacroBuilder.h"16#include "llvm/ADT/StringSwitch.h"17 18using namespace clang;19using namespace clang::targets;20 21const char *const SparcTargetInfo::GCCRegNames[] = {22 // clang-format off23 // Integer registers24 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",25 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",26 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",27 28 // Floating-point registers29 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10",30 "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",31 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f32",32 "f34", "f36", "f38", "f40", "f42", "f44", "f46", "f48", "f50", "f52", "f54",33 "f56", "f58", "f60", "f62",34 35 // Condition code registers36 "icc", "fcc0", "fcc1", "fcc2", "fcc3",37 // clang-format on38};39 40ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {41 return llvm::ArrayRef(GCCRegNames);42}43 44const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {45 {{"g0"}, "r0"}, {{"g1"}, "r1"}, {{"g2"}, "r2"}, {{"g3"}, "r3"},46 {{"g4"}, "r4"}, {{"g5"}, "r5"}, {{"g6"}, "r6"}, {{"g7"}, "r7"},47 {{"o0"}, "r8"}, {{"o1"}, "r9"}, {{"o2"}, "r10"}, {{"o3"}, "r11"},48 {{"o4"}, "r12"}, {{"o5"}, "r13"}, {{"o6", "sp"}, "r14"}, {{"o7"}, "r15"},49 {{"l0"}, "r16"}, {{"l1"}, "r17"}, {{"l2"}, "r18"}, {{"l3"}, "r19"},50 {{"l4"}, "r20"}, {{"l5"}, "r21"}, {{"l6"}, "r22"}, {{"l7"}, "r23"},51 {{"i0"}, "r24"}, {{"i1"}, "r25"}, {{"i2"}, "r26"}, {{"i3"}, "r27"},52 {{"i4"}, "r28"}, {{"i5"}, "r29"}, {{"i6", "fp"}, "r30"}, {{"i7"}, "r31"},53};54 55ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {56 return llvm::ArrayRef(GCCRegAliases);57}58 59bool SparcTargetInfo::hasFeature(StringRef Feature) const {60 return llvm::StringSwitch<bool>(Feature)61 .Case("softfloat", SoftFloat)62 .Case("sparc", true)63 .Default(false);64}65 66struct SparcCPUInfo {67 llvm::StringLiteral Name;68 SparcTargetInfo::CPUKind Kind;69 SparcTargetInfo::CPUGeneration Generation;70};71 72static constexpr SparcCPUInfo CPUInfo[] = {73 {{"v8"}, SparcTargetInfo::CK_V8, SparcTargetInfo::CG_V8},74 {{"supersparc"}, SparcTargetInfo::CK_SUPERSPARC, SparcTargetInfo::CG_V8},75 {{"sparclite"}, SparcTargetInfo::CK_SPARCLITE, SparcTargetInfo::CG_V8},76 {{"f934"}, SparcTargetInfo::CK_F934, SparcTargetInfo::CG_V8},77 {{"hypersparc"}, SparcTargetInfo::CK_HYPERSPARC, SparcTargetInfo::CG_V8},78 {{"sparclite86x"},79 SparcTargetInfo::CK_SPARCLITE86X,80 SparcTargetInfo::CG_V8},81 {{"sparclet"}, SparcTargetInfo::CK_SPARCLET, SparcTargetInfo::CG_V8},82 {{"tsc701"}, SparcTargetInfo::CK_TSC701, SparcTargetInfo::CG_V8},83 {{"v9"}, SparcTargetInfo::CK_V9, SparcTargetInfo::CG_V9},84 {{"ultrasparc"}, SparcTargetInfo::CK_ULTRASPARC, SparcTargetInfo::CG_V9},85 {{"ultrasparc3"}, SparcTargetInfo::CK_ULTRASPARC3, SparcTargetInfo::CG_V9},86 {{"niagara"}, SparcTargetInfo::CK_NIAGARA, SparcTargetInfo::CG_V9},87 {{"niagara2"}, SparcTargetInfo::CK_NIAGARA2, SparcTargetInfo::CG_V9},88 {{"niagara3"}, SparcTargetInfo::CK_NIAGARA3, SparcTargetInfo::CG_V9},89 {{"niagara4"}, SparcTargetInfo::CK_NIAGARA4, SparcTargetInfo::CG_V9},90 {{"ma2100"}, SparcTargetInfo::CK_MYRIAD2100, SparcTargetInfo::CG_V8},91 {{"ma2150"}, SparcTargetInfo::CK_MYRIAD2150, SparcTargetInfo::CG_V8},92 {{"ma2155"}, SparcTargetInfo::CK_MYRIAD2155, SparcTargetInfo::CG_V8},93 {{"ma2450"}, SparcTargetInfo::CK_MYRIAD2450, SparcTargetInfo::CG_V8},94 {{"ma2455"}, SparcTargetInfo::CK_MYRIAD2455, SparcTargetInfo::CG_V8},95 {{"ma2x5x"}, SparcTargetInfo::CK_MYRIAD2x5x, SparcTargetInfo::CG_V8},96 {{"ma2080"}, SparcTargetInfo::CK_MYRIAD2080, SparcTargetInfo::CG_V8},97 {{"ma2085"}, SparcTargetInfo::CK_MYRIAD2085, SparcTargetInfo::CG_V8},98 {{"ma2480"}, SparcTargetInfo::CK_MYRIAD2480, SparcTargetInfo::CG_V8},99 {{"ma2485"}, SparcTargetInfo::CK_MYRIAD2485, SparcTargetInfo::CG_V8},100 {{"ma2x8x"}, SparcTargetInfo::CK_MYRIAD2x8x, SparcTargetInfo::CG_V8},101 {{"leon2"}, SparcTargetInfo::CK_LEON2, SparcTargetInfo::CG_V8},102 {{"at697e"}, SparcTargetInfo::CK_LEON2_AT697E, SparcTargetInfo::CG_V8},103 {{"at697f"}, SparcTargetInfo::CK_LEON2_AT697F, SparcTargetInfo::CG_V8},104 {{"leon3"}, SparcTargetInfo::CK_LEON3, SparcTargetInfo::CG_V8},105 {{"ut699"}, SparcTargetInfo::CK_LEON3_UT699, SparcTargetInfo::CG_V8},106 {{"gr712rc"}, SparcTargetInfo::CK_LEON3_GR712RC, SparcTargetInfo::CG_V8},107 {{"leon4"}, SparcTargetInfo::CK_LEON4, SparcTargetInfo::CG_V8},108 {{"gr740"}, SparcTargetInfo::CK_LEON4_GR740, SparcTargetInfo::CG_V8},109};110 111SparcTargetInfo::CPUGeneration112SparcTargetInfo::getCPUGeneration(CPUKind Kind) const {113 if (Kind == CK_GENERIC)114 return CG_V8;115 const SparcCPUInfo *Item = llvm::find_if(116 CPUInfo, [Kind](const SparcCPUInfo &Info) { return Info.Kind == Kind; });117 if (Item == std::end(CPUInfo))118 llvm_unreachable("Unexpected CPU kind");119 return Item->Generation;120}121 122SparcTargetInfo::CPUKind SparcTargetInfo::getCPUKind(StringRef Name) const {123 const SparcCPUInfo *Item = llvm::find_if(124 CPUInfo, [Name](const SparcCPUInfo &Info) { return Info.Name == Name; });125 126 if (Item == std::end(CPUInfo))127 return CK_GENERIC;128 return Item->Kind;129}130 131void SparcTargetInfo::fillValidCPUList(132 SmallVectorImpl<StringRef> &Values) const {133 for (const SparcCPUInfo &Info : CPUInfo)134 Values.push_back(Info.Name);135}136 137void SparcTargetInfo::getTargetDefines(const LangOptions &Opts,138 MacroBuilder &Builder) const {139 DefineStd(Builder, "sparc", Opts);140 Builder.defineMacro("__REGISTER_PREFIX__", "");141 142 if (SoftFloat)143 Builder.defineMacro("SOFT_FLOAT", "1");144}145 146void SparcV8TargetInfo::getTargetDefines(const LangOptions &Opts,147 MacroBuilder &Builder) const {148 SparcTargetInfo::getTargetDefines(Opts, Builder);149 if (getTriple().isOSSolaris())150 Builder.defineMacro("__sparcv8");151 else {152 switch (getCPUGeneration(CPU)) {153 case CG_V8:154 Builder.defineMacro("__sparcv8");155 Builder.defineMacro("__sparcv8__");156 break;157 case CG_V9:158 Builder.defineMacro("__sparc_v9__");159 break;160 }161 }162 if (getCPUGeneration(CPU) == CG_V9) {163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");165 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");166 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");167 }168 Builder.defineMacro("__LONG_DOUBLE_128__");169}170 171void SparcV9TargetInfo::getTargetDefines(const LangOptions &Opts,172 MacroBuilder &Builder) const {173 SparcTargetInfo::getTargetDefines(Opts, Builder);174 Builder.defineMacro("__sparcv9");175 Builder.defineMacro("__arch64__");176 // Solaris doesn't need these variants, but the BSDs do.177 if (!getTriple().isOSSolaris()) {178 Builder.defineMacro("__sparc64__");179 Builder.defineMacro("__sparc_v9__");180 Builder.defineMacro("__sparcv9__");181 }182 183 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");184 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");186 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");187}188 189void SparcV9TargetInfo::fillValidCPUList(190 SmallVectorImpl<StringRef> &Values) const {191 for (const SparcCPUInfo &Info : CPUInfo)192 if (Info.Generation == CG_V9)193 Values.push_back(Info.Name);194}195