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1//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===//2//3// The LLVM Compiler Infrastructure4//5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.6// See https://llvm.org/LICENSE.txt for license information.7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception8//9//===----------------------------------------------------------------------===//10//11// This file declares Xtensa TargetInfo objects.12//13//===----------------------------------------------------------------------===//14 15#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H16#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H17 18#include "clang/Basic/TargetInfo.h"19#include "clang/Basic/TargetOptions.h"20#include "llvm/ADT/StringSwitch.h"21#include "llvm/Support/Compiler.h"22#include "llvm/TargetParser/Triple.h"23 24#include "clang/Basic/Builtins.h"25#include "clang/Basic/MacroBuilder.h"26#include "clang/Basic/TargetBuiltins.h"27 28namespace clang {29namespace targets {30 31class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {32 static const Builtin::Info BuiltinInfo[];33 34protected:35 std::string CPU;36 37public:38 XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &)39 : TargetInfo(Triple) {40 // no big-endianess support yet41 BigEndian = false;42 NoAsmVariants = true;43 LongLongAlign = 64;44 SuitableAlign = 32;45 DoubleAlign = LongDoubleAlign = 64;46 SizeType = UnsignedInt;47 PtrDiffType = SignedInt;48 IntPtrType = SignedInt;49 WCharType = SignedInt;50 WIntType = UnsignedInt;51 UseZeroLengthBitfieldAlignment = true;52 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;53 resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32");54 }55 56 void getTargetDefines(const LangOptions &Opts,57 MacroBuilder &Builder) const override;58 59 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override {60 return {};61 }62 63 BuiltinVaListKind getBuiltinVaListKind() const override {64 return TargetInfo::XtensaABIBuiltinVaList;65 }66 67 std::string_view getClobbers() const override { return ""; }68 69 ArrayRef<const char *> getGCCRegNames() const override {70 static const char *const GCCRegNames[] = {71 // General register name72 "a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10",73 "a11", "a12", "a13", "a14", "a15",74 // Special register name75 "sar"};76 return llvm::ArrayRef(GCCRegNames);77 }78 79 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {80 return {};81 }82 83 bool validateAsmConstraint(const char *&Name,84 TargetInfo::ConstraintInfo &Info) const override {85 switch (*Name) {86 default:87 return false;88 case 'a':89 Info.setAllowsRegister();90 return true;91 }92 return false;93 }94 95 int getEHDataRegisterNumber(unsigned RegNo) const override {96 return (RegNo < 2) ? RegNo : -1;97 }98 99 bool isValidCPUName(StringRef Name) const override {100 return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false);101 }102 103 bool setCPU(const std::string &Name) override {104 CPU = Name;105 return isValidCPUName(Name);106 }107};108 109} // namespace targets110} // namespace clang111#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H112