1061 lines · cpp
1//===- PPC.cpp ------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8 9#include "ABIInfoImpl.h"10#include "TargetInfo.h"11#include "clang/Basic/DiagnosticFrontend.h"12 13using namespace clang;14using namespace clang::CodeGen;15 16static RValue complexTempStructure(CodeGenFunction &CGF, Address VAListAddr,17 QualType Ty, CharUnits SlotSize,18 CharUnits EltSize, const ComplexType *CTy) {19 Address Addr =20 emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, SlotSize * 2,21 SlotSize, SlotSize, /*AllowHigher*/ true);22 23 Address RealAddr = Addr;24 Address ImagAddr = RealAddr;25 if (CGF.CGM.getDataLayout().isBigEndian()) {26 RealAddr =27 CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize - EltSize);28 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,29 2 * SlotSize - EltSize);30 } else {31 ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);32 }33 34 llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());35 RealAddr = RealAddr.withElementType(EltTy);36 ImagAddr = ImagAddr.withElementType(EltTy);37 llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");38 llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");39 40 return RValue::getComplex(Real, Imag);41}42 43static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,44 llvm::Value *Address, bool Is64Bit,45 bool IsAIX) {46 // This is calculated from the LLVM and GCC tables and verified47 // against gcc output. AFAIK all PPC ABIs use the same encoding.48 49 CodeGen::CGBuilderTy &Builder = CGF.Builder;50 51 llvm::IntegerType *i8 = CGF.Int8Ty;52 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);53 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);54 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);55 56 // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers57 AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 0, 31);58 59 // 32-63: fp0-31, the 8-byte floating-point registers60 AssignToArrayRange(Builder, Address, Eight8, 32, 63);61 62 // 64-67 are various 4-byte or 8-byte special-purpose registers:63 // 64: mq64 // 65: lr65 // 66: ctr66 // 67: ap67 AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 64, 67);68 69 // 68-76 are various 4-byte special-purpose registers:70 // 68-75 cr0-771 // 76: xer72 AssignToArrayRange(Builder, Address, Four8, 68, 76);73 74 // 77-108: v0-31, the 16-byte vector registers75 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);76 77 // 109: vrsave78 // 110: vscr79 AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 109, 110);80 81 // AIX does not utilize the rest of the registers.82 if (IsAIX)83 return false;84 85 // 111: spe_acc86 // 112: spefscr87 // 113: sfp88 AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 111, 113);89 90 if (!Is64Bit)91 return false;92 93 // TODO: Need to verify if these registers are used on 64 bit AIX with Power894 // or above CPU.95 // 64-bit only registers:96 // 114: tfhar97 // 115: tfiar98 // 116: texasr99 AssignToArrayRange(Builder, Address, Eight8, 114, 116);100 101 return false;102}103 104// AIX105namespace {106/// AIXABIInfo - The AIX XCOFF ABI information.107class AIXABIInfo : public ABIInfo {108 const bool Is64Bit;109 const unsigned PtrByteSize;110 CharUnits getParamTypeAlignment(QualType Ty) const;111 112public:113 AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)114 : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}115 116 bool isPromotableTypeForABI(QualType Ty) const;117 118 ABIArgInfo classifyReturnType(QualType RetTy) const;119 ABIArgInfo classifyArgumentType(QualType Ty) const;120 121 void computeInfo(CGFunctionInfo &FI) const override {122 if (!getCXXABI().classifyReturnType(FI))123 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());124 125 for (auto &I : FI.arguments())126 I.info = classifyArgumentType(I.type);127 }128 129 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,130 AggValueSlot Slot) const override;131};132 133class AIXTargetCodeGenInfo : public TargetCodeGenInfo {134 const bool Is64Bit;135 136public:137 AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)138 : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(CGT, Is64Bit)),139 Is64Bit(Is64Bit) {}140 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {141 return 1; // r1 is the dedicated stack pointer142 }143 144 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,145 llvm::Value *Address) const override;146 147 void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,148 CodeGen::CodeGenModule &M) const override;149};150} // namespace151 152// Return true if the ABI requires Ty to be passed sign- or zero-153// extended to 32/64 bits.154bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {155 // Treat an enum type as its underlying type.156 if (const auto *ED = Ty->getAsEnumDecl())157 Ty = ED->getIntegerType();158 159 // Promotable integer types are required to be promoted by the ABI.160 if (getContext().isPromotableIntegerType(Ty))161 return true;162 163 if (!Is64Bit)164 return false;165 166 // For 64 bit mode, in addition to the usual promotable integer types, we also167 // need to extend all 32-bit types, since the ABI requires promotion to 64168 // bits.169 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())170 switch (BT->getKind()) {171 case BuiltinType::Int:172 case BuiltinType::UInt:173 return true;174 default:175 break;176 }177 178 return false;179}180 181ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {182 if (RetTy->isAnyComplexType())183 return ABIArgInfo::getDirect();184 185 if (RetTy->isVectorType())186 return ABIArgInfo::getDirect();187 188 if (RetTy->isVoidType())189 return ABIArgInfo::getIgnore();190 191 if (isAggregateTypeForABI(RetTy))192 return getNaturalAlignIndirect(RetTy, getDataLayout().getAllocaAddrSpace());193 194 return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)195 : ABIArgInfo::getDirect());196}197 198ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {199 Ty = useFirstFieldIfTransparentUnion(Ty);200 201 if (Ty->isAnyComplexType())202 return ABIArgInfo::getDirect();203 204 if (Ty->isVectorType())205 return ABIArgInfo::getDirect();206 207 if (isAggregateTypeForABI(Ty)) {208 // Records with non-trivial destructors/copy-constructors should not be209 // passed by value.210 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))211 return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),212 RAA == CGCXXABI::RAA_DirectInMemory);213 214 CharUnits CCAlign = getParamTypeAlignment(Ty);215 CharUnits TyAlign = getContext().getTypeAlignInChars(Ty);216 217 return ABIArgInfo::getIndirect(218 CCAlign, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),219 /*ByVal=*/true,220 /*Realign=*/TyAlign > CCAlign);221 }222 223 return (isPromotableTypeForABI(Ty)224 ? ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty))225 : ABIArgInfo::getDirect());226}227 228CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {229 // Complex types are passed just like their elements.230 if (const ComplexType *CTy = Ty->getAs<ComplexType>())231 Ty = CTy->getElementType();232 233 if (Ty->isVectorType())234 return CharUnits::fromQuantity(16);235 236 // If the structure contains a vector type, the alignment is 16.237 if (isRecordWithSIMDVectorType(getContext(), Ty))238 return CharUnits::fromQuantity(16);239 240 return CharUnits::fromQuantity(PtrByteSize);241}242 243RValue AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,244 QualType Ty, AggValueSlot Slot) const {245 246 auto TypeInfo = getContext().getTypeInfoInChars(Ty);247 TypeInfo.Align = getParamTypeAlignment(Ty);248 249 CharUnits SlotSize = CharUnits::fromQuantity(PtrByteSize);250 251 // If we have a complex type and the base type is smaller than the register252 // size, the ABI calls for the real and imaginary parts to be right-adjusted253 // in separate words in 32bit mode or doublewords in 64bit mode. However,254 // Clang expects us to produce a pointer to a structure with the two parts255 // packed tightly. So generate loads of the real and imaginary parts relative256 // to the va_list pointer, and store them to a temporary structure. We do the257 // same as the PPC64ABI here.258 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {259 CharUnits EltSize = TypeInfo.Width / 2;260 if (EltSize < SlotSize)261 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);262 }263 264 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,265 SlotSize, /*AllowHigher*/ true, Slot);266}267 268bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(269 CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {270 return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);271}272 273void AIXTargetCodeGenInfo::setTargetAttributes(274 const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {275 if (!isa<llvm::GlobalVariable>(GV))276 return;277 278 auto *GVar = cast<llvm::GlobalVariable>(GV);279 auto GVId = GV->getName();280 281 // Is this a global variable specified by the user as toc-data?282 bool UserSpecifiedTOC =283 llvm::binary_search(M.getCodeGenOpts().TocDataVarsUserSpecified, GVId);284 // Assumes the same variable cannot be in both TocVarsUserSpecified and285 // NoTocVars.286 if (UserSpecifiedTOC ||287 ((M.getCodeGenOpts().AllTocData) &&288 !llvm::binary_search(M.getCodeGenOpts().NoTocDataVars, GVId))) {289 const unsigned long PointerSize =290 GV->getParent()->getDataLayout().getPointerSizeInBits() / 8;291 auto *VarD = dyn_cast<VarDecl>(D);292 assert(VarD && "Invalid declaration of global variable.");293 294 ASTContext &Context = D->getASTContext();295 unsigned Alignment = Context.toBits(Context.getDeclAlign(D)) / 8;296 const auto *Ty = VarD->getType().getTypePtr();297 const RecordDecl *RDecl = Ty->getAsRecordDecl();298 299 bool EmitDiagnostic = UserSpecifiedTOC && GV->hasExternalLinkage();300 auto reportUnsupportedWarning = [&](bool ShouldEmitWarning, StringRef Msg) {301 if (ShouldEmitWarning)302 M.getDiags().Report(D->getLocation(), diag::warn_toc_unsupported_type)303 << GVId << Msg;304 };305 if (!Ty || Ty->isIncompleteType())306 reportUnsupportedWarning(EmitDiagnostic, "of incomplete type");307 else if (RDecl && RDecl->hasFlexibleArrayMember())308 reportUnsupportedWarning(EmitDiagnostic,309 "it contains a flexible array member");310 else if (VarD->getTLSKind() != VarDecl::TLS_None)311 reportUnsupportedWarning(EmitDiagnostic, "of thread local storage");312 else if (PointerSize < Context.getTypeInfo(VarD->getType()).Width / 8)313 reportUnsupportedWarning(EmitDiagnostic,314 "variable is larger than a pointer");315 else if (PointerSize < Alignment)316 reportUnsupportedWarning(EmitDiagnostic,317 "variable is aligned wider than a pointer");318 else if (D->hasAttr<SectionAttr>())319 reportUnsupportedWarning(EmitDiagnostic,320 "variable has a section attribute");321 else if (GV->hasExternalLinkage() ||322 (M.getCodeGenOpts().AllTocData && !GV->hasLocalLinkage()))323 GVar->addAttribute("toc-data");324 }325}326 327// PowerPC-32328namespace {329/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.330class PPC32_SVR4_ABIInfo : public DefaultABIInfo {331 bool IsSoftFloatABI;332 bool IsRetSmallStructInRegABI;333 334 CharUnits getParamTypeAlignment(QualType Ty) const;335 336public:337 PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,338 bool RetSmallStructInRegABI)339 : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),340 IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}341 342 ABIArgInfo classifyReturnType(QualType RetTy) const;343 344 void computeInfo(CGFunctionInfo &FI) const override {345 if (!getCXXABI().classifyReturnType(FI))346 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());347 for (auto &I : FI.arguments())348 I.info = classifyArgumentType(I.type);349 }350 351 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,352 AggValueSlot Slot) const override;353};354 355class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {356public:357 PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,358 bool RetSmallStructInRegABI)359 : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(360 CGT, SoftFloatABI, RetSmallStructInRegABI)) {}361 362 static bool isStructReturnInRegABI(const llvm::Triple &Triple,363 const CodeGenOptions &Opts);364 365 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {366 // This is recovered from gcc output.367 return 1; // r1 is the dedicated stack pointer368 }369 370 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,371 llvm::Value *Address) const override;372};373}374 375CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {376 // Complex types are passed just like their elements.377 if (const ComplexType *CTy = Ty->getAs<ComplexType>())378 Ty = CTy->getElementType();379 380 if (Ty->isVectorType())381 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16382 : 4);383 384 // For single-element float/vector structs, we consider the whole type385 // to have the same alignment requirements as its single element.386 const Type *AlignTy = nullptr;387 if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {388 const BuiltinType *BT = EltType->getAs<BuiltinType>();389 if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||390 (BT && BT->isFloatingPoint()))391 AlignTy = EltType;392 }393 394 if (AlignTy)395 return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);396 return CharUnits::fromQuantity(4);397}398 399ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {400 uint64_t Size;401 402 // -msvr4-struct-return puts small aggregates in GPR3 and GPR4.403 if (isAggregateTypeForABI(RetTy) && IsRetSmallStructInRegABI &&404 (Size = getContext().getTypeSize(RetTy)) <= 64) {405 // System V ABI (1995), page 3-22, specified:406 // > A structure or union whose size is less than or equal to 8 bytes407 // > shall be returned in r3 and r4, as if it were first stored in the408 // > 8-byte aligned memory area and then the low addressed word were409 // > loaded into r3 and the high-addressed word into r4. Bits beyond410 // > the last member of the structure or union are not defined.411 //412 // GCC for big-endian PPC32 inserts the pad before the first member,413 // not "beyond the last member" of the struct. To stay compatible414 // with GCC, we coerce the struct to an integer of the same size.415 // LLVM will extend it and return i32 in r3, or i64 in r3:r4.416 if (Size == 0)417 return ABIArgInfo::getIgnore();418 else {419 llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size);420 return ABIArgInfo::getDirect(CoerceTy);421 }422 }423 424 return DefaultABIInfo::classifyReturnType(RetTy);425}426 427// TODO: this implementation is now likely redundant with428// DefaultABIInfo::EmitVAArg.429RValue PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,430 QualType Ty, AggValueSlot Slot) const {431 if (getTarget().getTriple().isOSDarwin()) {432 auto TI = getContext().getTypeInfoInChars(Ty);433 TI.Align = getParamTypeAlignment(Ty);434 435 CharUnits SlotSize = CharUnits::fromQuantity(4);436 return emitVoidPtrVAArg(CGF, VAList, Ty,437 classifyArgumentType(Ty).isIndirect(), TI, SlotSize,438 /*AllowHigherAlign=*/true, Slot);439 }440 441 const unsigned OverflowLimit = 8;442 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {443 // TODO: Implement this. For now ignore.444 (void)CTy;445 return RValue::getAggregate(Address::invalid()); // FIXME?446 }447 448 // struct __va_list_tag {449 // unsigned char gpr;450 // unsigned char fpr;451 // unsigned short reserved;452 // void *overflow_arg_area;453 // void *reg_save_area;454 // };455 456 bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;457 bool isInt = !Ty->isFloatingType();458 bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;459 460 // All aggregates are passed indirectly? That doesn't seem consistent461 // with the argument-lowering code.462 bool isIndirect = isAggregateTypeForABI(Ty);463 464 CGBuilderTy &Builder = CGF.Builder;465 466 // The calling convention either uses 1-2 GPRs or 1 FPR.467 Address NumRegsAddr = Address::invalid();468 if (isInt || IsSoftFloatABI) {469 NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");470 } else {471 NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");472 }473 474 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");475 476 // "Align" the register count when TY is i64.477 if (isI64 || (isF64 && IsSoftFloatABI)) {478 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));479 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));480 }481 482 llvm::Value *CC =483 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");484 485 llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");486 llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");487 llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");488 489 Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);490 491 llvm::Type *DirectTy = CGF.ConvertType(Ty), *ElementTy = DirectTy;492 if (isIndirect)493 DirectTy = CGF.DefaultPtrTy;494 495 // Case 1: consume registers.496 Address RegAddr = Address::invalid();497 {498 CGF.EmitBlock(UsingRegs);499 500 Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);501 RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr), CGF.Int8Ty,502 CharUnits::fromQuantity(8));503 assert(RegAddr.getElementType() == CGF.Int8Ty);504 505 // Floating-point registers start after the general-purpose registers.506 if (!(isInt || IsSoftFloatABI)) {507 RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,508 CharUnits::fromQuantity(32));509 }510 511 // Get the address of the saved value by scaling the number of512 // registers we've used by the number of513 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);514 llvm::Value *RegOffset =515 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));516 RegAddr = Address(Builder.CreateInBoundsGEP(517 CGF.Int8Ty, RegAddr.emitRawPointer(CGF), RegOffset),518 DirectTy,519 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));520 521 // Increase the used-register count.522 NumRegs =523 Builder.CreateAdd(NumRegs,524 Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));525 Builder.CreateStore(NumRegs, NumRegsAddr);526 527 CGF.EmitBranch(Cont);528 }529 530 // Case 2: consume space in the overflow area.531 Address MemAddr = Address::invalid();532 {533 CGF.EmitBlock(UsingOverflow);534 535 Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);536 537 // Everything in the overflow area is rounded up to a size of at least 4.538 CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);539 540 CharUnits Size;541 if (!isIndirect) {542 auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);543 Size = TypeInfo.Width.alignTo(OverflowAreaAlign);544 } else {545 Size = CGF.getPointerSize();546 }547 548 Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);549 Address OverflowArea =550 Address(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"), CGF.Int8Ty,551 OverflowAreaAlign);552 // Round up address of argument to alignment553 CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);554 if (Align > OverflowAreaAlign) {555 llvm::Value *Ptr = OverflowArea.emitRawPointer(CGF);556 OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),557 OverflowArea.getElementType(), Align);558 }559 560 MemAddr = OverflowArea.withElementType(DirectTy);561 562 // Increase the overflow area.563 OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);564 Builder.CreateStore(OverflowArea.emitRawPointer(CGF), OverflowAreaAddr);565 CGF.EmitBranch(Cont);566 }567 568 CGF.EmitBlock(Cont);569 570 // Merge the cases with a phi.571 Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,572 "vaarg.addr");573 574 // Load the pointer if the argument was passed indirectly.575 if (isIndirect) {576 Result = Address(Builder.CreateLoad(Result, "aggr"), ElementTy,577 getContext().getTypeAlignInChars(Ty));578 }579 580 return CGF.EmitLoadOfAnyValue(CGF.MakeAddrLValue(Result, Ty), Slot);581}582 583bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(584 const llvm::Triple &Triple, const CodeGenOptions &Opts) {585 assert(Triple.isPPC32());586 587 switch (Opts.getStructReturnConvention()) {588 case CodeGenOptions::SRCK_Default:589 break;590 case CodeGenOptions::SRCK_OnStack: // -maix-struct-return591 return false;592 case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return593 return true;594 }595 596 if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())597 return true;598 599 return false;600}601 602bool603PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,604 llvm::Value *Address) const {605 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,606 /*IsAIX*/ false);607}608 609// PowerPC-64610 611namespace {612 613/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.614class PPC64_SVR4_ABIInfo : public ABIInfo {615 static const unsigned GPRBits = 64;616 PPC64_SVR4_ABIKind Kind;617 bool IsSoftFloatABI;618 619public:620 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,621 bool SoftFloatABI)622 : ABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}623 624 bool isPromotableTypeForABI(QualType Ty) const;625 CharUnits getParamTypeAlignment(QualType Ty) const;626 627 ABIArgInfo classifyReturnType(QualType RetTy) const;628 ABIArgInfo classifyArgumentType(QualType Ty) const;629 630 bool isHomogeneousAggregateBaseType(QualType Ty) const override;631 bool isHomogeneousAggregateSmallEnough(const Type *Ty,632 uint64_t Members) const override;633 634 // TODO: We can add more logic to computeInfo to improve performance.635 // Example: For aggregate arguments that fit in a register, we could636 // use getDirectInReg (as is done below for structs containing a single637 // floating-point value) to avoid pushing them to memory on function638 // entry. This would require changing the logic in PPCISelLowering639 // when lowering the parameters in the caller and args in the callee.640 void computeInfo(CGFunctionInfo &FI) const override {641 if (!getCXXABI().classifyReturnType(FI))642 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());643 for (auto &I : FI.arguments()) {644 // We rely on the default argument classification for the most part.645 // One exception: An aggregate containing a single floating-point646 // or vector item must be passed in a register if one is available.647 const Type *T = isSingleElementStruct(I.type, getContext());648 if (T) {649 const BuiltinType *BT = T->getAs<BuiltinType>();650 if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||651 (BT && BT->isFloatingPoint())) {652 QualType QT(T, 0);653 I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));654 continue;655 }656 }657 I.info = classifyArgumentType(I.type);658 }659 }660 661 RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,662 AggValueSlot Slot) const override;663};664 665class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {666 667public:668 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT, PPC64_SVR4_ABIKind Kind,669 bool SoftFloatABI)670 : TargetCodeGenInfo(671 std::make_unique<PPC64_SVR4_ABIInfo>(CGT, Kind, SoftFloatABI)) {672 SwiftInfo =673 std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);674 }675 676 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {677 // This is recovered from gcc output.678 return 1; // r1 is the dedicated stack pointer679 }680 681 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,682 llvm::Value *Address) const override;683 void emitTargetMetadata(CodeGen::CodeGenModule &CGM,684 const llvm::MapVector<GlobalDecl, StringRef>685 &MangledDeclNames) const override;686};687 688class PPC64TargetCodeGenInfo : public TargetCodeGenInfo {689public:690 PPC64TargetCodeGenInfo(CodeGenTypes &CGT)691 : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {}692 693 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {694 // This is recovered from gcc output.695 return 1; // r1 is the dedicated stack pointer696 }697 698 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,699 llvm::Value *Address) const override;700};701}702 703// Return true if the ABI requires Ty to be passed sign- or zero-704// extended to 64 bits.705bool706PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {707 // Treat an enum type as its underlying type.708 if (const auto *ED = Ty->getAsEnumDecl())709 Ty = ED->getIntegerType();710 711 // Promotable integer types are required to be promoted by the ABI.712 if (isPromotableIntegerTypeForABI(Ty))713 return true;714 715 // In addition to the usual promotable integer types, we also need to716 // extend all 32-bit types, since the ABI requires promotion to 64 bits.717 if (const BuiltinType *BT = Ty->getAs<BuiltinType>())718 switch (BT->getKind()) {719 case BuiltinType::Int:720 case BuiltinType::UInt:721 return true;722 default:723 break;724 }725 726 if (const auto *EIT = Ty->getAs<BitIntType>())727 if (EIT->getNumBits() < 64)728 return true;729 730 return false;731}732 733/// isAlignedParamType - Determine whether a type requires 16-byte or734/// higher alignment in the parameter area. Always returns at least 8.735CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {736 // Complex types are passed just like their elements.737 if (const ComplexType *CTy = Ty->getAs<ComplexType>())738 Ty = CTy->getElementType();739 740 auto FloatUsesVector = [this](QualType Ty){741 return Ty->isRealFloatingType() && &getContext().getFloatTypeSemantics(742 Ty) == &llvm::APFloat::IEEEquad();743 };744 745 // Only vector types of size 16 bytes need alignment (larger types are746 // passed via reference, smaller types are not aligned).747 if (Ty->isVectorType()) {748 return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);749 } else if (FloatUsesVector(Ty)) {750 // According to ABI document section 'Optional Save Areas': If extended751 // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION752 // format are supported, map them to a single quadword, quadword aligned.753 return CharUnits::fromQuantity(16);754 }755 756 // For single-element float/vector structs, we consider the whole type757 // to have the same alignment requirements as its single element.758 const Type *AlignAsType = nullptr;759 const Type *EltType = isSingleElementStruct(Ty, getContext());760 if (EltType) {761 const BuiltinType *BT = EltType->getAs<BuiltinType>();762 if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||763 (BT && BT->isFloatingPoint()))764 AlignAsType = EltType;765 }766 767 // Likewise for ELFv2 homogeneous aggregates.768 const Type *Base = nullptr;769 uint64_t Members = 0;770 if (!AlignAsType && Kind == PPC64_SVR4_ABIKind::ELFv2 &&771 isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))772 AlignAsType = Base;773 774 // With special case aggregates, only vector base types need alignment.775 if (AlignAsType) {776 bool UsesVector = AlignAsType->isVectorType() ||777 FloatUsesVector(QualType(AlignAsType, 0));778 return CharUnits::fromQuantity(UsesVector ? 16 : 8);779 }780 781 // Otherwise, we only need alignment for any aggregate type that782 // has an alignment requirement of >= 16 bytes.783 if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {784 return CharUnits::fromQuantity(16);785 }786 787 return CharUnits::fromQuantity(8);788}789 790bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {791 // Homogeneous aggregates for ELFv2 must have base types of float,792 // double, long double, or 128-bit vectors.793 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {794 if (BT->getKind() == BuiltinType::Float ||795 BT->getKind() == BuiltinType::Double ||796 BT->getKind() == BuiltinType::LongDouble ||797 BT->getKind() == BuiltinType::Ibm128 ||798 (getContext().getTargetInfo().hasFloat128Type() &&799 (BT->getKind() == BuiltinType::Float128))) {800 if (IsSoftFloatABI)801 return false;802 return true;803 }804 }805 if (const VectorType *VT = Ty->getAs<VectorType>()) {806 if (getContext().getTypeSize(VT) == 128)807 return true;808 }809 return false;810}811 812bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(813 const Type *Base, uint64_t Members) const {814 // Vector and fp128 types require one register, other floating point types815 // require one or two registers depending on their size.816 uint32_t NumRegs =817 ((getContext().getTargetInfo().hasFloat128Type() &&818 Base->isFloat128Type()) ||819 Base->isVectorType()) ? 1820 : (getContext().getTypeSize(Base) + 63) / 64;821 822 // Homogeneous Aggregates may occupy at most 8 registers.823 return Members * NumRegs <= 8;824}825 826ABIArgInfo827PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {828 Ty = useFirstFieldIfTransparentUnion(Ty);829 830 if (Ty->isAnyComplexType())831 return ABIArgInfo::getDirect();832 833 // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)834 // or via reference (larger than 16 bytes).835 if (Ty->isVectorType()) {836 uint64_t Size = getContext().getTypeSize(Ty);837 if (Size > 128)838 return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),839 /*ByVal=*/false);840 else if (Size < 128) {841 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);842 return ABIArgInfo::getDirect(CoerceTy);843 }844 }845 846 if (const auto *EIT = Ty->getAs<BitIntType>())847 if (EIT->getNumBits() > 128)848 return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),849 /*ByVal=*/true);850 851 if (isAggregateTypeForABI(Ty)) {852 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))853 return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),854 RAA == CGCXXABI::RAA_DirectInMemory);855 856 uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();857 uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();858 859 // ELFv2 homogeneous aggregates are passed as array types.860 const Type *Base = nullptr;861 uint64_t Members = 0;862 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&863 isHomogeneousAggregate(Ty, Base, Members)) {864 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));865 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);866 return ABIArgInfo::getDirect(CoerceTy);867 }868 869 // If an aggregate may end up fully in registers, we do not870 // use the ByVal method, but pass the aggregate as array.871 // This is usually beneficial since we avoid forcing the872 // back-end to store the argument to memory.873 uint64_t Bits = getContext().getTypeSize(Ty);874 if (Bits > 0 && Bits <= 8 * GPRBits) {875 llvm::Type *CoerceTy;876 877 // Types up to 8 bytes are passed as integer type (which will be878 // properly aligned in the argument save area doubleword).879 if (Bits <= GPRBits)880 CoerceTy =881 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));882 // Larger types are passed as arrays, with the base type selected883 // according to the required alignment in the save area.884 else {885 uint64_t RegBits = ABIAlign * 8;886 uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;887 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);888 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);889 }890 891 return ABIArgInfo::getDirect(CoerceTy);892 }893 894 // All other aggregates are passed ByVal.895 return ABIArgInfo::getIndirect(896 CharUnits::fromQuantity(ABIAlign),897 /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),898 /*ByVal=*/true, /*Realign=*/TyAlign > ABIAlign);899 }900 901 return (isPromotableTypeForABI(Ty)902 ? ABIArgInfo::getExtend(Ty, CGT.ConvertType(Ty))903 : ABIArgInfo::getDirect());904}905 906ABIArgInfo907PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {908 if (RetTy->isVoidType())909 return ABIArgInfo::getIgnore();910 911 if (RetTy->isAnyComplexType())912 return ABIArgInfo::getDirect();913 914 // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)915 // or via reference (larger than 16 bytes).916 if (RetTy->isVectorType()) {917 uint64_t Size = getContext().getTypeSize(RetTy);918 if (Size > 128)919 return getNaturalAlignIndirect(RetTy,920 getDataLayout().getAllocaAddrSpace());921 else if (Size < 128) {922 llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);923 return ABIArgInfo::getDirect(CoerceTy);924 }925 }926 927 if (const auto *EIT = RetTy->getAs<BitIntType>())928 if (EIT->getNumBits() > 128)929 return getNaturalAlignIndirect(930 RetTy, getDataLayout().getAllocaAddrSpace(), /*ByVal=*/false);931 932 if (isAggregateTypeForABI(RetTy)) {933 // ELFv2 homogeneous aggregates are returned as array types.934 const Type *Base = nullptr;935 uint64_t Members = 0;936 if (Kind == PPC64_SVR4_ABIKind::ELFv2 &&937 isHomogeneousAggregate(RetTy, Base, Members)) {938 llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));939 llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);940 return ABIArgInfo::getDirect(CoerceTy);941 }942 943 // ELFv2 small aggregates are returned in up to two registers.944 uint64_t Bits = getContext().getTypeSize(RetTy);945 if (Kind == PPC64_SVR4_ABIKind::ELFv2 && Bits <= 2 * GPRBits) {946 if (Bits == 0)947 return ABIArgInfo::getIgnore();948 949 llvm::Type *CoerceTy;950 if (Bits > GPRBits) {951 CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);952 CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);953 } else954 CoerceTy =955 llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));956 return ABIArgInfo::getDirect(CoerceTy);957 }958 959 // All other aggregates are returned indirectly.960 return getNaturalAlignIndirect(RetTy, getDataLayout().getAllocaAddrSpace());961 }962 963 return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)964 : ABIArgInfo::getDirect());965}966 967// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.968RValue PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,969 QualType Ty, AggValueSlot Slot) const {970 auto TypeInfo = getContext().getTypeInfoInChars(Ty);971 TypeInfo.Align = getParamTypeAlignment(Ty);972 973 CharUnits SlotSize = CharUnits::fromQuantity(8);974 975 // If we have a complex type and the base type is smaller than 8 bytes,976 // the ABI calls for the real and imaginary parts to be right-adjusted977 // in separate doublewords. However, Clang expects us to produce a978 // pointer to a structure with the two parts packed tightly. So generate979 // loads of the real and imaginary parts relative to the va_list pointer,980 // and store them to a temporary structure.981 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {982 CharUnits EltSize = TypeInfo.Width / 2;983 if (EltSize < SlotSize)984 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy);985 }986 987 // Otherwise, just use the general rule.988 //989 // The PPC64 ABI passes some arguments in integer registers, even to variadic990 // functions. To allow va_list to use the simple "void*" representation,991 // variadic calls allocate space in the argument area for the integer argument992 // registers, and variadic functions spill their integer argument registers to993 // this area in their prologues. When aggregates smaller than a register are994 // passed this way, they are passed in the least significant bits of the995 // register, which means that after spilling on big-endian targets they will996 // be right-aligned in their argument slot. This is uncommon; for a variety of997 // reasons, other big-endian targets don't end up right-aligning aggregate998 // types this way, and so right-alignment only applies to fundamental types.999 // So on PPC64, we must force the use of right-alignment even for aggregates.1000 return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,1001 SlotSize, /*AllowHigher*/ true, Slot,1002 /*ForceRightAdjust*/ true);1003}1004 1005bool1006PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(1007 CodeGen::CodeGenFunction &CGF,1008 llvm::Value *Address) const {1009 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,1010 /*IsAIX*/ false);1011}1012 1013void PPC64_SVR4_TargetCodeGenInfo::emitTargetMetadata(1014 CodeGen::CodeGenModule &CGM,1015 const llvm::MapVector<GlobalDecl, StringRef> &MangledDeclNames) const {1016 if (CGM.getTypes().isLongDoubleReferenced()) {1017 llvm::LLVMContext &Ctx = CGM.getLLVMContext();1018 const auto *flt = &CGM.getTarget().getLongDoubleFormat();1019 if (flt == &llvm::APFloat::PPCDoubleDouble())1020 CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",1021 llvm::MDString::get(Ctx, "doubledouble"));1022 else if (flt == &llvm::APFloat::IEEEquad())1023 CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",1024 llvm::MDString::get(Ctx, "ieeequad"));1025 else if (flt == &llvm::APFloat::IEEEdouble())1026 CGM.getModule().addModuleFlag(llvm::Module::Error, "float-abi",1027 llvm::MDString::get(Ctx, "ieeedouble"));1028 }1029}1030 1031bool1032PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,1033 llvm::Value *Address) const {1034 return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,1035 /*IsAIX*/ false);1036}1037 1038std::unique_ptr<TargetCodeGenInfo>1039CodeGen::createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit) {1040 return std::make_unique<AIXTargetCodeGenInfo>(CGM.getTypes(), Is64Bit);1041}1042 1043std::unique_ptr<TargetCodeGenInfo>1044CodeGen::createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI) {1045 bool RetSmallStructInRegABI = PPC32TargetCodeGenInfo::isStructReturnInRegABI(1046 CGM.getTriple(), CGM.getCodeGenOpts());1047 return std::make_unique<PPC32TargetCodeGenInfo>(CGM.getTypes(), SoftFloatABI,1048 RetSmallStructInRegABI);1049}1050 1051std::unique_ptr<TargetCodeGenInfo>1052CodeGen::createPPC64TargetCodeGenInfo(CodeGenModule &CGM) {1053 return std::make_unique<PPC64TargetCodeGenInfo>(CGM.getTypes());1054}1055 1056std::unique_ptr<TargetCodeGenInfo> CodeGen::createPPC64_SVR4_TargetCodeGenInfo(1057 CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind, bool SoftFloatABI) {1058 return std::make_unique<PPC64_SVR4_TargetCodeGenInfo>(CGM.getTypes(), Kind,1059 SoftFloatABI);1060}1061