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1/*===--------------- avx10_2convertintrin.h - AVX10_2CONVERT ---------------===2 *3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4 * See https://llvm.org/LICENSE.txt for license information.5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6 *7 *===-----------------------------------------------------------------------===8 */9#ifndef __IMMINTRIN_H10#error \11 "Never use <avx10_2convertintrin.h> directly; include <immintrin.h> instead."12#endif // __IMMINTRIN_H13 14#ifdef __SSE2__15 16#ifndef __AVX10_2CONVERTINTRIN_H17#define __AVX10_2CONVERTINTRIN_H18 19/* Define the default attributes for the functions in this file. */20#define __DEFAULT_FN_ATTRS128 \21 __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \22 __min_vector_width__(128)))23#define __DEFAULT_FN_ATTRS256 \24 __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \25 __min_vector_width__(256)))26 27// clang-format off28 29/// Convert two 128-bit vectors, \a __A and \a __B, containing packed30/// single-precision (32-bit) floating-point elements to a 128-bit vector31/// containing FP16 elements.32///33/// \code{.operation}34/// FOR i := 0 to 735/// IF i < 436/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])37/// ELSE38/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])39/// FI40///41/// ENDFOR42///43/// dst[MAX:128] := 044/// \endcode45///46/// \headerfile <immintrin.h>47///48/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.49///50/// \param __A51/// A 128-bit vector of [4 x float].52/// \param __B53/// A 128-bit vector of [4 x float].54/// \returns55/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the56/// (converted) elements from \a __B; higher order elements correspond to the57/// (converted) elements from \a __A.58static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,59 __m128 __B) {60 return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(61 (__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)(-1));62}63 64/// Convert two 128-bit vectors, \a __A and \a __B, containing packed65/// single-precision (32-bit) floating-point elements to a 128-bit vector66/// containing FP16 elements. Merging mask \a __U is used to determine if given67/// element should be taken from \a __W instead.68///69/// \code{.operation}70/// FOR i := 0 to 771/// IF __U[i]72/// IF i < 473/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])74/// ELSE75/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])76/// FI77/// ELSE78/// dst.fp16[i] := __W.fp16[i]79/// FI80/// ENDFOR81///82/// dst[MAX:128] := 083/// \endcode84///85/// \headerfile <immintrin.h>86///87/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.88///89/// \param __W90/// A 128-bit vector of [8 x fp16].91/// \param __U92/// A 8-bit merging mask.93/// \param __A94/// A 128-bit vector of [4 x float].95/// \param __B96/// A 128-bit vector of [4 x float].97/// \returns98/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the99/// (converted) elements from \a __B; higher order elements correspond to the100/// (converted) elements from \a __A. If corresponding mask bit is not set, then101/// element from \a __W is taken instead.102static __inline__ __m128h __DEFAULT_FN_ATTRS128103_mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {104 return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(105 (__v4sf)__A, (__v4sf)__B, (__v8hf)__W, (__mmask8)__U);106}107 108/// Convert two 128-bit vectors, \a __A and \a __B, containing packed109/// single-precision (32-bit) floating-point elements to a 128-bit vector110/// containing FP16 elements. Zeroing mask \a __U is used to determine if given111/// element should be zeroed instead.112///113/// \code{.operation}114/// FOR i := 0 to 7115/// IF __U[i]116/// IF i < 4117/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])118/// ELSE119/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])120/// FI121/// ELSE122/// dst.fp16[i] := 0123/// FI124/// ENDFOR125///126/// dst[MAX:128] := 0127/// \endcode128///129/// \headerfile <immintrin.h>130///131/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.132///133/// \param __U134/// A 8-bit zeroing mask.135/// \param __A136/// A 128-bit vector of [4 x float].137/// \param __B138/// A 128-bit vector of [4 x float].139/// \returns140/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the141/// (converted) elements from \a __B; higher order elements correspond to the142/// (converted) elements from \a __A. If corresponding mask bit is not set,143/// then zero is taken instead.144static __inline__ __m128h __DEFAULT_FN_ATTRS128145_mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {146 return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(147 (__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U);148}149 150/// Convert two 256-bit vectors, \a __A and \a __B, containing packed151/// single-precision (32-bit) floating-point elements to a 256-bit vector152/// containing FP16 elements.153/// 154/// \code{.operation}155/// FOR i := 0 to 15 156/// IF i < 8157/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])158/// ELSE159/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])160/// FI161/// ENDFOR162///163/// dst[MAX:256] := 0164/// \endcode165///166/// \headerfile <immintrin.h>167///168/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.169///170/// \param __A171/// A 256-bit vector of [8 x float].172/// \param __B173/// A 256-bit vector of [8 x float].174/// \returns175/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the176/// (converted) elements from \a __B; higher order elements correspond to the177/// (converted) elements from \a __A.178static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,179 __m256 __B) {180 return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(181 (__v8sf)__A, (__v8sf)__B, (__v16hf)_mm256_setzero_ph(), (__mmask16)(-1));182}183 184/// Convert two 256-bit vectors, \a __A and \a __B, containing packed185/// single-precision (32-bit) floating-point elements to a 256-bit vector186/// containing FP16 elements. Merging mask \a __U is used to determine if given187/// element should be taken from \a __W instead.188///189/// \code{.operation}190/// FOR i := 0 to 15191/// IF __U[i]192/// IF i < 8193/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])194/// ELSE195/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])196/// FI197/// ELSE198/// dst.fp16[i] := __W.fp16[i]199/// FI200/// ENDFOR201///202/// dst[MAX:256] := 0203/// \endcode204///205/// \headerfile <immintrin.h>206///207/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.208///209/// \param __W210/// A 256-bit vector of [16 x fp16].211/// \param __U212/// A 16-bit merging mask.213/// \param __A214/// A 256-bit vector of [8 x float].215/// \param __B216/// A 256-bit vector of [8 x float].217/// \returns218/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the219/// (converted) elements from \a __B; higher order elements correspond to the220/// (converted) elements from \a __A. If corresponding mask bit is not set, then221/// element from \a __W is taken instead.222static __inline__ __m256h __DEFAULT_FN_ATTRS256223_mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {224 return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(225 (__v8sf)__A, (__v8sf)__B, (__v16hf)__W, (__mmask16)__U);226}227 228/// Convert two 256-bit vectors, \a __A and \a __B, containing packed229/// single-precision (32-bit) floating-point elements to a 256-bit vector230/// containing FP16 elements. Zeroing mask \a __U is used to determine if given231/// element should be zeroed instead.232///233/// \code{.operation}234/// FOR i := 0 to 15 235/// IF __U[i]236/// IF i < 8237/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])238/// ELSE239/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])240/// FI241/// ELSE242/// dst.fp16[i] := 0243/// FI244/// ENDFOR245///246/// dst[MAX:256] := 0247/// \endcode248///249/// \headerfile <immintrin.h>250///251/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.252///253/// \param __U254/// A 16-bit zeroing mask.255/// \param __A256/// A 256-bit vector of [8 x float].257/// \param __B258/// A 256-bit vector of [8 x float].259/// \returns260/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the261/// (converted) elements from \a __B; higher order elements correspond to the262/// (converted) elements from \a __A. If corresponding mask bit is not set,263/// then zero is taken instead.264static __inline__ __m256h __DEFAULT_FN_ATTRS256265_mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {266 return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(267 (__v8sf)__A, (__v8sf)__B, (__v16hf)_mm256_setzero_ph(), (__mmask16)__U);268}269 270/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements271/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each272/// 16-bit integer stored in \a __B.273///274/// \code{.operation}275/// FOR i := 0 to 7276/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])277/// ENDFOR278///279/// dst[MAX:64] := 0280/// \endcode281///282/// \headerfile <immintrin.h>283///284/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.285///286/// \param __A287/// A 128-bit vector of [8 x int16].288/// \param __B289/// A 128-bit vector of [8 x fp16].290/// \returns291/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the292/// converted elements from \a __B using biases from \a __A; higher order293/// elements are zeroed.294static __inline__ __m128i __DEFAULT_FN_ATTRS128295_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {296 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(297 (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);298}299 300/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements301/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each302/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if303/// given element should be taken from \a __W instead.304///305/// \code{.operation}306/// FOR i := 0 to 7307/// IF __U[i]308/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])309/// ELSE310/// dst.bf8[i] := __W.bf8[i]311/// FI312/// ENDFOR313///314/// dst[MAX:64] := 0315/// \endcode316///317/// \headerfile <immintrin.h>318///319/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.320///321/// \param __W322/// A 128-bit vector of [16 x bf8].323/// \param __U324/// A 8-bit merging mask.325/// \param __A326/// A 128-bit vector of [8 x int16].327/// \param __B328/// A 128-bit vector of [8 x fp16].329/// \returns330/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the331/// converted elements from \a __B, using biases from \a __A; higher order332/// elements are zeroed. If corresponding mask bit is not set, then element333/// from \a __W is taken instead.334static __inline__ __m128i __DEFAULT_FN_ATTRS128335_mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {336 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(337 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);338}339 340/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements341/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each342/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if343/// given element should be zeroed instead.344///345/// \code{.operation}346/// FOR i := 0 to 7347/// IF __U[i]348/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])349/// ELSE350/// dst.bf8[i] := 0351/// FI352/// ENDFOR353///354/// dst[MAX:64] := 0355/// \endcode356///357/// \headerfile <immintrin.h>358///359/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.360///361/// \param __U362/// A 8-bit zeroing mask.363/// \param __A364/// A 128-bit vector of [8 x int16].365/// \param __B366/// A 128-bit vector of [8 x fp16].367/// \returns368/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the369/// converted elements from \a __B, using biases from \a __A; higher order370/// elements are zeroed. If corresponding mask bit is not set, then element371/// is zeroed.372static __inline__ __m128i __DEFAULT_FN_ATTRS128373_mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {374 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(375 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),376 (__mmask8)__U);377}378 379/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements380/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each381/// 16-bit integer stored in \a __B.382///383/// \code{.operation}384/// FOR i := 0 to 15385/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])386/// ENDFOR387///388/// dst[MAX:128] := 0389/// \endcode390///391/// \headerfile <immintrin.h>392///393/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.394///395/// \param __A396/// A 256-bit vector of [16 x int16].397/// \param __B398/// A 256-bit vector of [16 x fp16].399/// \returns400/// A 128-bit vector of [16 x bf8]. Elements correspond to the401/// converted elements from \a __B using biases from \a __A.402static __inline__ __m128i __DEFAULT_FN_ATTRS256403_mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {404 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(405 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),406 (__mmask16)-1);407}408 409/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements410/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each411/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if412/// given element should be taken from \a __W instead.413///414/// \code{.operation}415/// FOR i := 0 to 15416/// IF __U[i]417/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])418/// ELSE419/// dst.bf8[i] := __W.bf8[i]420/// FI421/// ENDFOR422///423/// dst[MAX:128] := 0424/// \endcode425///426/// \headerfile <immintrin.h>427///428/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.429///430/// \param __W431/// A 128-bit vector of [16 x bf8].432/// \param __U433/// A 16-bit merging mask.434/// \param __A435/// A 256-bit vector of [16 x int16].436/// \param __B437/// A 256-bit vector of [16 x fp16].438/// \returns439/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted440/// elements from \a __B, using biases from \a __A. If corresponding mask bit441/// is not set, then element from \a __W is taken instead.442static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(443 __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {444 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(445 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);446}447 448/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements449/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each450/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if451/// given element should be zeroed instead.452///453/// \code{.operation}454/// FOR i := 0 to 15455/// IF __U[i]456/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])457/// ELSE458/// dst.bf8[i] := 0459/// FI460/// ENDFOR461///462/// dst[MAX:128] := 0463/// \endcode464///465/// \headerfile <immintrin.h>466///467/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.468///469/// \param __U470/// A 16-bit zeroing mask.471/// \param __A472/// A 256-bit vector of [16 x int16].473/// \param __B474/// A 256-bit vector of [16 x fp16].475/// \returns476/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted477/// elements from \a __B, using biases from \a __A. If corresponding mask bit478/// is not set, then element is zeroed.479static __inline__ __m128i __DEFAULT_FN_ATTRS256480_mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {481 return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(482 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),483 (__mmask16)__U);484}485 486/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements487/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each488/// 16-bit integer stored in \a __B. Results are saturated.489///490/// \code{.operation}491/// FOR i := 0 to 7492/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])493/// ENDFOR494///495/// dst[MAX:64] := 0496/// \endcode497///498/// \headerfile <immintrin.h>499///500/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.501///502/// \param __A503/// A 128-bit vector of [8 x int16].504/// \param __B505/// A 128-bit vector of [8 x fp16].506/// \returns507/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the508/// converted elements from \a __B using biases from \a __A; higher order509/// elements are zeroed.510static __inline__ __m128i __DEFAULT_FN_ATTRS128511_mm_cvts_biasph_bf8(__m128i __A, __m128h __B) {512 return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(513 (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);514}515 516/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements517/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each518/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U519/// is used to determine if given element should be taken from \a __W instead.520///521/// \code{.operation}522/// FOR i := 0 to 7523/// IF __U[i]524/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])525/// ELSE526/// dst.bf8[i] := __W.bf8[i]527/// FI528/// ENDFOR529///530/// dst[MAX:64] := 0531/// \endcode532///533/// \headerfile <immintrin.h>534///535/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.536///537/// \param __W538/// A 128-bit vector of [16 x bf8].539/// \param __U540/// A 8-bit merging mask.541/// \param __A542/// A 128-bit vector of [8 x int16].543/// \param __B544/// A 128-bit vector of [8 x fp16].545/// \returns546/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the547/// converted elements from \a __B, using biases from \a __A; higher order548/// elements are zeroed. If corresponding mask bit is not set, then element549/// from \a __W is taken instead.550static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvts_biasph_bf8(__m128i551 __W, __mmask8 __U, __m128i __A, __m128h __B) { return552 (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( (__v16qi)__A,553 (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); }554 555/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements556/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each557/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U558/// is used to determine if given element should be zeroed instead.559///560/// \code{.operation}561/// FOR i := 0 to 7562/// IF __U[i]563/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])564/// ELSE565/// dst.bf8[i] := 0566/// FI567/// ENDFOR568///569/// dst[MAX:64] := 0570/// \endcode571///572/// \headerfile <immintrin.h>573///574/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.575///576/// \param __U577/// A 8-bit zeroing mask.578/// \param __A579/// A 128-bit vector of [8 x int16].580/// \param __B581/// A 128-bit vector of [8 x fp16].582/// \returns583/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the584/// converted elements from \a __B, using biases from \a __A; higher order585/// elements are zeroed. If corresponding mask bit is not set, then element586/// is zeroed.587static __inline__ __m128i __DEFAULT_FN_ATTRS128588_mm_maskz_cvts_biasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {589 return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(590 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),591 (__mmask8)__U);592}593 594 595/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements596/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each597/// 16-bit integer stored in \a __B. Results are saturated.598///599/// \code{.operation}600/// FOR i := 0 to 15601/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])602/// ENDFOR603///604/// dst[MAX:128] := 0605/// \endcode606///607/// \headerfile <immintrin.h>608///609/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.610///611/// \param __A612/// A 256-bit vector of [16 x int16].613/// \param __B614/// A 256-bit vector of [16 x fp16].615/// \returns616/// A 128-bit vector of [16 x bf8]. Elements correspond to the617/// converted elements from \a __B using biases from \a __A.618static __inline__ __m128i __DEFAULT_FN_ATTRS256619_mm256_cvts_biasph_bf8(__m256i __A, __m256h __B) {620 return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(621 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),622 (__mmask16)-1);623}624 625/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements626/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each627/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U628/// is used to determine if given element should be taken from \a __W instead.629///630/// \code{.operation}631/// FOR i := 0 to 15632/// IF __U[i]633/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])634/// ELSE635/// dst.bf8[i] := __W.bf8[i]636/// FI637/// ENDFOR638///639/// dst[MAX:128] := 0640/// \endcode641///642/// \headerfile <immintrin.h>643///644/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.645///646/// \param __W647/// A 128-bit vector of [16 x bf8].648/// \param __U649/// A 16-bit merging mask.650/// \param __A651/// A 256-bit vector of [16 x int16].652/// \param __B653/// A 256-bit vector of [16 x fp16].654/// \returns655/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted656/// elements from \a __B, using biases from \a __A. If corresponding mask bit657/// is not set, then element from \a __W is taken instead.658static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasph_bf8(659 __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {660 return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(661 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);662}663 664/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements665/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each666/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U667/// is used to determine if given element should be zeroed instead.668///669/// \code{.operation}670/// FOR i := 0 to 15671/// IF __U[i]672/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])673/// ELSE674/// dst.bf8[i] := 0675/// FI676/// ENDFOR677///678/// dst[MAX:128] := 0679/// \endcode680///681/// \headerfile <immintrin.h>682///683/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.684///685/// \param __U686/// A 16-bit zeroing mask.687/// \param __A688/// A 256-bit vector of [16 x int16].689/// \param __B690/// A 256-bit vector of [16 x fp16].691/// \returns692/// A 128-bit vector of [16 x bf8]. Elements correspond to the converted693/// elements from \a __B, using biases from \a __A. If corresponding mask bit694/// is not set, then element is zeroed.695static __inline__ __m128i __DEFAULT_FN_ATTRS256696_mm256_maskz_cvts_biasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {697 return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(698 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),699 (__mmask16)__U);700}701 702/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements703/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each704/// 16-bit integer stored in \a __B.705///706/// \code{.operation}707/// FOR i := 0 to 7708/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])709/// ENDFOR710///711/// dst[MAX:64] := 0712/// \endcode713///714/// \headerfile <immintrin.h>715///716/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.717///718/// \param __A719/// A 128-bit vector of [8 x int16].720/// \param __B721/// A 128-bit vector of [8 x fp16].722/// \returns723/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the724/// converted elements from \a __B using biases from \a __A; higher order725/// elements are zeroed.726static __inline__ __m128i __DEFAULT_FN_ATTRS128727_mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {728 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(729 (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);730}731 732/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements733/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each734/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if735/// given element should be taken from \a __W instead.736///737/// \code{.operation}738/// FOR i := 0 to 7739/// IF __U[i]740/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])741/// ELSE742/// dst.hf8[i] := __W.hf8[i]743/// FI744/// ENDFOR745///746/// dst[MAX:64] := 0747/// \endcode748///749/// \headerfile <immintrin.h>750///751/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.752///753/// \param __W754/// A 128-bit vector of [16 x hf8].755/// \param __U756/// A 8-bit merging mask.757/// \param __A758/// A 128-bit vector of [8 x int16].759/// \param __B760/// A 128-bit vector of [8 x fp16].761/// \returns762/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the763/// converted elements from \a __B, using biases from \a __A; higher order764/// elements are zeroed. If corresponding mask bit is not set, then element765/// from \a __W is taken instead.766static __inline__ __m128i __DEFAULT_FN_ATTRS128767_mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {768 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(769 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);770}771 772/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements773/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each774/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if775/// given element should be zeroed instead.776///777/// \code{.operation}778/// FOR i := 0 to 7779/// IF __U[i]780/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])781/// ELSE782/// dst.hf8[i] := 0783/// FI784/// ENDFOR785///786/// dst[MAX:64] := 0787/// \endcode788///789/// \headerfile <immintrin.h>790///791/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.792///793/// \param __U794/// A 8-bit zeroing mask.795/// \param __A796/// A 128-bit vector of [8 x int16].797/// \param __B798/// A 128-bit vector of [8 x fp16].799/// \returns800/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the801/// converted elements from \a __B, using biases from \a __A; higher order802/// elements are zeroed. If corresponding mask bit is not set, then element803/// is zeroed.804static __inline__ __m128i __DEFAULT_FN_ATTRS128805_mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {806 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(807 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),808 (__mmask8)__U);809}810 811/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements812/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each813/// 16-bit integer stored in \a __B.814///815/// \code{.operation}816/// FOR i := 0 to 15817/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])818/// ENDFOR819///820/// dst[MAX:128] := 0821/// \endcode822///823/// \headerfile <immintrin.h>824///825/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.826///827/// \param __A828/// A 256-bit vector of [16 x half].829/// \param __B830/// A 256-bit vector of [16 x i16].831/// \returns832/// A 128-bit vector of [16 x hf8]. Elements correspond to the833/// converted elements from \a __B using biases from \a __A.834static __inline__ __m128i __DEFAULT_FN_ATTRS256835_mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {836 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(837 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),838 (__mmask16)-1);839}840 841/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements842/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each843/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if844/// given element should be taken from \a __W instead.845///846/// \code{.operation}847/// FOR i := 0 to 15848/// IF __U[i]849/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])850/// ELSE851/// dst.hf8[i] := __W.hf8[i]852/// FI853/// ENDFOR854///855/// dst[MAX:128] := 0856/// \endcode857///858/// \headerfile <immintrin.h>859///860/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.861///862/// \param __W863/// A 128-bit vector of [16 x hf8].864/// \param __U865/// A 16-bit merging mask.866/// \param __A867/// A 256-bit vector of [16 x int16].868/// \param __B869/// A 256-bit vector of [16 x fp16].870/// \returns871/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted872/// elements from \a __B, using biases from \a __A. If corresponding mask bit873/// is not set, then element from \a __W is taken instead.874static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(875 __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {876 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(877 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);878}879 880/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements881/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each882/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if883/// given element should be taken zeroed instead.884///885/// \code{.operation}886/// FOR i := 0 to 15887/// IF __U[i]888/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])889/// ELSE890/// dst.hf8[i] := 0891/// FI892/// ENDFOR893///894/// dst[MAX:128] := 0895/// \endcode896///897/// \headerfile <immintrin.h>898///899/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.900///901/// \param __U902/// A 16-bit zeroing mask.903/// \param __A904/// A 256-bit vector of [16 x half].905/// \param __B906/// A 256-bit vector of [16 x i16].907/// \returns908/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted909/// elements from \a __B, using biases from \a __A. If corresponding mask bit910/// is not set, then element is zeroed.911static __inline__ __m128i __DEFAULT_FN_ATTRS256912_mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {913 return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(914 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),915 (__mmask16)__U);916}917 918/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements919/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each920/// 16-bit integer stored in \a __B. Results are saturated.921///922/// \code{.operation}923/// FOR i := 0 to 7924/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])925/// ENDFOR926///927/// dst[MAX:64] := 0928/// \endcode929///930/// \headerfile <immintrin.h>931///932/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S`instruction.933///934/// \param __A935/// A 128-bit vector of [8 x int16].936/// \param __B937/// A 128-bit vector of [8 x fp16].938/// \returns939/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the940/// converted elements from \a __B using biases from \a __A; higher order941/// elements are zeroed.942static __inline__ __m128i __DEFAULT_FN_ATTRS128943_mm_cvts_biasph_hf8(__m128i __A, __m128h __B) {944 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(945 (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);946}947 948/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements949/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each950/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U951/// is used to determine if given element should be taken from \a __W instead.952///953/// \code{.operation}954/// FOR i := 0 to 7955/// IF __U[i]956/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])957/// ELSE958/// dst.hf8[i] := __W.hf8[i]959/// FI960/// ENDFOR961///962/// dst[MAX:64] := 0963/// \endcode964///965/// \headerfile <immintrin.h>966///967/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.968///969/// \param __W970/// A 128-bit vector of [16 x hf8].971/// \param __U972/// A 8-bit merging mask.973/// \param __A974/// A 128-bit vector of [8 x int16].975/// \param __B976/// A 128-bit vector of [8 x fp16].977/// \returns978/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the979/// converted elements from \a __B, using biases from \a __A; higher order980/// elements are zeroed. If corresponding mask bit is not set, then element981/// from \a __W is taken instead.982static __inline__ __m128i __DEFAULT_FN_ATTRS128983_mm_mask_cvts_biasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {984 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(985 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);986}987 988/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements989/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each990/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U991/// is used to determine if given element should be zeroed instead.992///993/// \code{.operation}994/// FOR i := 0 to 7995/// IF __U[i]996/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])997/// ELSE998/// dst.hf8[i] := 0999/// FI1000/// ENDFOR1001///1002/// dst[MAX:64] := 01003/// \endcode1004///1005/// \headerfile <immintrin.h>1006///1007/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.1008///1009/// \param __U1010/// A 8-bit zeroing mask.1011/// \param __A1012/// A 128-bit vector of [8 x int16].1013/// \param __B1014/// A 128-bit vector of [8 x fp16].1015/// \returns1016/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the1017/// converted elements from \a __B, using biases from \a __A; higher order1018/// elements are zeroed. If corresponding mask bit is not set, then element1019/// is zeroed.1020static __inline__ __m128i __DEFAULT_FN_ATTRS1281021_mm_maskz_cvts_biasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {1022 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(1023 (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),1024 (__mmask8)__U);1025}1026 1027/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements1028/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each1029/// 16-bit integer stored in \a __B. Results are saturated.1030///1031/// \code{.operation}1032/// FOR i := 0 to 151033/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])1034/// ENDFOR1035///1036/// dst[MAX:128] := 01037/// \endcode1038///1039/// \headerfile <immintrin.h>1040///1041/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.1042///1043/// \param __A1044/// A 256-bit vector of [16 x int16].1045/// \param __B1046/// A 256-bit vector of [16 x fp16].1047/// \returns1048/// A 128-bit vector of [16 x hf8]. Elements correspond to the1049/// converted elements from \a __B using biases from \a __A.1050static __inline__ __m128i __DEFAULT_FN_ATTRS2561051_mm256_cvts_biasph_hf8(__m256i __A, __m256h __B) {1052 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(1053 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),1054 (__mmask16)-1);1055}1056 1057/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements1058/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each1059/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U1060/// is used to determine if given element should be taken from \a __W instead.1061///1062/// \code{.operation}1063/// FOR i := 0 to 151064/// IF __U[i]1065/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])1066/// ELSE1067/// dst.hf8[i] := __W.hf8[i]1068/// FI1069/// ENDFOR1070///1071/// dst[MAX:128] := 01072/// \endcode1073///1074/// \headerfile <immintrin.h>1075///1076/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.1077///1078/// \param __W1079/// A 128-bit vector of [16 x hf8].1080/// \param __U1081/// A 16-bit merging mask.1082/// \param __A1083/// A 256-bit vector of [16 x int16].1084/// \param __B1085/// A 256-bit vector of [16 x fp16].1086/// \returns1087/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted1088/// elements from \a __B, using biases from \a __A. If corresponding mask bit1089/// is not set, then element from \a __W is taken instead.1090static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasph_hf8(1091 __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {1092 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(1093 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);1094}1095 1096/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements1097/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each1098/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U1099/// is used to determine if given element should be zeroed instead.1100///1101/// \code{.operation}1102/// FOR i := 0 to 151103/// IF __U[i]1104/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])1105/// ELSE1106/// dst.hf8[i] := 01107/// FI1108/// ENDFOR1109///1110/// dst[MAX:128] := 01111/// \endcode1112///1113/// \headerfile <immintrin.h>1114///1115/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.1116///1117/// \param __U1118/// A 16-bit zeroing mask.1119/// \param __A1120/// A 256-bit vector of [16 x int16].1121/// \param __B1122/// A 256-bit vector of [16 x fp16].1123/// \returns1124/// A 128-bit vector of [16 x hf8]. Elements correspond to the converted1125/// elements from \a __B, using biases from \a __A. If corresponding mask bit1126/// is not set, then element is zeroed.1127static __inline__ __m128i __DEFAULT_FN_ATTRS2561128_mm256_maskz_cvts_biasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {1129 return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(1130 (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),1131 (__mmask16)__U);1132}1133 1134/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161135/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1136///1137/// \code{.operation}1138/// FOR i := 0 to 15 1139/// IF i < 81140/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1141/// ELSE1142/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])1143/// FI1144/// ENDFOR1145///1146/// dst[MAX:128] := 01147/// \endcode1148///1149/// \headerfile <immintrin.h>1150///1151/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1152///1153/// \param __A1154/// A 128-bit vector of [8 x fp16].1155/// \param __B1156/// A 128-bit vector of [8 x fp16].1157/// \returns1158/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1159/// (converted) elements from \a __B; higher order elements correspond to the1160/// (converted) elements from \a __A.1161static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,1162 __m128h __B) {1163 return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A),1164 (__v8hf)(__B));1165}1166 1167/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161168/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1169/// Merging mask \a __U is used to determine if given element should be taken1170/// from \a __W instead.1171///1172/// \code{.operation}1173/// FOR i := 0 to 151174/// IF __U[i]1175/// IF i < 81176/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1177/// ELSE1178/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])1179/// FI1180/// ELSE1181/// dst.bf8[i] := __W.bf8[i]1182/// FI1183/// ENDFOR1184///1185/// dst[MAX:128] := 01186/// \endcode1187///1188/// \headerfile <immintrin.h>1189///1190/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1191///1192/// \param __W1193/// A 128-bit vector of [16 x bf8].1194/// \param __U1195/// A 16-bit merging mask.1196/// \param __A1197/// A 128-bit vector of [8 x fp16].1198/// \param __B1199/// A 128-bit vector of [8 x fp16].1200/// \returns1201/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1202/// (converted) elements from \a __B; higher order elements correspond to the1203/// (converted) elements from \a __A. If corresponding mask bit is not set, then1204/// element from \a __W is taken instead.1205static __inline__ __m128i __DEFAULT_FN_ATTRS1281206_mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {1207 return (__m128i)__builtin_ia32_selectb_128(1208 (__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B), (__v16qi)__W);1209}1210 1211/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161212/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1213/// Zeroing mask \a __U is used to determine if given element should be zeroed1214/// instead.1215///1216/// \code{.operation}1217/// FOR i := 0 to 15 1218/// IF __U[i]1219/// IF i < 81220/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1221/// ELSE1222/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])1223/// FI1224/// ELSE1225/// dst.bf8[i] := 01226/// FI1227/// ENDFOR1228///1229/// dst[MAX:128] := 01230/// \endcode1231///1232/// \headerfile <immintrin.h>1233///1234/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1235///1236/// \param __U1237/// A 16-bit zeroing mask.1238/// \param __A1239/// A 128-bit vector of [8 x fp16].1240/// \param __B1241/// A 128-bit vector of [8 x fp16].1242/// \returns1243/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1244/// (converted) elements from \a __B; higher order elements correspond to the1245/// (converted) elements from \a __A. If corresponding mask bit is not set, then1246/// zero is taken instead.1247static __inline__ __m128i __DEFAULT_FN_ATTRS1281248_mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {1249 return (__m128i)__builtin_ia32_selectb_128(1250 (__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B),1251 (__v16qi)(__m128i)_mm_setzero_si128());1252}1253 1254/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161255/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1256///1257/// \code{.operation}1258/// FOR i := 0 to 31 1259/// IF i < 16 1260/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1261/// ELSE1262/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])1263/// FI1264/// ENDFOR1265///1266/// dst[MAX:256] := 01267/// \endcode1268///1269/// \headerfile <immintrin.h>1270///1271/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1272///1273/// \param __A1274/// A 256-bit vector of [16 x fp16].1275/// \param __B1276/// A 256-bit vector of [16 x fp16].1277/// \returns1278/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1279/// (converted) elements from \a __B; higher order elements correspond to the1280/// (converted) elements from \a __A.1281static __inline__ __m256i __DEFAULT_FN_ATTRS2561282_mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {1283 return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A),1284 (__v16hf)(__B));1285}1286 1287/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161288/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1289/// Merging mask \a __U is used to determine if given element should be taken1290/// from \a __W instead.1291///1292/// \code{.operation}1293/// FOR i := 0 to 31 1294/// IF __U[i]1295/// IF i < 16 1296/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1297/// ELSE1298/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])1299/// FI1300/// ELSE1301/// dst.bf8[i] := __W.bf8[i]1302/// FI1303/// ENDFOR1304///1305/// dst[MAX:256] := 01306/// \endcode1307///1308/// \headerfile <immintrin.h>1309///1310/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1311///1312/// \param __W1313/// A 256-bit vector of [32 x bf8].1314/// \param __U1315/// A 32-bit merging mask.1316/// \param __A1317/// A 256-bit vector of [16 x fp16].1318/// \param __B1319/// A 256-bit vector of [16 x fp16].1320/// \returns1321/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1322/// (converted) elements from \a __B; higher order elements correspond to the1323/// (converted) elements from \a __A. If corresponding mask bit is not set, then1324/// element from \a __W is taken instead.1325static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(1326 __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {1327 return (__m256i)__builtin_ia32_selectb_256(1328 (__mmask32)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B), (__v32qi)__W);1329}1330 1331/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161332/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1333/// Zeroing mask \a __U is used to determine if given element should be zeroed1334/// instead.1335///1336/// \code{.operation}1337/// FOR i := 0 to 31 1338/// IF __U[i]1339/// IF i < 16 1340/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])1341/// ELSE1342/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])1343/// FI1344/// ELSE1345/// dst.bf8[i] := 01346/// FI1347/// ENDFOR1348///1349/// dst[MAX:256] := 01350/// \endcode1351///1352/// \headerfile <immintrin.h>1353///1354/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.1355///1356/// \param __U1357/// A 32-bit zeroing mask.1358/// \param __A1359/// A 256-bit vector of [16 x fp16].1360/// \param __B1361/// A 256-bit vector of [16 x fp16].1362/// \returns1363/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1364/// (converted) elements from \a __B; higher order elements correspond to the1365/// (converted) elements from \a __A. If corresponding mask bit is not set,1366/// zero is taken instead.1367static __inline__ __m256i __DEFAULT_FN_ATTRS2561368_mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {1369 return (__m256i)__builtin_ia32_selectb_256(1370 (__mmask32)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B),1371 (__v32qi)(__m256i)_mm256_setzero_si256());1372}1373 1374/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161375/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1376/// Resulting elements are saturated in case of overflow.1377///1378/// \code{.operation}1379/// FOR i := 0 to 15 1380/// IF i < 81381/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1382/// ELSE1383/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])1384/// FI1385/// ENDFOR1386///1387/// dst[MAX:128] := 01388/// \endcode1389///1390/// \headerfile <immintrin.h>1391///1392/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1393///1394/// \param __A1395/// A 128-bit vector of [8 x fp16].1396/// \param __B1397/// A 128-bit vector of [8 x fp16].1398/// \returns1399/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1400/// (converted) elements from \a __B; higher order elements correspond to the1401/// (converted) elements from \a __A.1402static __inline__ __m128i __DEFAULT_FN_ATTRS1281403_mm_cvts_2ph_bf8(__m128h __A, __m128h __B) {1404 return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A),1405 (__v8hf)(__B));1406}1407 1408/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161409/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1410/// Merging mask \a __U is used to determine if given element should be taken1411/// from \a __W instead. Resulting elements are saturated in case of overflow.1412///1413/// \code{.operation}1414/// FOR i := 0 to 15 1415/// IF __U[i]1416/// IF i < 81417/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1418/// ELSE1419/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])1420/// FI1421/// ELSE1422/// dst.bf8[i] := __W.bf8[i]1423/// FI1424/// ENDFOR1425///1426/// dst[MAX:128] := 01427/// \endcode1428///1429/// \headerfile <immintrin.h>1430///1431/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1432///1433/// \param __W1434/// A 128-bit vector of [16 x bf8].1435/// \param __U1436/// A 16-bit merging mask.1437/// \param __A1438/// A 128-bit vector of [8 x fp16].1439/// \param __B1440/// A 128-bit vector of [8 x fp16].1441/// \returns1442/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1443/// (converted) elements from \a __B; higher order elements correspond to the1444/// (converted) elements from \a __A. If corresponding mask bit is not set, then1445/// element from \a __W is taken instead.1446static __inline__ __m128i __DEFAULT_FN_ATTRS1281447_mm_mask_cvts_2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {1448 return (__m128i)__builtin_ia32_selectb_128(1449 (__mmask16)__U, (__v16qi)_mm_cvts_2ph_bf8(__A, __B), (__v16qi)__W);1450}1451 1452/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161453/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.1454/// Zeroing mask \a __U is used to determine if given element should be zeroed1455/// instead. Resulting elements are saturated in case of overflow.1456///1457/// \code{.operation}1458/// FOR i := 0 to 15 1459/// IF __U[i]1460/// IF i < 81461/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1462/// ELSE1463/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])1464/// FI1465/// ELSE1466/// dst.bf8[i] := 01467/// FI1468/// ENDFOR1469///1470/// dst[MAX:128] := 01471/// \endcode1472///1473/// \headerfile <immintrin.h>1474///1475/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1476///1477/// \param __U1478/// A 16-bit zeroing mask.1479/// \param __A1480/// A 128-bit vector of [8 x fp16].1481/// \param __B1482/// A 128-bit vector of [8 x fp16].1483/// \returns1484/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the1485/// (converted) elements from \a __B; higher order elements correspond to the1486/// (converted) elements from \a __A. If corresponding mask bit is not set, then1487/// zero is taken instead.1488static __inline__ __m128i __DEFAULT_FN_ATTRS1281489_mm_maskz_cvts_2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {1490 return (__m128i)__builtin_ia32_selectb_128(1491 (__mmask16)__U, (__v16qi)_mm_cvts_2ph_bf8(__A, __B),1492 (__v16qi)(__m128i)_mm_setzero_si128());1493}1494 1495/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161496/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1497/// Resulting elements are saturated in case of overflow.1498///1499/// \code{.operation}1500/// FOR i := 0 to 31 1501/// IF i < 16 1502/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1503/// ELSE1504/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])1505/// FI1506/// ENDFOR1507///1508/// dst[MAX:256] := 01509/// \endcode1510///1511/// \headerfile <immintrin.h>1512///1513/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1514///1515/// \param __A1516/// A 256-bit vector of [16 x fp16].1517/// \param __B1518/// A 256-bit vector of [16 x fp16].1519/// \returns1520/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1521/// (converted) elements from \a __B; higher order elements correspond to the1522/// (converted) elements from \a __A.1523static __inline__ __m256i __DEFAULT_FN_ATTRS2561524_mm256_cvts_2ph_bf8(__m256h __A, __m256h __B) {1525 return (__m256i)__builtin_ia32_vcvt2ph2bf8s_256((__v16hf)(__A),1526 (__v16hf)(__B));1527}1528 1529/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161530/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1531/// Merging mask \a __U is used to determine if given element should be taken1532/// from \a __W instead. Resulting elements are saturated in case of overflow.1533///1534/// \code{.operation}1535/// FOR i := 0 to 31 1536/// IF __U[i]1537/// IF i < 16 1538/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1539/// ELSE1540/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])1541/// FI1542/// ELSE1543/// dst.bf8[i] := __W.bf8[i]1544/// FI1545/// ENDFOR1546///1547/// dst[MAX:256] := 01548/// \endcode1549///1550/// \headerfile <immintrin.h>1551///1552/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1553///1554/// \param __W1555/// A 256-bit vector of [32 x bf8].1556/// \param __U1557/// A 32-bit merging mask.1558/// \param __A1559/// A 256-bit vector of [16 x fp16].1560/// \param __B1561/// A 256-bit vector of [16 x fp16].1562/// \returns1563/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1564/// (converted) elements from \a __B; higher order elements correspond to the1565/// (converted) elements from \a __A. If corresponding mask bit is not set, then1566/// element from \a __W is taken instead.1567static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_2ph_bf8(1568 __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {1569 return (__m256i)__builtin_ia32_selectb_256(1570 (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_bf8(__A, __B), (__v32qi)__W);1571}1572 1573/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161574/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.1575/// Zeroing mask \a __U is used to determine if given element should be zeroed1576/// instead. Resulting elements are saturated in case of overflow.1577///1578/// \code{.operation}1579/// FOR i := 0 to 31 1580/// IF __U[i]1581/// IF i < 16 1582/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])1583/// ELSE1584/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])1585/// FI1586/// ELSE1587/// dst.bf8[i] := 01588/// FI1589/// ENDFOR1590///1591/// dst[MAX:256] := 01592/// \endcode1593///1594/// \headerfile <immintrin.h>1595///1596/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.1597///1598/// \param __U1599/// A 32-bit zeroing mask.1600/// \param __A1601/// A 256-bit vector of [16 x fp16].1602/// \param __B1603/// A 256-bit vector of [16 x fp16].1604/// \returns1605/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the1606/// (converted) elements from \a __B; higher order elements correspond to the1607/// (converted) elements from \a __A. If corresponding mask bit is not set,1608/// zero is taken instead.1609static __inline__ __m256i __DEFAULT_FN_ATTRS2561610_mm256_maskz_cvts_2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {1611 return (__m256i)__builtin_ia32_selectb_256(1612 (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_bf8(__A, __B),1613 (__v32qi)(__m256i)_mm256_setzero_si256());1614}1615 1616/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161617/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1618///1619/// \code{.operation}1620/// FOR i := 0 to 15 1621/// IF i < 81622/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1623/// ELSE1624/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])1625/// FI1626/// ENDFOR1627///1628/// dst[MAX:128] := 01629/// \endcode1630///1631/// \headerfile <immintrin.h>1632///1633/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1634///1635/// \param __A1636/// A 128-bit vector of [8 x fp16].1637/// \param __B1638/// A 128-bit vector of [8 x fp16].1639/// \returns1640/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1641/// (converted) elements from \a __B; higher order elements correspond to the1642/// (converted) elements from \a __A.1643static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,1644 __m128h __B) {1645 return (__m128i)__builtin_ia32_vcvt2ph2hf8_128((__v8hf)(__A),1646 (__v8hf)(__B));1647}1648 1649/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161650/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1651/// Merging mask \a __U is used to determine if given element should be taken1652/// from \a __W instead.1653///1654/// \code{.operation}1655/// FOR i := 0 to 15 1656/// IF __U[i]1657/// IF i < 81658/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1659/// ELSE1660/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])1661/// FI1662/// ELSE1663/// dst.hf8[i] := __W.hf8[i]1664/// FI1665/// ENDFOR1666///1667/// dst[MAX:128] := 01668/// \endcode1669///1670/// \headerfile <immintrin.h>1671///1672/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1673///1674/// \param __W1675/// A 128-bit vector of [16 x hf8].1676/// \param __U1677/// A 16-bit merging mask.1678/// \param __A1679/// A 128-bit vector of [8 x fp16].1680/// \param __B1681/// A 128-bit vector of [8 x fp16].1682/// \returns1683/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1684/// (converted) elements from \a __B; higher order elements correspond to the1685/// (converted) elements from \a __A. If corresponding mask bit is not set, then1686/// element from \a __W is taken instead.1687static __inline__ __m128i __DEFAULT_FN_ATTRS1281688_mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {1689 return (__m128i)__builtin_ia32_selectb_128(1690 (__mmask16)__U, (__v16qi)_mm_cvt2ph_hf8(__A, __B), (__v16qi)__W);1691}1692 1693/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161694/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1695/// Zeroing mask \a __U is used to determine if given element should be zeroed1696/// instead.1697///1698/// \code{.operation}1699/// FOR i := 0 to 15 1700/// IF __U[i]1701/// IF i < 81702/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1703/// ELSE1704/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])1705/// FI1706/// ELSE1707/// dst.hf8[i] := 01708/// FI1709/// ENDFOR1710///1711/// dst[MAX:128] := 01712/// \endcode1713///1714/// \headerfile <immintrin.h>1715///1716/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1717///1718/// \param __U1719/// A 16-bit zeroing mask.1720/// \param __A1721/// A 128-bit vector of [8 x fp16].1722/// \param __B1723/// A 128-bit vector of [8 x fp16].1724/// \returns1725/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1726/// (converted) elements from \a __B; higher order elements correspond to the1727/// (converted) elements from \a __A. If corresponding mask bit is not set, then1728/// zero is taken instead.1729static __inline__ __m128i __DEFAULT_FN_ATTRS1281730_mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {1731 return (__m128i)__builtin_ia32_selectb_128(1732 (__mmask16)__U, (__v16qi)_mm_cvt2ph_hf8(__A, __B),1733 (__v16qi)(__m128i)_mm_setzero_si128());1734}1735 1736/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161737/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.1738///1739/// \code{.operation}1740/// FOR i := 0 to 31 1741/// IF i < 16 1742/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1743/// ELSE1744/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])1745/// FI1746/// ENDFOR1747///1748/// dst[MAX:256] := 01749/// \endcode1750///1751/// \headerfile <immintrin.h>1752///1753/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1754///1755/// \param __A1756/// A 256-bit vector of [16 x fp16].1757/// \param __B1758/// A 256-bit vector of [16 x fp16].1759/// \returns1760/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the1761/// (converted) elements from \a __B; higher order elements correspond to the1762/// (converted) elements from \a __A.1763static __inline__ __m256i __DEFAULT_FN_ATTRS2561764_mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {1765 return (__m256i)__builtin_ia32_vcvt2ph2hf8_256((__v16hf)(__A),1766 (__v16hf)(__B));1767}1768 1769/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161770/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.1771/// Merging mask \a __U is used to determine if given element should be taken1772/// from \a __W instead.1773///1774/// \code{.operation}1775/// FOR i := 0 to 31 1776/// IF __U[i]1777/// IF i < 16 1778/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1779/// ELSE1780/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])1781/// FI1782/// ELSE1783/// dst.hf8[i] := __W.hf8[i]1784/// FI1785/// ENDFOR1786///1787/// dst[MAX:256] := 01788/// \endcode1789///1790/// \headerfile <immintrin.h>1791///1792/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1793///1794/// \param __W1795/// A 256-bit vector of [32 x hf8].1796/// \param __U1797/// A 32-bit merging mask.1798/// \param __A1799/// A 256-bit vector of [16 x fp16].1800/// \param __B1801/// A 256-bit vector of [16 x fp16].1802/// \returns1803/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the1804/// (converted) elements from \a __B; higher order elements correspond to the1805/// (converted) elements from \a __A. If corresponding mask bit is not set, then1806/// element from \a __W is taken instead.1807static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(1808 __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {1809 return (__m256i)__builtin_ia32_selectb_256(1810 (__mmask32)__U, (__v32qi)_mm256_cvt2ph_hf8(__A, __B), (__v32qi)__W);1811}1812 1813/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161814/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.1815/// Zeroing mask \a __U is used to determine if given element should be zeroed1816/// instead.1817///1818/// \code{.operation}1819/// FOR i := 0 to 31 1820/// IF __U[i]1821/// IF i < 16 1822/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])1823/// ELSE1824/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])1825/// FI1826/// ELSE1827/// dst.hf8[i] := 01828/// FI1829/// ENDFOR1830///1831/// dst[MAX:256] := 01832/// \endcode1833///1834/// \headerfile <immintrin.h>1835///1836/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.1837///1838/// \param __U1839/// A 32-bit zeroing mask.1840/// \param __A1841/// A 256-bit vector of [16 x fp16].1842/// \param __B1843/// A 256-bit vector of [16 x fp16].1844/// \returns1845/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the1846/// (converted) elements from \a __B; higher order elements correspond to the1847/// (converted) elements from \a __A. If corresponding mask bit is not set,1848/// zero is taken instead.1849static __inline__ __m256i __DEFAULT_FN_ATTRS2561850_mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {1851 return (__m256i)__builtin_ia32_selectb_256(1852 (__mmask32)__U, (__v32qi)_mm256_cvt2ph_hf8(__A, __B),1853 (__v32qi)(__m256i)_mm256_setzero_si256());1854}1855 1856/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161857/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1858/// Resulting elements are saturated in case of overflow.1859///1860/// \code{.operation}1861/// FOR i := 0 to 15 1862/// IF i < 81863/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])1864/// ELSE1865/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])1866/// FI1867/// ENDFOR1868///1869/// dst[MAX:128] := 01870/// \endcode1871///1872/// \headerfile <immintrin.h>1873///1874/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.1875///1876/// \param __A1877/// A 128-bit vector of [8 x fp16].1878/// \param __B1879/// A 128-bit vector of [8 x fp16].1880/// \returns1881/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1882/// (converted) elements from \a __B; higher order elements correspond to the1883/// (converted) elements from \a __A.1884static __inline__ __m128i __DEFAULT_FN_ATTRS1281885_mm_cvts_2ph_hf8(__m128h __A, __m128h __B) {1886 return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A),1887 (__v8hf)(__B));1888}1889 1890/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161891/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1892/// Merging mask \a __U is used to determine if given element should be taken1893/// from \a __W instead. Resulting elements are saturated in case of overflow.1894///1895/// \code{.operation}1896/// FOR i := 0 to 15 1897/// IF __U[i]1898/// IF i < 81899/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])1900/// ELSE1901/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])1902/// FI1903/// ELSE1904/// dst.hf8[i] := __W.hf8[i]1905/// FI1906/// ENDFOR1907///1908/// dst[MAX:128] := 01909/// \endcode1910///1911/// \headerfile <immintrin.h>1912///1913/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.1914///1915/// \param __W1916/// A 128-bit vector of [16 x hf8].1917/// \param __U1918/// A 16-bit merging mask.1919/// \param __A1920/// A 128-bit vector of [8 x fp16].1921/// \param __B1922/// A 128-bit vector of [8 x fp16].1923/// \returns1924/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1925/// (converted) elements from \a __B; higher order elements correspond to the1926/// (converted) elements from \a __A. If corresponding mask bit is not set, then1927/// element from \a __W is taken instead.1928static __inline__ __m128i __DEFAULT_FN_ATTRS1281929_mm_mask_cvts_2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {1930 return (__m128i)__builtin_ia32_selectb_128(1931 (__mmask16)__U, (__v16qi)_mm_cvts_2ph_hf8(__A, __B), (__v16qi)__W);1932}1933 1934/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP161935/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.1936/// Zeroing mask \a __U is used to determine if given element should be zeroed1937/// instead. Resulting elements are saturated in case of overflow.1938///1939/// \code{.operation}1940/// FOR i := 0 to 15 1941/// IF __U[i]1942/// IF i < 81943/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])1944/// ELSE1945/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])1946/// FI1947/// ELSE1948/// dst.hf8[i] := 01949/// FI1950/// ENDFOR1951///1952/// dst[MAX:128] := 01953/// \endcode1954///1955/// \headerfile <immintrin.h>1956///1957/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.1958///1959/// \param __U1960/// A 16-bit zeroing mask.1961/// \param __A1962/// A 128-bit vector of [8 x fp16].1963/// \param __B1964/// A 128-bit vector of [8 x fp16].1965/// \returns1966/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the1967/// (converted) elements from \a __B; higher order elements correspond to the1968/// (converted) elements from \a __A. If corresponding mask bit is not set, then1969/// zero is taken instead.1970static __inline__ __m128i __DEFAULT_FN_ATTRS1281971_mm_maskz_cvts_2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {1972 return (__m128i)__builtin_ia32_selectb_128(1973 (__mmask16)__U, (__v16qi)_mm_cvts_2ph_hf8(__A, __B),1974 (__v16qi)(__m128i)_mm_setzero_si128());1975}1976 1977/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP161978/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.1979/// Resulting elements are saturated in case of overflow.1980///1981/// \code{.operation}1982/// FOR i := 0 to 31 1983/// IF i < 16 1984/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])1985/// ELSE1986/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])1987/// FI1988/// ENDFOR1989///1990/// dst[MAX:256] := 01991/// \endcode1992///1993/// \headerfile <immintrin.h>1994///1995/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.1996///1997/// \param __A1998/// A 256-bit vector of [16 x fp16].1999/// \param __B2000/// A 256-bit vector of [16 x fp16].2001/// \returns2002/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the2003/// (converted) elements from \a __B; higher order elements correspond to the2004/// (converted) elements from \a __A.2005static __inline__ __m256i __DEFAULT_FN_ATTRS2562006_mm256_cvts_2ph_hf8(__m256h __A, __m256h __B) {2007 return (__m256i)__builtin_ia32_vcvt2ph2hf8s_256((__v16hf)(__A),2008 (__v16hf)(__B));2009}2010 2011/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP162012/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.2013/// Merging mask \a __U is used to determine if given element should be taken2014/// from \a __W instead. Resulting elements are saturated in case of overflow.2015///2016/// \code{.operation}2017/// FOR i := 0 to 31 2018/// IF __U[i]2019/// IF i < 16 2020/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])2021/// ELSE2022/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])2023/// FI2024/// ELSE2025/// dst.hf8[i] := __W.hf8[i]2026/// FI2027/// ENDFOR2028///2029/// dst[MAX:256] := 02030/// \endcode2031///2032/// \headerfile <immintrin.h>2033///2034/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.2035///2036/// \param __W2037/// A 256-bit vector of [32 x hf8].2038/// \param __U2039/// A 32-bit merging mask.2040/// \param __A2041/// A 256-bit vector of [16 x fp16].2042/// \param __B2043/// A 256-bit vector of [16 x fp16].2044/// \returns2045/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the2046/// (converted) elements from \a __B; higher order elements correspond to the2047/// (converted) elements from \a __A. If corresponding mask bit is not set, then2048/// element from \a __W is taken instead.2049static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_2ph_hf8(2050 __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {2051 return (__m256i)__builtin_ia32_selectb_256(2052 (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_hf8(__A, __B), (__v32qi)__W);2053}2054 2055/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP162056/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.2057/// Zeroing mask \a __U is used to determine if given element should be zeroed2058/// instead. Resulting elements are saturated in case of overflow.2059///2060/// \code{.operation}2061/// FOR i := 0 to 31 2062/// IF __U[i]2063/// IF i < 16 2064/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])2065/// ELSE2066/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])2067/// FI2068/// ELSE2069/// dst.hf8[i] := 02070/// FI2071/// ENDFOR2072///2073/// dst[MAX:256] := 02074/// \endcode2075///2076/// \headerfile <immintrin.h>2077///2078/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.2079///2080/// \param __U2081/// A 32-bit zeroing mask.2082/// \param __A2083/// A 256-bit vector of [16 x fp16].2084/// \param __B2085/// A 256-bit vector of [16 x fp16].2086/// \returns2087/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the2088/// (converted) elements from \a __B; higher order elements correspond to the2089/// (converted) elements from \a __A. If corresponding mask bit is not set,2090/// zero is taken instead.2091static __inline__ __m256i __DEFAULT_FN_ATTRS2562092_mm256_maskz_cvts_2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {2093 return (__m256i)__builtin_ia32_selectb_256(2094 (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_hf8(__A, __B),2095 (__v32qi)(__m256i)_mm256_setzero_si256());2096}2097 2098/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point2099/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.2100///2101/// \code{.operation}2102/// FOR i := 0 to 72103/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2104/// ENDFOR2105///2106/// dst[MAX:128] := 02107/// \endcode2108///2109/// \headerfile <immintrin.h>2110///2111/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2112///2113/// \param __A2114/// A 128-bit vector of [16 x hf8].2115/// \returns2116/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the2117/// (converted) elements from \a __A.2118static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8_ph(__m128i __A) {2119 return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(2120 (__v16qi)__A, (__v8hf)(__m128h)_mm_undefined_ph(), (__mmask8)-1);2121}2122 2123/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point2124/// elements to a 128-bit vector containing FP16 elements. The conversion is2125/// exact. Merging mask \a __U is used to determine if given element should be2126/// taken from \a __W instead.2127///2128/// \code{.operation}2129/// FOR i := 0 to 72130/// IF __U[i]2131/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2132/// ELSE2133/// dst.fp16[i] := __W.fp16[i]2134/// FI2135/// ENDFOR2136///2137/// dst[MAX:128] := 02138/// \endcode2139///2140/// \headerfile <immintrin.h>2141///2142/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2143///2144/// \param __W2145/// A 128-bit vector of [8 x fp16].2146/// \param __U2147/// A 8-bit merging mask.2148/// \param __A2149/// A 128-bit vector of [16 x hf8].2150/// \returns2151/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the2152/// (converted) elements from \a __A. If corresponding mask bit is not set, then2153/// element from \a __W is taken instead.2154static __inline__ __m128h __DEFAULT_FN_ATTRS1282155_mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {2156 return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(2157 (__v16qi)__A, (__v8hf)(__m128h)__W, (__mmask8)__U);2158}2159 2160/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point2161/// elements to a 128-bit vector containing FP16 elements. The conversion is2162/// exact. Zeroing mask \a __U is used to determine if given element should be2163/// zeroed instead.2164///2165/// \code{.operation}2166/// FOR i := 0 to 72167/// IF __U[i]2168/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2169/// ELSE2170/// dst.fp16[i] := 02171/// FI2172/// ENDFOR2173///2174/// dst[MAX:128] := 02175/// \endcode2176///2177/// \headerfile <immintrin.h>2178///2179/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2180///2181/// \param __U2182/// A 8-bit zeroing mask.2183/// \param __A2184/// A 128-bit vector of [16 x hf8].2185/// \returns2186/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the2187/// (converted) elements from \a __A. If corresponding mask bit is not set, then2188/// zero is taken instead.2189static __inline__ __m128h __DEFAULT_FN_ATTRS1282190_mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A) {2191 return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(2192 (__v16qi)__A, (__v8hf)(__m128h)_mm_setzero_ph(), (__mmask8)__U);2193}2194 2195/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point2196/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.2197///2198/// \code{.operation}2199/// FOR i := 0 to 152200/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2201/// ENDFOR2202///2203/// dst[MAX:256] := 02204/// \endcode2205///2206/// \headerfile <immintrin.h>2207///2208/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2209///2210/// \param __A2211/// A 256-bit vector of [32 x hf8].2212/// \returns2213/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the2214/// (converted) elements from \a __A.2215static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8_ph(__m128i __A) {2216 return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(2217 (__v16qi)__A, (__v16hf)(__m256h)_mm256_undefined_ph(), (__mmask16)-1);2218}2219 2220/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point2221/// elements to a 256-bit vector containing FP16 elements. The conversion is2222/// exact. Merging mask \a __U is used to determine if given element should be2223/// taken from \a __W instead.2224///2225/// \code{.operation}2226/// FOR i := 0 to 15 2227/// IF __U[i]2228/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2229/// ELSE2230/// dst.fp16[i] := __W.fp16[i]2231/// FI2232/// ENDFOR2233///2234/// dst[MAX:256] := 02235/// \endcode2236///2237/// \headerfile <immintrin.h>2238///2239/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2240///2241/// \param __W2242/// A 256-bit vector of [16 x fp16].2243/// \param __U2244/// A 16-bit merging mask.2245/// \param __A2246/// A 256-bit vector of [32 x hf8].2247/// \returns2248/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the2249/// (converted) elements from \a __A. If corresponding mask bit is not set, then2250/// element from \a __W is taken instead.2251static __inline__ __m256h __DEFAULT_FN_ATTRS2562252_mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {2253 return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(2254 (__v16qi)__A, (__v16hf)(__m256h)__W, (__mmask16)__U);2255}2256 2257/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point2258/// elements to a 256-bit vector containing FP16 elements. The conversion is2259/// exact. Zeroing mask \a __U is used to determine if given element should be2260/// zeroed instead.2261///2262/// \code{.operation}2263/// FOR i := 0 to 15 2264/// IF __U[i]2265/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])2266/// ELSE2267/// dst.fp16[i] := 02268/// FI2269/// ENDFOR2270///2271/// dst[MAX:256] := 02272/// \endcode2273///2274/// \headerfile <immintrin.h>2275///2276/// This intrinsic corresponds to the \c VCVTHF82PH instruction.2277///2278/// \param __U2279/// A 16-bit zeroing mask.2280/// \param __A2281/// A 256-bit vector of [32 x hf8].2282/// \returns2283/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the2284/// (converted) elements from \a __A. If corresponding mask bit is not set, then2285/// zero is taken instead.2286static __inline__ __m256h __DEFAULT_FN_ATTRS2562287_mm256_maskz_cvthf8_ph(__mmask16 __U, __m128i __A) {2288 return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(2289 (__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U);2290}2291 2292/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2293/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2294/// resulting vector are zeroed.2295///2296/// \code{.operation}2297/// FOR i := 0 to 72298/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2299/// ENDFOR2300///2301/// dst[MAX:64] := 02302/// \endcode2303///2304/// \headerfile <immintrin.h>2305///2306/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2307///2308/// \param __A2309/// A 128-bit vector of [8 x fp16].2310/// \returns2311/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)2312/// elements from \a __A; upper elements are zeroed. 2313static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {2314 return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(2315 (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);2316}2317 2318/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2319/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2320/// resulting vector are zeroed. Merging mask \a __U is used to determine if2321/// given element should be taken from \a __W instead.2322///2323/// \code{.operation}2324/// FOR i := 0 to 72325/// IF __U[i]2326/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2327/// ELSE2328/// dst.bf8[i] := __W.bf8[i]2329/// FI2330/// ENDFOR2331///2332/// dst[MAX:64] := 02333/// \endcode2334///2335/// \headerfile <immintrin.h>2336///2337/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2338///2339/// \param __W2340/// A 128-bit vector of [16 x bf8].2341/// \param __U2342/// A 8-bit merging mask.2343/// \param __A2344/// A 128-bit vector of [8 x fp16].2345/// \returns2346/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the2347/// (converted) elements from \a __A; upper elements are zeroed. If2348/// corresponding mask bit is not set, then element from \a __W is taken instead.2349static __inline__ __m128i __DEFAULT_FN_ATTRS1282350_mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {2351 return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(2352 (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);2353}2354 2355/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2356/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2357/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if2358/// given element should be zeroed instead.2359///2360/// \code{.operation}2361/// FOR i := 0 to 72362/// IF __U[i]2363/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2364/// ELSE2365/// dst.bf8[i] := 02366/// FI2367/// ENDFOR2368///2369/// dst[MAX:64] := 02370/// \endcode2371///2372/// \headerfile <immintrin.h>2373///2374/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2375///2376/// \param __U2377/// A 8-bit zeroing mask.2378/// \param __A2379/// A 128-bit vector of [8 x fp16].2380/// \returns2381/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the2382/// (converted) elements from \a __A; upper elements are zeroed. If2383/// corresponding mask bit is not set, then element is zeroed.2384static __inline__ __m128i __DEFAULT_FN_ATTRS1282385_mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {2386 return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(2387 (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);2388}2389 2390/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2391/// to a 128-bit vector containing E5M2 FP8 elements.2392///2393/// \code{.operation}2394/// FOR i := 0 to 152395/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2396/// ENDFOR2397///2398/// dst[MAX:128] := 02399/// \endcode2400///2401/// \headerfile <immintrin.h>2402///2403/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2404///2405/// \param __A2406/// A 256-bit vector of [16 x fp16].2407/// \returns2408/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)2409/// elements from \a __A.2410static __inline__ __m128i __DEFAULT_FN_ATTRS2562411_mm256_cvtph_bf8(__m256h __A) {2412 return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(2413 (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);2414}2415 2416/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2417/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is2418/// used to determine if given element should be taken from \a __W instead.2419/// 2420/// \code{.operation}2421/// FOR i := 0 to 152422/// IF __U[i]2423/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2424/// ELSE2425/// dst.bf8[i] := __W.bf8[i]2426/// FI2427/// ENDFOR2428///2429/// dst[MAX:128] := 02430/// \endcode2431///2432/// \headerfile <immintrin.h>2433///2434/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2435///2436/// \param __W2437/// A 128-bit vector of [16 x bf8].2438/// \param __U2439/// A 16-bit merging mask.2440/// \param __A2441/// A 256-bit vector of [8 x fp16].2442/// \returns2443/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the2444/// (converted) elements from \a __A. If2445/// corresponding mask bit is not set, then element from \a __W is taken instead.2446static __inline__ __m128i __DEFAULT_FN_ATTRS2562447_mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {2448 return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(2449 (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);2450}2451 2452/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2453/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is2454/// used to determine if given element should be zeroed instead.2455/// 2456/// \code{.operation}2457/// FOR i := 0 to 152458/// IF __U[i]2459/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])2460/// ELSE2461/// dst.bf8[i] := 02462/// FI2463/// ENDFOR2464///2465/// dst[MAX:128] := 02466/// \endcode2467///2468/// \headerfile <immintrin.h>2469///2470/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.2471///2472/// \param __U2473/// A 16-bit zeroing mask.2474/// \param __A2475/// A 256-bit vector of [16 x fp16].2476/// \returns2477/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the2478/// (converted) elements from \a __A. If corresponding mask bit is not set,2479/// then element is zeroed instead.2480static __inline__ __m128i __DEFAULT_FN_ATTRS2562481_mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {2482 return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(2483 (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);2484}2485 2486/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2487/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2488/// resulting vector are zeroed. Results are saturated.2489/// 2490/// \code{.operation}2491/// FOR i := 0 to 72492/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2493/// ENDFOR2494///2495/// dst[MAX:64] := 02496/// \endcode2497///2498/// \headerfile <immintrin.h>2499///2500/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2501///2502/// \param __A2503/// A 128-bit vector of [8 x fp16].2504/// \returns2505/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)2506/// elements from \a __A; upper elements are zeroed. 2507static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_ph_bf8(__m128h __A) {2508 return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(2509 (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);2510}2511 2512/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2513/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2514/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is2515/// used to determine if given element should be taken from \a __W instead.2516///2517/// \code{.operation}2518/// FOR i := 0 to 72519/// IF __U[i]2520/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2521/// ELSE2522/// dst.bf8[i] := __W.bf8[i]2523/// FI2524/// ENDFOR2525///2526/// dst[MAX:64] := 02527/// \endcode2528///2529/// \headerfile <immintrin.h>2530///2531/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2532///2533/// \param __W2534/// A 128-bit vector of [16 x bf8].2535/// \param __U2536/// A 8-bit merging mask.2537/// \param __A2538/// A 128-bit vector of [8 x fp16].2539/// \returns2540/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the2541/// (converted) elements from \a __A; upper elements are zeroed. If2542/// corresponding mask bit is not set, then element from \a __W is taken instead.2543static __inline__ __m128i __DEFAULT_FN_ATTRS1282544_mm_mask_cvts_ph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {2545 return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(2546 (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);2547}2548 2549/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2550/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2551/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is2552/// used to determine if given element should be zeroed instead.2553///2554/// \code{.operation}2555/// FOR i := 0 to 72556/// IF __U[i]2557/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2558/// ELSE2559/// dst.bf8[i] := 02560/// FI2561/// ENDFOR2562///2563/// dst[MAX:64] := 02564/// \endcode2565///2566/// \headerfile <immintrin.h>2567///2568/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2569///2570/// \param __U2571/// A 8-bit zeroing mask.2572/// \param __A2573/// A 128-bit vector of [8 x fp16].2574/// \returns2575/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the2576/// (converted) elements from \a __A; upper elements are zeroed. If2577/// corresponding mask bit is not set, then element is zeroed.2578static __inline__ __m128i __DEFAULT_FN_ATTRS1282579_mm_maskz_cvts_ph_bf8(__mmask8 __U, __m128h __A) {2580 return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(2581 (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);2582}2583 2584/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2585/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.2586///2587/// \code{.operation}2588/// FOR i := 0 to 152589/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2590/// ENDFOR2591///2592/// dst[MAX:128] := 02593/// \endcode2594///2595/// \headerfile <immintrin.h>2596///2597/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2598///2599/// \param __A2600/// A 256-bit vector of [16 x fp16].2601/// \returns2602/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)2603/// elements from \a __A.2604static __inline__ __m128i __DEFAULT_FN_ATTRS2562605_mm256_cvts_ph_bf8(__m256h __A) {2606 return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(2607 (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);2608}2609 2610/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2611/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.2612/// Merging mask \a __U is used to determine if given element should be taken2613/// from \a __W instead.2614///2615/// \code{.operation}2616/// FOR i := 0 to 152617/// IF __U[i]2618/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2619/// ELSE2620/// dst.bf8[i] := __W.bf8[i]2621/// FI2622/// ENDFOR2623///2624/// dst[MAX:128] := 02625/// \endcode2626///2627/// \headerfile <immintrin.h>2628///2629/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2630///2631/// \param __W2632/// A 128-bit vector of [16 x bf8].2633/// \param __U2634/// A 16-bit merging mask.2635/// \param __A2636/// A 256-bit vector of [8 x fp16].2637/// \returns2638/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the2639/// (converted) elements from \a __A. If2640/// corresponding mask bit is not set, then element from \a __W is taken instead.2641static __inline__ __m128i __DEFAULT_FN_ATTRS2562642_mm256_mask_cvts_ph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {2643 return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(2644 (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);2645}2646 2647/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2648/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.2649/// Zeroing mask \a __U is used to determine if given element should be zeroed2650/// instead.2651///2652/// \code{.operation}2653/// FOR i := 0 to 15 2654/// IF __U[i]2655/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])2656/// ELSE2657/// dst.bf8[i] := 02658/// FI2659/// ENDFOR2660///2661/// dst[MAX:128] := 02662/// \endcode2663///2664/// \headerfile <immintrin.h>2665///2666/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.2667///2668/// \param __U2669/// A 16-bit zeroing mask.2670/// \param __A2671/// A 256-bit vector of [16 x fp16].2672/// \returns2673/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the2674/// (converted) elements from \a __A. If corresponding mask bit is not set,2675/// then element is zeroed instead.2676static __inline__ __m128i __DEFAULT_FN_ATTRS2562677_mm256_maskz_cvts_ph_bf8(__mmask16 __U, __m256h __A) {2678 return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(2679 (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);2680}2681 2682/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2683/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of2684/// resulting vector are zeroed.2685///2686/// \code{.operation}2687/// FOR i := 0 to 72688/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2689/// ENDFOR2690///2691/// dst[MAX:64] := 02692/// \endcode2693///2694/// \headerfile <immintrin.h>2695///2696/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2697///2698/// \param __A2699/// A 128-bit vector of [8 x fp16].2700/// \returns2701/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)2702/// elements from \a __A; upper elements are zeroed. 2703static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {2704 return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(2705 (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);2706}2707 2708/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2709/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of2710/// resulting vector are zeroed. Merging mask \a __U is used to determine if2711/// given element should be taken from \a __W instead.2712///2713/// \code{.operation}2714/// FOR i := 0 to 72715/// IF __U[i]2716/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2717/// ELSE2718/// dst.hf8[i] := __W.hf8[i]2719/// FI2720/// ENDFOR2721///2722/// dst[MAX:64] := 02723/// \endcode2724///2725/// \headerfile <immintrin.h>2726///2727/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2728///2729/// \param __W2730/// A 128-bit vector of [16 x hf8].2731/// \param __U2732/// A 8-bit merging mask.2733/// \param __A2734/// A 128-bit vector of [8 x fp16].2735/// \returns2736/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the2737/// (converted) elements from \a __A; upper elements are zeroed. If2738/// corresponding mask bit is not set, then element from \a __W is taken instead.2739static __inline__ __m128i __DEFAULT_FN_ATTRS1282740_mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {2741 return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(2742 (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);2743}2744 2745/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2746/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of2747/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if2748/// given element should be zeroed instead.2749///2750/// \code{.operation}2751/// FOR i := 0 to 72752/// IF __U[i]2753/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2754/// ELSE2755/// dst.hf8[i] := 02756/// FI2757/// ENDFOR2758///2759/// dst[MAX:64] := 02760/// \endcode2761///2762/// \headerfile <immintrin.h>2763///2764/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2765///2766/// \param __U2767/// A 8-bit zeroing mask.2768/// \param __A2769/// A 128-bit vector of [8 x fp16].2770/// \returns2771/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the2772/// (converted) elements from \a __A; upper elements are zeroed. If2773/// corresponding mask bit is not set, then element is zeroed.2774static __inline__ __m128i __DEFAULT_FN_ATTRS1282775_mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {2776 return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(2777 (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);2778}2779 2780/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2781/// to a 128-bit vector containing E4M3 FP8 elements.2782///2783/// \code{.operation}2784/// FOR i := 0 to 152785/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2786/// ENDFOR2787///2788/// dst[MAX:128] := 02789/// \endcode2790///2791/// \headerfile <immintrin.h>2792///2793/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2794///2795/// \param __A2796/// A 256-bit vector of [16 x fp16].2797/// \returns2798/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)2799/// elements from \a __A.2800static __inline__ __m128i __DEFAULT_FN_ATTRS2562801_mm256_cvtph_hf8(__m256h __A) {2802 return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(2803 (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);2804}2805 2806/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2807/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is2808/// used to determine if given element should be taken from \a __W instead.2809/// 2810/// \code{.operation}2811/// FOR i := 0 to 152812/// IF __U[i]2813/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2814/// ELSE2815/// dst.hf8[i] := __W.hf8[i]2816/// FI2817/// ENDFOR2818///2819/// dst[MAX:128] := 02820/// \endcode2821///2822/// \headerfile <immintrin.h>2823///2824/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2825///2826/// \param __W2827/// A 128-bit vector of [16 x hf8].2828/// \param __U2829/// A 16-bit merging mask.2830/// \param __A2831/// A 256-bit vector of [8 x fp16].2832/// \returns2833/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the2834/// (converted) elements from \a __A. If2835/// corresponding mask bit is not set, then element from \a __W is taken instead.2836static __inline__ __m128i __DEFAULT_FN_ATTRS2562837_mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {2838 return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(2839 (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);2840}2841 2842/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2843/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is2844/// used to determine if given element should be zeroed instead.2845/// 2846/// \code{.operation}2847/// FOR i := 0 to 152848/// IF __U[i]2849/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])2850/// ELSE2851/// dst.hf8[i] := 02852/// FI2853/// ENDFOR2854///2855/// dst[MAX:128] := 02856/// \endcode2857///2858/// \headerfile <immintrin.h>2859///2860/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.2861///2862/// \param __U2863/// A 16-bit zeroing mask.2864/// \param __A2865/// A 256-bit vector of [16 x fp16].2866/// \returns2867/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the2868/// (converted) elements from \a __A. If corresponding mask bit is not set,2869/// then element is zeroed instead.2870static __inline__ __m128i __DEFAULT_FN_ATTRS2562871_mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {2872 return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(2873 (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);2874}2875 2876/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2877/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of2878/// resulting vector are zeroed. Results are saturated.2879/// 2880/// \code{.operation}2881/// FOR i := 0 to 72882/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])2883/// ENDFOR2884///2885/// dst[MAX:64] := 02886/// \endcode2887///2888/// \headerfile <immintrin.h>2889///2890/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.2891///2892/// \param __A2893/// A 128-bit vector of [8 x fp16].2894/// \returns2895/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)2896/// elements from \a __A; upper elements are zeroed. 2897static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_ph_hf8(__m128h __A) {2898 return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(2899 (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);2900}2901 2902/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2903/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of2904/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is2905/// used to determine if given element should be taken from \a __W instead.2906///2907/// \code{.operation}2908/// FOR i := 0 to 72909/// IF __U[i]2910/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])2911/// ELSE2912/// dst.hf8[i] := __W.hf8[i]2913/// FI2914/// ENDFOR2915///2916/// dst[MAX:64] := 02917/// \endcode2918///2919/// \headerfile <immintrin.h>2920///2921/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.2922///2923/// \param __W2924/// A 128-bit vector of [16 x hf8].2925/// \param __U2926/// A 8-bit merging mask.2927/// \param __A2928/// A 128-bit vector of [8 x fp16].2929/// \returns2930/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the2931/// (converted) elements from \a __A; upper elements are zeroed. If2932/// corresponding mask bit is not set, then element from \a __W is taken instead.2933static __inline__ __m128i __DEFAULT_FN_ATTRS1282934_mm_mask_cvts_ph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {2935 return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(2936 (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);2937}2938 2939/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements2940/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of2941/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is2942/// used to determine if given element should be zeroed instead.2943///2944/// \code{.operation}2945/// FOR i := 0 to 72946/// IF __U[i]2947/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])2948/// ELSE2949/// dst.hf8[i] := 02950/// FI2951/// ENDFOR2952///2953/// dst[MAX:64] := 02954/// \endcode2955///2956/// \headerfile <immintrin.h>2957///2958/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.2959///2960/// \param __U2961/// A 8-bit zeroing mask.2962/// \param __A2963/// A 128-bit vector of [8 x fp16].2964/// \returns2965/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the2966/// (converted) elements from \a __A; upper elements are zeroed. If2967/// corresponding mask bit is not set, then element is zeroed.2968static __inline__ __m128i __DEFAULT_FN_ATTRS1282969_mm_maskz_cvts_ph_hf8(__mmask8 __U, __m128h __A) {2970 return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(2971 (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);2972}2973 2974/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements2975/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.2976///2977/// \code{.operation}2978/// FOR i := 0 to 152979/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])2980/// ENDFOR2981///2982/// dst[MAX:128] := 02983/// \endcode2984///2985/// \headerfile <immintrin.h>2986///2987/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.2988///2989/// \param __A2990/// A 256-bit vector of [16 x fp16].2991/// \returns2992/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)2993/// elements from \a __A.2994static __inline__ __m128i __DEFAULT_FN_ATTRS2562995_mm256_cvts_ph_hf8(__m256h __A) {2996 return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(2997 (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);2998}2999 3000/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements3001/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.3002/// Merging mask \a __U is used to determine if given element should be taken3003/// from \a __W instead.3004///3005/// \code{.operation}3006/// FOR i := 0 to 153007/// IF __U[i]3008/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])3009/// ELSE3010/// dst.hf8[i] := __W.hf8[i]3011/// FI3012/// ENDFOR3013///3014/// dst[MAX:128] := 03015/// \endcode3016///3017/// \headerfile <immintrin.h>3018///3019/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.3020///3021/// \param __W3022/// A 128-bit vector of [16 x hf8].3023/// \param __U3024/// A 16-bit merging mask.3025/// \param __A3026/// A 256-bit vector of [8 x fp16].3027/// \returns3028/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the3029/// (converted) elements from \a __A. If3030/// corresponding mask bit is not set, then element from \a __W is taken instead.3031static __inline__ __m128i __DEFAULT_FN_ATTRS2563032_mm256_mask_cvts_ph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {3033 return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(3034 (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);3035}3036 3037/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements3038/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.3039/// Zeroing mask \a __U is used to determine if given element should be zeroed3040/// instead.3041///3042/// \code{.operation}3043/// FOR i := 0 to 15 3044/// IF __U[i]3045/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])3046/// ELSE3047/// dst.hf8[i] := 03048/// FI3049/// ENDFOR3050///3051/// dst[MAX:128] := 03052/// \endcode3053///3054/// \headerfile <immintrin.h>3055///3056/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.3057///3058/// \param __U3059/// A 16-bit zeroing mask.3060/// \param __A3061/// A 256-bit vector of [16 x fp16].3062/// \returns3063/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the3064/// (converted) elements from \a __A. If corresponding mask bit is not set,3065/// then element is zeroed instead.3066static __inline__ __m128i __DEFAULT_FN_ATTRS2563067_mm256_maskz_cvts_ph_hf8(__mmask16 __U, __m256h __A) {3068 return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(3069 (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);3070}3071 3072/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point3073/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.3074///3075/// \code{.operation}3076/// FOR i := 0 to 73077/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3078/// ENDFOR3079/// \endcode3080///3081/// \headerfile <immintrin.h>3082///3083/// This intrinsic does not correspond to a single instruction.3084///3085/// \param __A3086/// A 128-bit vector of [16 x bf8].3087/// \returns3088/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the3089/// (converted) elements from \a __A.3090static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {3091 return _mm_castsi128_ph(_mm_slli_epi16(_mm_cvtepi8_epi16(__A), 8));3092}3093 3094/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point3095/// elements to a 128-bit vector containing FP16 elements. The conversion is3096/// exact. Merging mask \a __U is used to determine if given element should be3097/// taken from \a __W instead.3098///3099/// \code{.operation}3100/// FOR i := 0 to 73101/// IF __U[i]3102/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3103/// ELSE3104/// dst.fp16[i] := __W.fp16[i]3105/// FI3106/// ENDFOR3107/// \endcode3108///3109/// \headerfile <immintrin.h>3110///3111/// This intrinsic does not correspond to a single instruction.3112///3113/// \param __W3114/// A 128-bit vector of [8 x fp16].3115/// \param __U3116/// A 8-bit merging mask.3117/// \param __A3118/// A 128-bit vector of [16 x bf8].3119/// \returns3120/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the3121/// (converted) elements from \a __A. If corresponding mask bit is not set, then3122/// element from \a __W is taken instead.3123static __inline__ __m128h __DEFAULT_FN_ATTRS1283124_mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {3125 return _mm_castsi128_ph(3126 _mm_mask_slli_epi16((__m128i)__W, __U, _mm_cvtepi8_epi16(__A), 8));3127}3128 3129/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point3130/// elements to a 128-bit vector containing FP16 elements. The conversion is3131/// exact. Zeroing mask \a __U is used to determine if given element should be3132/// zeroed instead.3133///3134/// \code{.operation}3135/// FOR i := 0 to 73136/// IF __U[i]3137/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3138/// ELSE3139/// dst.fp16[i] := 03140/// FI3141/// ENDFOR3142/// \endcode3143///3144/// \headerfile <immintrin.h>3145///3146/// This intrinsic does not correspond to a single instruction.3147///3148/// \param __U3149/// A 8-bit zeroing mask.3150/// \param __A3151/// A 128-bit vector of [16 x bf8].3152/// \returns3153/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the3154/// (converted) elements from \a __A. If corresponding mask bit is not set, then3155/// zero is taken instead.3156static __inline__ __m128h __DEFAULT_FN_ATTRS1283157_mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {3158 return _mm_castsi128_ph(_mm_slli_epi16(_mm_maskz_cvtepi8_epi16(__U, __A), 8));3159}3160 3161/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point3162/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.3163///3164/// \code{.operation}3165/// FOR i := 0 to 153166/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3167/// ENDFOR3168/// \endcode3169///3170/// \headerfile <immintrin.h>3171///3172/// This intrinsic does not correspond to a single instruction.3173///3174/// \param __A3175/// A 256-bit vector of [32 x bf8].3176/// \returns3177/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the3178/// (converted) elements from \a __A.3179static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {3180 return _mm256_castsi256_ph(_mm256_slli_epi16(_mm256_cvtepi8_epi16(__A), 8));3181}3182 3183/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point3184/// elements to a 256-bit vector containing FP16 elements. The conversion is3185/// exact. Merging mask \a __U is used to determine if given element should be3186/// taken from \a __W instead.3187///3188/// \code{.operation}3189/// FOR i := 0 to 15 3190/// IF __U[i]3191/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3192/// ELSE3193/// dst.fp16[i] := __W.fp16[i]3194/// FI3195/// ENDFOR3196/// \endcode3197///3198/// \headerfile <immintrin.h>3199///3200/// This intrinsic does not correspond to a single instruction.3201///3202/// \param __W3203/// A 256-bit vector of [16 x fp16].3204/// \param __U3205/// A 16-bit merging mask.3206/// \param __A3207/// A 256-bit vector of [32 x bf8].3208/// \returns3209/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the3210/// (converted) elements from \a __A. If corresponding mask bit is not set, then3211/// element from \a __W is taken instead.3212static __inline__ __m256h __DEFAULT_FN_ATTRS2563213_mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {3214 return _mm256_castsi256_ph(3215 _mm256_mask_slli_epi16((__m256i)__W, __U, _mm256_cvtepi8_epi16(__A), 8));3216}3217 3218/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point3219/// elements to a 256-bit vector containing FP16 elements. The conversion is3220/// exact. Zeroing mask \a __U is used to determine if given element should be3221/// zeroed instead.3222///3223/// \code{.operation}3224/// FOR i := 0 to 15 3225/// IF __U[i]3226/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])3227/// ELSE3228/// dst.fp16[i] := 03229/// FI3230/// ENDFOR3231/// \endcode3232///3233/// \headerfile <immintrin.h>3234///3235/// This intrinsic does not correspond to a single instruction.3236///3237/// \param __U3238/// A 16-bit zeroing mask.3239/// \param __A3240/// A 256-bit vector of [32 x bf8].3241/// \returns3242/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the3243/// (converted) elements from \a __A. If corresponding mask bit is not set, then3244/// zero is taken instead.3245static __inline__ __m256h __DEFAULT_FN_ATTRS2563246_mm256_maskz_cvtbf8_ph(__mmask16 __U, __m128i __A) {3247 return _mm256_castsi256_ph(3248 _mm256_slli_epi16(_mm256_maskz_cvtepi8_epi16(__U, __A), 8));3249}3250 3251// clang-format on3252 3253#undef __DEFAULT_FN_ATTRS1283254#undef __DEFAULT_FN_ATTRS2563255 3256#endif // __AVX10_2CONVERTINTRIN_H3257#endif // __SSE2__3258