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1/*===---- avx2intrin.h - AVX2 intrinsics -----------------------------------===2 *3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4 * See https://llvm.org/LICENSE.txt for license information.5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6 *7 *===-----------------------------------------------------------------------===8 */9 10#ifndef __IMMINTRIN_H11#error "Never use <avx2intrin.h> directly; include <immintrin.h> instead."12#endif13 14#ifndef __AVX2INTRIN_H15#define __AVX2INTRIN_H16 17/* Define the default attributes for the functions in this file. */18#define __DEFAULT_FN_ATTRS256 \19 __attribute__((__always_inline__, __nodebug__, __target__("avx2"), \20 __min_vector_width__(256)))21#define __DEFAULT_FN_ATTRS128 \22 __attribute__((__always_inline__, __nodebug__, __target__("avx2"), \23 __min_vector_width__(128)))24 25#if defined(__cplusplus) && (__cplusplus >= 201103L)26#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr27#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr28#else29#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS25630#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS12831#endif32 33/* SSE4 Multiple Packed Sums of Absolute Difference. */34/// Computes sixteen sum of absolute difference (SAD) operations on sets of35/// four unsigned 8-bit integers from the 256-bit integer vectors \a X and36/// \a Y.37///38/// Eight SAD results are computed using the lower half of the input39/// vectors, and another eight using the upper half. These 16-bit values40/// are returned in the lower and upper halves of the 256-bit result,41/// respectively.42///43/// A single SAD operation selects four bytes from \a X and four bytes from44/// \a Y as input. It computes the differences between each \a X byte and45/// the corresponding \a Y byte, takes the absolute value of each46/// difference, and sums these four values to form one 16-bit result. The47/// intrinsic computes 16 of these results with different sets of input48/// bytes.49///50/// For each set of eight results, the SAD operations use the same four51/// bytes from \a Y; the starting bit position for these four bytes is52/// specified by \a M[1:0] times 32. The eight operations use successive53/// sets of four bytes from \a X; the starting bit position for the first54/// set of four bytes is specified by \a M[2] times 32. These bit positions55/// are all relative to the 128-bit lane for each set of eight operations.56///57/// \code{.operation}58/// r := 059/// FOR i := 0 TO 160/// j := i*361/// Ybase := M[j+1:j]*32 + i*12862/// Xbase := M[j+2]*32 + i*12863/// FOR k := 0 TO 364/// temp0 := ABS(X[Xbase+7:Xbase] - Y[Ybase+7:Ybase])65/// temp1 := ABS(X[Xbase+15:Xbase+8] - Y[Ybase+15:Ybase+8])66/// temp2 := ABS(X[Xbase+23:Xbase+16] - Y[Ybase+23:Ybase+16])67/// temp3 := ABS(X[Xbase+31:Xbase+24] - Y[Ybase+31:Ybase+24])68/// result[r+15:r] := temp0 + temp1 + temp2 + temp369/// Xbase := Xbase + 870/// r := r + 1671/// ENDFOR72/// ENDFOR73/// \endcode74///75/// \headerfile <immintrin.h>76///77/// \code78/// __m256i _mm256_mpsadbw_epu8(__m256i X, __m256i Y, const int M);79/// \endcode80///81/// This intrinsic corresponds to the \c VMPSADBW instruction.82///83/// \param X84/// A 256-bit integer vector containing one of the inputs.85/// \param Y86/// A 256-bit integer vector containing one of the inputs.87/// \param M88/// An unsigned immediate value specifying the starting positions of the89/// bytes to operate on.90/// \returns A 256-bit vector of [16 x i16] containing the result.91#define _mm256_mpsadbw_epu8(X, Y, M) \92 ((__m256i)__builtin_ia32_mpsadbw256((__v32qi)(__m256i)(X), \93 (__v32qi)(__m256i)(Y), (int)(M)))94 95/// Computes the absolute value of each signed byte in the 256-bit integer96/// vector \a __a and returns each value in the corresponding byte of97/// the result.98///99/// \headerfile <immintrin.h>100///101/// This intrinsic corresponds to the \c VPABSB instruction.102///103/// \param __a104/// A 256-bit integer vector.105/// \returns A 256-bit integer vector containing the result.106static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR107_mm256_abs_epi8(__m256i __a) {108 return (__m256i)__builtin_elementwise_abs((__v32qs)__a);109}110 111/// Computes the absolute value of each signed 16-bit element in the 256-bit112/// vector of [16 x i16] in \a __a and returns each value in the113/// corresponding element of the result.114///115/// \headerfile <immintrin.h>116///117/// This intrinsic corresponds to the \c VPABSW instruction.118///119/// \param __a120/// A 256-bit vector of [16 x i16].121/// \returns A 256-bit vector of [16 x i16] containing the result.122static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR123_mm256_abs_epi16(__m256i __a) {124 return (__m256i)__builtin_elementwise_abs((__v16hi)__a);125}126 127/// Computes the absolute value of each signed 32-bit element in the 256-bit128/// vector of [8 x i32] in \a __a and returns each value in the129/// corresponding element of the result.130///131/// \headerfile <immintrin.h>132///133/// This intrinsic corresponds to the \c VPABSD instruction.134///135/// \param __a136/// A 256-bit vector of [8 x i32].137/// \returns A 256-bit vector of [8 x i32] containing the result.138static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR139_mm256_abs_epi32(__m256i __a) {140 return (__m256i)__builtin_elementwise_abs((__v8si)__a);141}142 143/// Converts the elements of two 256-bit vectors of [16 x i16] to 8-bit144/// integers using signed saturation, and returns the 256-bit result.145///146/// \code{.operation}147/// FOR i := 0 TO 7148/// j := i*16149/// k := i*8150/// result[7+k:k] := SATURATE8(__a[15+j:j])151/// result[71+k:64+k] := SATURATE8(__b[15+j:j])152/// result[135+k:128+k] := SATURATE8(__a[143+j:128+j])153/// result[199+k:192+k] := SATURATE8(__b[143+j:128+j])154/// ENDFOR155/// \endcode156///157/// \headerfile <immintrin.h>158///159/// This intrinsic corresponds to the \c VPACKSSWB instruction.160///161/// \param __a162/// A 256-bit vector of [16 x i16] used to generate result[63:0] and163/// result[191:128].164/// \param __b165/// A 256-bit vector of [16 x i16] used to generate result[127:64] and166/// result[255:192].167/// \returns A 256-bit integer vector containing the result.168static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR169_mm256_packs_epi16(__m256i __a, __m256i __b) {170 return (__m256i)__builtin_ia32_packsswb256((__v16hi)__a, (__v16hi)__b);171}172 173/// Converts the elements of two 256-bit vectors of [8 x i32] to 16-bit174/// integers using signed saturation, and returns the resulting 256-bit175/// vector of [16 x i16].176///177/// \code{.operation}178/// FOR i := 0 TO 3179/// j := i*32180/// k := i*16181/// result[15+k:k] := SATURATE16(__a[31+j:j])182/// result[79+k:64+k] := SATURATE16(__b[31+j:j])183/// result[143+k:128+k] := SATURATE16(__a[159+j:128+j])184/// result[207+k:192+k] := SATURATE16(__b[159+j:128+j])185/// ENDFOR186/// \endcode187///188/// \headerfile <immintrin.h>189///190/// This intrinsic corresponds to the \c VPACKSSDW instruction.191///192/// \param __a193/// A 256-bit vector of [8 x i32] used to generate result[63:0] and194/// result[191:128].195/// \param __b196/// A 256-bit vector of [8 x i32] used to generate result[127:64] and197/// result[255:192].198/// \returns A 256-bit vector of [16 x i16] containing the result.199static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR200_mm256_packs_epi32(__m256i __a, __m256i __b) {201 return (__m256i)__builtin_ia32_packssdw256((__v8si)__a, (__v8si)__b);202}203 204/// Converts elements from two 256-bit vectors of [16 x i16] to 8-bit integers205/// using unsigned saturation, and returns the 256-bit result.206///207/// \code{.operation}208/// FOR i := 0 TO 7209/// j := i*16210/// k := i*8211/// result[7+k:k] := SATURATE8U(__a[15+j:j])212/// result[71+k:64+k] := SATURATE8U(__b[15+j:j])213/// result[135+k:128+k] := SATURATE8U(__a[143+j:128+j])214/// result[199+k:192+k] := SATURATE8U(__b[143+j:128+j])215/// ENDFOR216/// \endcode217///218/// \headerfile <immintrin.h>219///220/// This intrinsic corresponds to the \c VPACKUSWB instruction.221///222/// \param __a223/// A 256-bit vector of [16 x i16] used to generate result[63:0] and224/// result[191:128].225/// \param __b226/// A 256-bit vector of [16 x i16] used to generate result[127:64] and227/// result[255:192].228/// \returns A 256-bit integer vector containing the result.229static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR230_mm256_packus_epi16(__m256i __a, __m256i __b) {231 return (__m256i)__builtin_ia32_packuswb256((__v16hi)__a, (__v16hi)__b);232}233 234/// Converts elements from two 256-bit vectors of [8 x i32] to 16-bit integers235/// using unsigned saturation, and returns the resulting 256-bit vector of236/// [16 x i16].237///238/// \code{.operation}239/// FOR i := 0 TO 3240/// j := i*32241/// k := i*16242/// result[15+k:k] := SATURATE16U(__V1[31+j:j])243/// result[79+k:64+k] := SATURATE16U(__V2[31+j:j])244/// result[143+k:128+k] := SATURATE16U(__V1[159+j:128+j])245/// result[207+k:192+k] := SATURATE16U(__V2[159+j:128+j])246/// ENDFOR247/// \endcode248///249/// \headerfile <immintrin.h>250///251/// This intrinsic corresponds to the \c VPACKUSDW instruction.252///253/// \param __V1254/// A 256-bit vector of [8 x i32] used to generate result[63:0] and255/// result[191:128].256/// \param __V2257/// A 256-bit vector of [8 x i32] used to generate result[127:64] and258/// result[255:192].259/// \returns A 256-bit vector of [16 x i16] containing the result.260static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR261_mm256_packus_epi32(__m256i __V1, __m256i __V2) {262 return (__m256i) __builtin_ia32_packusdw256((__v8si)__V1, (__v8si)__V2);263}264 265/// Adds 8-bit integers from corresponding bytes of two 256-bit integer266/// vectors and returns the lower 8 bits of each sum in the corresponding267/// byte of the 256-bit integer vector result (overflow is ignored).268///269/// \headerfile <immintrin.h>270///271/// This intrinsic corresponds to the \c VPADDB instruction.272///273/// \param __a274/// A 256-bit integer vector containing one of the source operands.275/// \param __b276/// A 256-bit integer vector containing one of the source operands.277/// \returns A 256-bit integer vector containing the sums.278static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR279_mm256_add_epi8(__m256i __a, __m256i __b) {280 return (__m256i)((__v32qu)__a + (__v32qu)__b);281}282 283/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of284/// [16 x i16] and returns the lower 16 bits of each sum in the285/// corresponding element of the [16 x i16] result (overflow is ignored).286///287/// \headerfile <immintrin.h>288///289/// This intrinsic corresponds to the \c VPADDW instruction.290///291/// \param __a292/// A 256-bit vector of [16 x i16] containing one of the source operands.293/// \param __b294/// A 256-bit vector of [16 x i16] containing one of the source operands.295/// \returns A 256-bit vector of [16 x i16] containing the sums.296static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR297_mm256_add_epi16(__m256i __a, __m256i __b) {298 return (__m256i)((__v16hu)__a + (__v16hu)__b);299}300 301/// Adds 32-bit integers from corresponding elements of two 256-bit vectors of302/// [8 x i32] and returns the lower 32 bits of each sum in the corresponding303/// element of the [8 x i32] result (overflow is ignored).304///305/// \headerfile <immintrin.h>306///307/// This intrinsic corresponds to the \c VPADDD instruction.308///309/// \param __a310/// A 256-bit vector of [8 x i32] containing one of the source operands.311/// \param __b312/// A 256-bit vector of [8 x i32] containing one of the source operands.313/// \returns A 256-bit vector of [8 x i32] containing the sums.314static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR315_mm256_add_epi32(__m256i __a, __m256i __b) {316 return (__m256i)((__v8su)__a + (__v8su)__b);317}318 319/// Adds 64-bit integers from corresponding elements of two 256-bit vectors of320/// [4 x i64] and returns the lower 64 bits of each sum in the corresponding321/// element of the [4 x i64] result (overflow is ignored).322///323/// \headerfile <immintrin.h>324///325/// This intrinsic corresponds to the \c VPADDQ instruction.326///327/// \param __a328/// A 256-bit vector of [4 x i64] containing one of the source operands.329/// \param __b330/// A 256-bit vector of [4 x i64] containing one of the source operands.331/// \returns A 256-bit vector of [4 x i64] containing the sums.332static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR333_mm256_add_epi64(__m256i __a, __m256i __b) {334 return (__m256i)((__v4du)__a + (__v4du)__b);335}336 337/// Adds 8-bit integers from corresponding bytes of two 256-bit integer338/// vectors using signed saturation, and returns each sum in the339/// corresponding byte of the 256-bit integer vector result.340///341/// \headerfile <immintrin.h>342///343/// This intrinsic corresponds to the \c VPADDSB instruction.344///345/// \param __a346/// A 256-bit integer vector containing one of the source operands.347/// \param __b348/// A 256-bit integer vector containing one of the source operands.349/// \returns A 256-bit integer vector containing the sums.350static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR351_mm256_adds_epi8(__m256i __a, __m256i __b) {352 return (__m256i)__builtin_elementwise_add_sat((__v32qs)__a, (__v32qs)__b);353}354 355/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of356/// [16 x i16] using signed saturation, and returns the [16 x i16] result.357///358/// \headerfile <immintrin.h>359///360/// This intrinsic corresponds to the \c VPADDSW instruction.361///362/// \param __a363/// A 256-bit vector of [16 x i16] containing one of the source operands.364/// \param __b365/// A 256-bit vector of [16 x i16] containing one of the source operands.366/// \returns A 256-bit vector of [16 x i16] containing the sums.367static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR368_mm256_adds_epi16(__m256i __a, __m256i __b) {369 return (__m256i)__builtin_elementwise_add_sat((__v16hi)__a, (__v16hi)__b);370}371 372/// Adds 8-bit integers from corresponding bytes of two 256-bit integer373/// vectors using unsigned saturation, and returns each sum in the374/// corresponding byte of the 256-bit integer vector result.375///376/// \headerfile <immintrin.h>377///378/// This intrinsic corresponds to the \c VPADDUSB instruction.379///380/// \param __a381/// A 256-bit integer vector containing one of the source operands.382/// \param __b383/// A 256-bit integer vector containing one of the source operands.384/// \returns A 256-bit integer vector containing the sums.385static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR386_mm256_adds_epu8(__m256i __a, __m256i __b) {387 return (__m256i)__builtin_elementwise_add_sat((__v32qu)__a, (__v32qu)__b);388}389 390/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of391/// [16 x i16] using unsigned saturation, and returns the [16 x i16] result.392///393/// \headerfile <immintrin.h>394///395/// This intrinsic corresponds to the \c VPADDUSW instruction.396///397/// \param __a398/// A 256-bit vector of [16 x i16] containing one of the source operands.399/// \param __b400/// A 256-bit vector of [16 x i16] containing one of the source operands.401/// \returns A 256-bit vector of [16 x i16] containing the sums.402static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR403_mm256_adds_epu16(__m256i __a, __m256i __b) {404 return (__m256i)__builtin_elementwise_add_sat((__v16hu)__a, (__v16hu)__b);405}406 407/// Uses the lower half of the 256-bit vector \a a as the upper half of a408/// temporary 256-bit value, and the lower half of the 256-bit vector \a b409/// as the lower half of the temporary value. Right-shifts the temporary410/// value by \a n bytes, and uses the lower 16 bytes of the shifted value411/// as the lower 16 bytes of the result. Uses the upper halves of \a a and412/// \a b to make another temporary value, right shifts by \a n, and uses413/// the lower 16 bytes of the shifted value as the upper 16 bytes of the414/// result.415///416/// \headerfile <immintrin.h>417///418/// \code419/// __m256i _mm256_alignr_epi8(__m256i a, __m256i b, const int n);420/// \endcode421///422/// This intrinsic corresponds to the \c VPALIGNR instruction.423///424/// \param a425/// A 256-bit integer vector containing source values.426/// \param b427/// A 256-bit integer vector containing source values.428/// \param n429/// An immediate value specifying the number of bytes to shift.430/// \returns A 256-bit integer vector containing the result.431#define _mm256_alignr_epi8(a, b, n) \432 ((__m256i)__builtin_ia32_palignr256((__v32qi)(__m256i)(a), \433 (__v32qi)(__m256i)(b), (n)))434 435/// Computes the bitwise AND of the 256-bit integer vectors in \a __a and436/// \a __b.437///438/// \headerfile <immintrin.h>439///440/// This intrinsic corresponds to the \c VPAND instruction.441///442/// \param __a443/// A 256-bit integer vector.444/// \param __b445/// A 256-bit integer vector.446/// \returns A 256-bit integer vector containing the result.447static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR448_mm256_and_si256(__m256i __a, __m256i __b)449{450 return (__m256i)((__v4du)__a & (__v4du)__b);451}452 453/// Computes the bitwise AND of the 256-bit integer vector in \a __b with454/// the bitwise NOT of the 256-bit integer vector in \a __a.455///456/// \headerfile <immintrin.h>457///458/// This intrinsic corresponds to the \c VPANDN instruction.459///460/// \param __a461/// A 256-bit integer vector.462/// \param __b463/// A 256-bit integer vector.464/// \returns A 256-bit integer vector containing the result.465static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR466_mm256_andnot_si256(__m256i __a, __m256i __b)467{468 return (__m256i)(~(__v4du)__a & (__v4du)__b);469}470 471/// Computes the averages of the corresponding unsigned bytes in the two472/// 256-bit integer vectors in \a __a and \a __b and returns each473/// average in the corresponding byte of the 256-bit result.474///475/// \code{.operation}476/// FOR i := 0 TO 31477/// j := i*8478/// result[j+7:j] := (__a[j+7:j] + __b[j+7:j] + 1) >> 1479/// ENDFOR480/// \endcode481///482/// \headerfile <immintrin.h>483///484/// This intrinsic corresponds to the \c VPAVGB instruction.485///486/// \param __a487/// A 256-bit integer vector.488/// \param __b489/// A 256-bit integer vector.490/// \returns A 256-bit integer vector containing the result.491static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR492_mm256_avg_epu8(__m256i __a, __m256i __b) {493 return (__m256i)__builtin_ia32_pavgb256((__v32qu)__a, (__v32qu)__b);494}495 496/// Computes the averages of the corresponding unsigned 16-bit integers in497/// the two 256-bit vectors of [16 x i16] in \a __a and \a __b and returns498/// each average in the corresponding element of the 256-bit result.499///500/// \code{.operation}501/// FOR i := 0 TO 15502/// j := i*16503/// result[j+15:j] := (__a[j+15:j] + __b[j+15:j] + 1) >> 1504/// ENDFOR505/// \endcode506///507/// \headerfile <immintrin.h>508///509/// This intrinsic corresponds to the \c VPAVGW instruction.510///511/// \param __a512/// A 256-bit vector of [16 x i16].513/// \param __b514/// A 256-bit vector of [16 x i16].515/// \returns A 256-bit vector of [16 x i16] containing the result.516static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR517_mm256_avg_epu16(__m256i __a, __m256i __b) {518 return (__m256i)__builtin_ia32_pavgw256((__v16hu)__a, (__v16hu)__b);519}520 521/// Merges 8-bit integer values from either of the two 256-bit vectors522/// \a __V1 or \a __V2, as specified by the 256-bit mask \a __M and returns523/// the resulting 256-bit integer vector.524///525/// \code{.operation}526/// FOR i := 0 TO 31527/// j := i*8528/// IF __M[7+i] == 0529/// result[7+j:j] := __V1[7+j:j]530/// ELSE531/// result[7+j:j] := __V2[7+j:j]532/// FI533/// ENDFOR534/// \endcode535///536/// \headerfile <immintrin.h>537///538/// This intrinsic corresponds to the \c VPBLENDVB instruction.539///540/// \param __V1541/// A 256-bit integer vector containing source values.542/// \param __V2543/// A 256-bit integer vector containing source values.544/// \param __M545/// A 256-bit integer vector, with bit [7] of each byte specifying the546/// source for each corresponding byte of the result. When the mask bit547/// is 0, the byte is copied from \a __V1; otherwise, it is copied from548/// \a __V2.549/// \returns A 256-bit integer vector containing the result.550static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR551_mm256_blendv_epi8(__m256i __V1, __m256i __V2, __m256i __M) {552 return (__m256i)__builtin_ia32_pblendvb256((__v32qi)__V1, (__v32qi)__V2,553 (__v32qi)__M);554}555 556/// Merges 16-bit integer values from either of the two 256-bit vectors557/// \a V1 or \a V2, as specified by the immediate integer operand \a M,558/// and returns the resulting 256-bit vector of [16 x i16].559///560/// \code{.operation}561/// FOR i := 0 TO 7562/// j := i*16563/// IF M[i] == 0564/// result[7+j:j] := V1[7+j:j]565/// result[135+j:128+j] := V1[135+j:128+j]566/// ELSE567/// result[7+j:j] := V2[7+j:j]568/// result[135+j:128+j] := V2[135+j:128+j]569/// FI570/// ENDFOR571/// \endcode572///573/// \headerfile <immintrin.h>574///575/// \code576/// __m256i _mm256_blend_epi16(__m256i V1, __m256i V2, const int M);577/// \endcode578///579/// This intrinsic corresponds to the \c VPBLENDW instruction.580///581/// \param V1582/// A 256-bit vector of [16 x i16] containing source values.583/// \param V2584/// A 256-bit vector of [16 x i16] containing source values.585/// \param M586/// An immediate 8-bit integer operand, with bits [7:0] specifying the587/// source for each element of the result. The position of the mask bit588/// corresponds to the index of a copied value. When a mask bit is 0, the589/// element is copied from \a V1; otherwise, it is copied from \a V2.590/// \a M[0] determines the source for elements 0 and 8, \a M[1] for591/// elements 1 and 9, and so forth.592/// \returns A 256-bit vector of [16 x i16] containing the result.593#define _mm256_blend_epi16(V1, V2, M) \594 ((__m256i)__builtin_ia32_pblendw256((__v16hi)(__m256i)(V1), \595 (__v16hi)(__m256i)(V2), (int)(M)))596 597/// Compares corresponding bytes in the 256-bit integer vectors in \a __a and598/// \a __b for equality and returns the outcomes in the corresponding599/// bytes of the 256-bit result.600///601/// \code{.operation}602/// FOR i := 0 TO 31603/// j := i*8604/// result[j+7:j] := (__a[j+7:j] == __b[j+7:j]) ? 0xFF : 0605/// ENDFOR606/// \endcode607///608/// \headerfile <immintrin.h>609///610/// This intrinsic corresponds to the \c VPCMPEQB instruction.611///612/// \param __a613/// A 256-bit integer vector containing one of the inputs.614/// \param __b615/// A 256-bit integer vector containing one of the inputs.616/// \returns A 256-bit integer vector containing the result.617static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR618_mm256_cmpeq_epi8(__m256i __a, __m256i __b)619{620 return (__m256i)((__v32qi)__a == (__v32qi)__b);621}622 623/// Compares corresponding elements in the 256-bit vectors of [16 x i16] in624/// \a __a and \a __b for equality and returns the outcomes in the625/// corresponding elements of the 256-bit result.626///627/// \code{.operation}628/// FOR i := 0 TO 15629/// j := i*16630/// result[j+15:j] := (__a[j+15:j] == __b[j+15:j]) ? 0xFFFF : 0631/// ENDFOR632/// \endcode633///634/// \headerfile <immintrin.h>635///636/// This intrinsic corresponds to the \c VPCMPEQW instruction.637///638/// \param __a639/// A 256-bit vector of [16 x i16] containing one of the inputs.640/// \param __b641/// A 256-bit vector of [16 x i16] containing one of the inputs.642/// \returns A 256-bit vector of [16 x i16] containing the result.643static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR644_mm256_cmpeq_epi16(__m256i __a, __m256i __b)645{646 return (__m256i)((__v16hi)__a == (__v16hi)__b);647}648 649/// Compares corresponding elements in the 256-bit vectors of [8 x i32] in650/// \a __a and \a __b for equality and returns the outcomes in the651/// corresponding elements of the 256-bit result.652///653/// \code{.operation}654/// FOR i := 0 TO 7655/// j := i*32656/// result[j+31:j] := (__a[j+31:j] == __b[j+31:j]) ? 0xFFFFFFFF : 0657/// ENDFOR658/// \endcode659///660/// \headerfile <immintrin.h>661///662/// This intrinsic corresponds to the \c VPCMPEQD instruction.663///664/// \param __a665/// A 256-bit vector of [8 x i32] containing one of the inputs.666/// \param __b667/// A 256-bit vector of [8 x i32] containing one of the inputs.668/// \returns A 256-bit vector of [8 x i32] containing the result.669static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR670_mm256_cmpeq_epi32(__m256i __a, __m256i __b)671{672 return (__m256i)((__v8si)__a == (__v8si)__b);673}674 675/// Compares corresponding elements in the 256-bit vectors of [4 x i64] in676/// \a __a and \a __b for equality and returns the outcomes in the677/// corresponding elements of the 256-bit result.678///679/// \code{.operation}680/// FOR i := 0 TO 3681/// j := i*64682/// result[j+63:j] := (__a[j+63:j] == __b[j+63:j]) ? 0xFFFFFFFFFFFFFFFF : 0683/// ENDFOR684/// \endcode685///686/// \headerfile <immintrin.h>687///688/// This intrinsic corresponds to the \c VPCMPEQQ instruction.689///690/// \param __a691/// A 256-bit vector of [4 x i64] containing one of the inputs.692/// \param __b693/// A 256-bit vector of [4 x i64] containing one of the inputs.694/// \returns A 256-bit vector of [4 x i64] containing the result.695static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR696_mm256_cmpeq_epi64(__m256i __a, __m256i __b)697{698 return (__m256i)((__v4di)__a == (__v4di)__b);699}700 701/// Compares corresponding signed bytes in the 256-bit integer vectors in702/// \a __a and \a __b for greater-than and returns the outcomes in the703/// corresponding bytes of the 256-bit result.704///705/// \code{.operation}706/// FOR i := 0 TO 31707/// j := i*8708/// result[j+7:j] := (__a[j+7:j] > __b[j+7:j]) ? 0xFF : 0709/// ENDFOR710/// \endcode711///712/// \headerfile <immintrin.h>713///714/// This intrinsic corresponds to the \c VPCMPGTB instruction.715///716/// \param __a717/// A 256-bit integer vector containing one of the inputs.718/// \param __b719/// A 256-bit integer vector containing one of the inputs.720/// \returns A 256-bit integer vector containing the result.721static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR722_mm256_cmpgt_epi8(__m256i __a, __m256i __b)723{724 /* This function always performs a signed comparison, but __v32qi is a char725 which may be signed or unsigned, so use __v32qs. */726 return (__m256i)((__v32qs)__a > (__v32qs)__b);727}728 729/// Compares corresponding signed elements in the 256-bit vectors of730/// [16 x i16] in \a __a and \a __b for greater-than and returns the731/// outcomes in the corresponding elements of the 256-bit result.732///733/// \code{.operation}734/// FOR i := 0 TO 15735/// j := i*16736/// result[j+15:j] := (__a[j+15:j] > __b[j+15:j]) ? 0xFFFF : 0737/// ENDFOR738/// \endcode739///740/// \headerfile <immintrin.h>741///742/// This intrinsic corresponds to the \c VPCMPGTW instruction.743///744/// \param __a745/// A 256-bit vector of [16 x i16] containing one of the inputs.746/// \param __b747/// A 256-bit vector of [16 x i16] containing one of the inputs.748/// \returns A 256-bit vector of [16 x i16] containing the result.749static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR750_mm256_cmpgt_epi16(__m256i __a, __m256i __b)751{752 return (__m256i)((__v16hi)__a > (__v16hi)__b);753}754 755/// Compares corresponding signed elements in the 256-bit vectors of756/// [8 x i32] in \a __a and \a __b for greater-than and returns the757/// outcomes in the corresponding elements of the 256-bit result.758///759/// \code{.operation}760/// FOR i := 0 TO 7761/// j := i*32762/// result[j+31:j] := (__a[j+31:j] > __b[j+31:j]) ? 0xFFFFFFFF : 0763/// ENDFOR764/// \endcode765///766/// \headerfile <immintrin.h>767///768/// This intrinsic corresponds to the \c VPCMPGTD instruction.769///770/// \param __a771/// A 256-bit vector of [8 x i32] containing one of the inputs.772/// \param __b773/// A 256-bit vector of [8 x i32] containing one of the inputs.774/// \returns A 256-bit vector of [8 x i32] containing the result.775static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR776_mm256_cmpgt_epi32(__m256i __a, __m256i __b)777{778 return (__m256i)((__v8si)__a > (__v8si)__b);779}780 781/// Compares corresponding signed elements in the 256-bit vectors of782/// [4 x i64] in \a __a and \a __b for greater-than and returns the783/// outcomes in the corresponding elements of the 256-bit result.784///785/// \code{.operation}786/// FOR i := 0 TO 3787/// j := i*64788/// result[j+63:j] := (__a[j+63:j] > __b[j+63:j]) ? 0xFFFFFFFFFFFFFFFF : 0789/// ENDFOR790/// \endcode791///792/// \headerfile <immintrin.h>793///794/// This intrinsic corresponds to the \c VPCMPGTQ instruction.795///796/// \param __a797/// A 256-bit vector of [4 x i64] containing one of the inputs.798/// \param __b799/// A 256-bit vector of [4 x i64] containing one of the inputs.800/// \returns A 256-bit vector of [4 x i64] containing the result.801static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR802_mm256_cmpgt_epi64(__m256i __a, __m256i __b)803{804 return (__m256i)((__v4di)__a > (__v4di)__b);805}806 807/// Horizontally adds the adjacent pairs of 16-bit integers from two 256-bit808/// vectors of [16 x i16] and returns the lower 16 bits of each sum in an809/// element of the [16 x i16] result (overflow is ignored). Sums from810/// \a __a are returned in the lower 64 bits of each 128-bit half of the811/// result; sums from \a __b are returned in the upper 64 bits of each812/// 128-bit half of the result.813///814/// \code{.operation}815/// FOR i := 0 TO 1816/// j := i*128817/// result[j+15:j] := __a[j+15:j] + __a[j+31:j+16]818/// result[j+31:j+16] := __a[j+47:j+32] + __a[j+63:j+48]819/// result[j+47:j+32] := __a[j+79:j+64] + __a[j+95:j+80]820/// result[j+63:j+48] := __a[j+111:j+96] + __a[j+127:j+112]821/// result[j+79:j+64] := __b[j+15:j] + __b[j+31:j+16]822/// result[j+95:j+80] := __b[j+47:j+32] + __b[j+63:j+48]823/// result[j+111:j+96] := __b[j+79:j+64] + __b[j+95:j+80]824/// result[j+127:j+112] := __b[j+111:j+96] + __b[j+127:j+112]825/// ENDFOR826/// \endcode827///828/// \headerfile <immintrin.h>829///830/// This intrinsic corresponds to the \c VPHADDW instruction.831///832/// \param __a833/// A 256-bit vector of [16 x i16] containing one of the source operands.834/// \param __b835/// A 256-bit vector of [16 x i16] containing one of the source operands.836/// \returns A 256-bit vector of [16 x i16] containing the sums.837static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR838_mm256_hadd_epi16(__m256i __a, __m256i __b) {839 return (__m256i)__builtin_ia32_phaddw256((__v16hi)__a, (__v16hi)__b);840}841 842/// Horizontally adds the adjacent pairs of 32-bit integers from two 256-bit843/// vectors of [8 x i32] and returns the lower 32 bits of each sum in an844/// element of the [8 x i32] result (overflow is ignored). Sums from \a __a845/// are returned in the lower 64 bits of each 128-bit half of the result;846/// sums from \a __b are returned in the upper 64 bits of each 128-bit half847/// of the result.848///849/// \code{.operation}850/// FOR i := 0 TO 1851/// j := i*128852/// result[j+31:j] := __a[j+31:j] + __a[j+63:j+32]853/// result[j+63:j+32] := __a[j+95:j+64] + __a[j+127:j+96]854/// result[j+95:j+64] := __b[j+31:j] + __b[j+63:j+32]855/// result[j+127:j+96] := __b[j+95:j+64] + __b[j+127:j+96]856/// ENDFOR857/// \endcode858///859/// \headerfile <immintrin.h>860///861/// This intrinsic corresponds to the \c VPHADDD instruction.862///863/// \param __a864/// A 256-bit vector of [8 x i32] containing one of the source operands.865/// \param __b866/// A 256-bit vector of [8 x i32] containing one of the source operands.867/// \returns A 256-bit vector of [8 x i32] containing the sums.868static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR869_mm256_hadd_epi32(__m256i __a, __m256i __b) {870 return (__m256i)__builtin_ia32_phaddd256((__v8si)__a, (__v8si)__b);871}872 873/// Horizontally adds the adjacent pairs of 16-bit integers from two 256-bit874/// vectors of [16 x i16] using signed saturation and returns each sum in875/// an element of the [16 x i16] result. Sums from \a __a are returned in876/// the lower 64 bits of each 128-bit half of the result; sums from \a __b877/// are returned in the upper 64 bits of each 128-bit half of the result.878///879/// \code{.operation}880/// FOR i := 0 TO 1881/// j := i*128882/// result[j+15:j] := SATURATE16(__a[j+15:j] + __a[j+31:j+16])883/// result[j+31:j+16] := SATURATE16(__a[j+47:j+32] + __a[j+63:j+48])884/// result[j+47:j+32] := SATURATE16(__a[j+79:j+64] + __a[j+95:j+80])885/// result[j+63:j+48] := SATURATE16(__a[j+111:j+96] + __a[j+127:j+112])886/// result[j+79:j+64] := SATURATE16(__b[j+15:j] + __b[j+31:j+16])887/// result[j+95:j+80] := SATURATE16(__b[j+47:j+32] + __b[j+63:j+48])888/// result[j+111:j+96] := SATURATE16(__b[j+79:j+64] + __b[j+95:j+80])889/// result[j+127:j+112] := SATURATE16(__b[j+111:j+96] + __b[j+127:j+112])890/// ENDFOR891/// \endcode892///893/// \headerfile <immintrin.h>894///895/// This intrinsic corresponds to the \c VPHADDSW instruction.896///897/// \param __a898/// A 256-bit vector of [16 x i16] containing one of the source operands.899/// \param __b900/// A 256-bit vector of [16 x i16] containing one of the source operands.901/// \returns A 256-bit vector of [16 x i16] containing the sums.902static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR903_mm256_hadds_epi16(__m256i __a, __m256i __b) {904 return (__m256i)__builtin_ia32_phaddsw256((__v16hi)__a, (__v16hi)__b);905}906 907/// Horizontally subtracts adjacent pairs of 16-bit integers from two 256-bit908/// vectors of [16 x i16] and returns the lower 16 bits of each difference909/// in an element of the [16 x i16] result (overflow is ignored).910/// Differences from \a __a are returned in the lower 64 bits of each911/// 128-bit half of the result; differences from \a __b are returned in the912/// upper 64 bits of each 128-bit half of the result.913///914/// \code{.operation}915/// FOR i := 0 TO 1916/// j := i*128917/// result[j+15:j] := __a[j+15:j] - __a[j+31:j+16]918/// result[j+31:j+16] := __a[j+47:j+32] - __a[j+63:j+48]919/// result[j+47:j+32] := __a[j+79:j+64] - __a[j+95:j+80]920/// result[j+63:j+48] := __a[j+111:j+96] - __a[j+127:j+112]921/// result[j+79:j+64] := __b[j+15:j] - __b[j+31:j+16]922/// result[j+95:j+80] := __b[j+47:j+32] - __b[j+63:j+48]923/// result[j+111:j+96] := __b[j+79:j+64] - __b[j+95:j+80]924/// result[j+127:j+112] := __b[j+111:j+96] - __b[j+127:j+112]925/// ENDFOR926/// \endcode927///928/// \headerfile <immintrin.h>929///930/// This intrinsic corresponds to the \c VPHSUBW instruction.931///932/// \param __a933/// A 256-bit vector of [16 x i16] containing one of the source operands.934/// \param __b935/// A 256-bit vector of [16 x i16] containing one of the source operands.936/// \returns A 256-bit vector of [16 x i16] containing the differences.937static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR938_mm256_hsub_epi16(__m256i __a, __m256i __b) {939 return (__m256i)__builtin_ia32_phsubw256((__v16hi)__a, (__v16hi)__b);940}941 942/// Horizontally subtracts adjacent pairs of 32-bit integers from two 256-bit943/// vectors of [8 x i32] and returns the lower 32 bits of each difference in944/// an element of the [8 x i32] result (overflow is ignored). Differences945/// from \a __a are returned in the lower 64 bits of each 128-bit half of946/// the result; differences from \a __b are returned in the upper 64 bits947/// of each 128-bit half of the result.948///949/// \code{.operation}950/// FOR i := 0 TO 1951/// j := i*128952/// result[j+31:j] := __a[j+31:j] - __a[j+63:j+32]953/// result[j+63:j+32] := __a[j+95:j+64] - __a[j+127:j+96]954/// result[j+95:j+64] := __b[j+31:j] - __b[j+63:j+32]955/// result[j+127:j+96] := __b[j+95:j+64] - __b[j+127:j+96]956/// ENDFOR957/// \endcode958///959/// \headerfile <immintrin.h>960///961/// This intrinsic corresponds to the \c VPHSUBD instruction.962///963/// \param __a964/// A 256-bit vector of [8 x i32] containing one of the source operands.965/// \param __b966/// A 256-bit vector of [8 x i32] containing one of the source operands.967/// \returns A 256-bit vector of [8 x i32] containing the differences.968static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR969_mm256_hsub_epi32(__m256i __a, __m256i __b) {970 return (__m256i)__builtin_ia32_phsubd256((__v8si)__a, (__v8si)__b);971}972 973/// Horizontally subtracts adjacent pairs of 16-bit integers from two 256-bit974/// vectors of [16 x i16] using signed saturation and returns each sum in975/// an element of the [16 x i16] result. Differences from \a __a are976/// returned in the lower 64 bits of each 128-bit half of the result;977/// differences from \a __b are returned in the upper 64 bits of each978/// 128-bit half of the result.979///980/// \code{.operation}981/// FOR i := 0 TO 1982/// j := i*128983/// result[j+15:j] := SATURATE16(__a[j+15:j] - __a[j+31:j+16])984/// result[j+31:j+16] := SATURATE16(__a[j+47:j+32] - __a[j+63:j+48])985/// result[j+47:j+32] := SATURATE16(__a[j+79:j+64] - __a[j+95:j+80])986/// result[j+63:j+48] := SATURATE16(__a[j+111:j+96] - __a[j+127:j+112])987/// result[j+79:j+64] := SATURATE16(__b[j+15:j] - __b[j+31:j+16])988/// result[j+95:j+80] := SATURATE16(__b[j+47:j+32] - __b[j+63:j+48])989/// result[j+111:j+96] := SATURATE16(__b[j+79:j+64] - __b[j+95:j+80])990/// result[j+127:j+112] := SATURATE16(__b[j+111:j+96] - __b[j+127:j+112])991/// ENDFOR992/// \endcode993///994/// \headerfile <immintrin.h>995///996/// This intrinsic corresponds to the \c VPHSUBSW instruction.997///998/// \param __a999/// A 256-bit vector of [16 x i16] containing one of the source operands.1000/// \param __b1001/// A 256-bit vector of [16 x i16] containing one of the source operands.1002/// \returns A 256-bit vector of [16 x i16] containing the differences.1003static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1004_mm256_hsubs_epi16(__m256i __a, __m256i __b) {1005 return (__m256i)__builtin_ia32_phsubsw256((__v16hi)__a, (__v16hi)__b);1006}1007 1008/// Multiplies each unsigned byte from the 256-bit integer vector in \a __a1009/// with the corresponding signed byte from the 256-bit integer vector in1010/// \a __b, forming signed 16-bit intermediate products. Adds adjacent1011/// pairs of those products using signed saturation to form 16-bit sums1012/// returned as elements of the [16 x i16] result.1013///1014/// \code{.operation}1015/// FOR i := 0 TO 151016/// j := i*161017/// temp1 := __a[j+7:j] * __b[j+7:j]1018/// temp2 := __a[j+15:j+8] * __b[j+15:j+8]1019/// result[j+15:j] := SATURATE16(temp1 + temp2)1020/// ENDFOR1021/// \endcode1022///1023/// \headerfile <immintrin.h>1024///1025/// This intrinsic corresponds to the \c VPMADDUBSW instruction.1026///1027/// \param __a1028/// A 256-bit vector containing one of the source operands.1029/// \param __b1030/// A 256-bit vector containing one of the source operands.1031/// \returns A 256-bit vector of [16 x i16] containing the result.1032static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1033_mm256_maddubs_epi16(__m256i __a, __m256i __b) {1034 return (__m256i)__builtin_ia32_pmaddubsw256((__v32qi)__a, (__v32qi)__b);1035}1036 1037/// Multiplies corresponding 16-bit elements of two 256-bit vectors of1038/// [16 x i16], forming 32-bit intermediate products, and adds pairs of1039/// those products to form 32-bit sums returned as elements of the1040/// [8 x i32] result.1041///1042/// There is only one wraparound case: when all four of the 16-bit sources1043/// are \c 0x8000, the result will be \c 0x80000000.1044///1045/// \code{.operation}1046/// FOR i := 0 TO 71047/// j := i*321048/// temp1 := __a[j+15:j] * __b[j+15:j]1049/// temp2 := __a[j+31:j+16] * __b[j+31:j+16]1050/// result[j+31:j] := temp1 + temp21051/// ENDFOR1052/// \endcode1053///1054/// \headerfile <immintrin.h>1055///1056/// This intrinsic corresponds to the \c VPMADDWD instruction.1057///1058/// \param __a1059/// A 256-bit vector of [16 x i16] containing one of the source operands.1060/// \param __b1061/// A 256-bit vector of [16 x i16] containing one of the source operands.1062/// \returns A 256-bit vector of [8 x i32] containing the result.1063static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1064_mm256_madd_epi16(__m256i __a, __m256i __b) {1065 return (__m256i)__builtin_ia32_pmaddwd256((__v16hi)__a, (__v16hi)__b);1066}1067 1068/// Compares the corresponding signed bytes in the two 256-bit integer vectors1069/// in \a __a and \a __b and returns the larger of each pair in the1070/// corresponding byte of the 256-bit result.1071///1072/// \headerfile <immintrin.h>1073///1074/// This intrinsic corresponds to the \c VPMAXSB instruction.1075///1076/// \param __a1077/// A 256-bit integer vector.1078/// \param __b1079/// A 256-bit integer vector.1080/// \returns A 256-bit integer vector containing the result.1081static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1082_mm256_max_epi8(__m256i __a, __m256i __b) {1083 return (__m256i)__builtin_elementwise_max((__v32qs)__a, (__v32qs)__b);1084}1085 1086/// Compares the corresponding signed 16-bit integers in the two 256-bit1087/// vectors of [16 x i16] in \a __a and \a __b and returns the larger of1088/// each pair in the corresponding element of the 256-bit result.1089///1090/// \headerfile <immintrin.h>1091///1092/// This intrinsic corresponds to the \c VPMAXSW instruction.1093///1094/// \param __a1095/// A 256-bit vector of [16 x i16].1096/// \param __b1097/// A 256-bit vector of [16 x i16].1098/// \returns A 256-bit vector of [16 x i16] containing the result.1099static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1100_mm256_max_epi16(__m256i __a, __m256i __b) {1101 return (__m256i)__builtin_elementwise_max((__v16hi)__a, (__v16hi)__b);1102}1103 1104/// Compares the corresponding signed 32-bit integers in the two 256-bit1105/// vectors of [8 x i32] in \a __a and \a __b and returns the larger of1106/// each pair in the corresponding element of the 256-bit result.1107///1108/// \headerfile <immintrin.h>1109///1110/// This intrinsic corresponds to the \c VPMAXSD instruction.1111///1112/// \param __a1113/// A 256-bit vector of [8 x i32].1114/// \param __b1115/// A 256-bit vector of [8 x i32].1116/// \returns A 256-bit vector of [8 x i32] containing the result.1117static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1118_mm256_max_epi32(__m256i __a, __m256i __b) {1119 return (__m256i)__builtin_elementwise_max((__v8si)__a, (__v8si)__b);1120}1121 1122/// Compares the corresponding unsigned bytes in the two 256-bit integer1123/// vectors in \a __a and \a __b and returns the larger of each pair in1124/// the corresponding byte of the 256-bit result.1125///1126/// \headerfile <immintrin.h>1127///1128/// This intrinsic corresponds to the \c VPMAXUB instruction.1129///1130/// \param __a1131/// A 256-bit integer vector.1132/// \param __b1133/// A 256-bit integer vector.1134/// \returns A 256-bit integer vector containing the result.1135static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1136_mm256_max_epu8(__m256i __a, __m256i __b) {1137 return (__m256i)__builtin_elementwise_max((__v32qu)__a, (__v32qu)__b);1138}1139 1140/// Compares the corresponding unsigned 16-bit integers in the two 256-bit1141/// vectors of [16 x i16] in \a __a and \a __b and returns the larger of1142/// each pair in the corresponding element of the 256-bit result.1143///1144/// \headerfile <immintrin.h>1145///1146/// This intrinsic corresponds to the \c VPMAXUW instruction.1147///1148/// \param __a1149/// A 256-bit vector of [16 x i16].1150/// \param __b1151/// A 256-bit vector of [16 x i16].1152/// \returns A 256-bit vector of [16 x i16] containing the result.1153static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1154_mm256_max_epu16(__m256i __a, __m256i __b) {1155 return (__m256i)__builtin_elementwise_max((__v16hu)__a, (__v16hu)__b);1156}1157 1158/// Compares the corresponding unsigned 32-bit integers in the two 256-bit1159/// vectors of [8 x i32] in \a __a and \a __b and returns the larger of1160/// each pair in the corresponding element of the 256-bit result.1161///1162/// \headerfile <immintrin.h>1163///1164/// This intrinsic corresponds to the \c VPMAXUD instruction.1165///1166/// \param __a1167/// A 256-bit vector of [8 x i32].1168/// \param __b1169/// A 256-bit vector of [8 x i32].1170/// \returns A 256-bit vector of [8 x i32] containing the result.1171static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1172_mm256_max_epu32(__m256i __a, __m256i __b) {1173 return (__m256i)__builtin_elementwise_max((__v8su)__a, (__v8su)__b);1174}1175 1176/// Compares the corresponding signed bytes in the two 256-bit integer vectors1177/// in \a __a and \a __b and returns the smaller of each pair in the1178/// corresponding byte of the 256-bit result.1179///1180/// \headerfile <immintrin.h>1181///1182/// This intrinsic corresponds to the \c VPMINSB instruction.1183///1184/// \param __a1185/// A 256-bit integer vector.1186/// \param __b1187/// A 256-bit integer vector.1188/// \returns A 256-bit integer vector containing the result.1189static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1190_mm256_min_epi8(__m256i __a, __m256i __b) {1191 return (__m256i)__builtin_elementwise_min((__v32qs)__a, (__v32qs)__b);1192}1193 1194/// Compares the corresponding signed 16-bit integers in the two 256-bit1195/// vectors of [16 x i16] in \a __a and \a __b and returns the smaller of1196/// each pair in the corresponding element of the 256-bit result.1197///1198/// \headerfile <immintrin.h>1199///1200/// This intrinsic corresponds to the \c VPMINSW instruction.1201///1202/// \param __a1203/// A 256-bit vector of [16 x i16].1204/// \param __b1205/// A 256-bit vector of [16 x i16].1206/// \returns A 256-bit vector of [16 x i16] containing the result.1207static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1208_mm256_min_epi16(__m256i __a, __m256i __b) {1209 return (__m256i)__builtin_elementwise_min((__v16hi)__a, (__v16hi)__b);1210}1211 1212/// Compares the corresponding signed 32-bit integers in the two 256-bit1213/// vectors of [8 x i32] in \a __a and \a __b and returns the smaller of1214/// each pair in the corresponding element of the 256-bit result.1215///1216/// \headerfile <immintrin.h>1217///1218/// This intrinsic corresponds to the \c VPMINSD instruction.1219///1220/// \param __a1221/// A 256-bit vector of [8 x i32].1222/// \param __b1223/// A 256-bit vector of [8 x i32].1224/// \returns A 256-bit vector of [8 x i32] containing the result.1225static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1226_mm256_min_epi32(__m256i __a, __m256i __b) {1227 return (__m256i)__builtin_elementwise_min((__v8si)__a, (__v8si)__b);1228}1229 1230/// Compares the corresponding unsigned bytes in the two 256-bit integer1231/// vectors in \a __a and \a __b and returns the smaller of each pair in1232/// the corresponding byte of the 256-bit result.1233///1234/// \headerfile <immintrin.h>1235///1236/// This intrinsic corresponds to the \c VPMINUB instruction.1237///1238/// \param __a1239/// A 256-bit integer vector.1240/// \param __b1241/// A 256-bit integer vector.1242/// \returns A 256-bit integer vector containing the result.1243static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1244_mm256_min_epu8(__m256i __a, __m256i __b) {1245 return (__m256i)__builtin_elementwise_min((__v32qu)__a, (__v32qu)__b);1246}1247 1248/// Compares the corresponding unsigned 16-bit integers in the two 256-bit1249/// vectors of [16 x i16] in \a __a and \a __b and returns the smaller of1250/// each pair in the corresponding element of the 256-bit result.1251///1252/// \headerfile <immintrin.h>1253///1254/// This intrinsic corresponds to the \c VPMINUW instruction.1255///1256/// \param __a1257/// A 256-bit vector of [16 x i16].1258/// \param __b1259/// A 256-bit vector of [16 x i16].1260/// \returns A 256-bit vector of [16 x i16] containing the result.1261static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1262_mm256_min_epu16(__m256i __a, __m256i __b) {1263 return (__m256i)__builtin_elementwise_min((__v16hu)__a, (__v16hu)__b);1264}1265 1266/// Compares the corresponding unsigned 32-bit integers in the two 256-bit1267/// vectors of [8 x i32] in \a __a and \a __b and returns the smaller of1268/// each pair in the corresponding element of the 256-bit result.1269///1270/// \headerfile <immintrin.h>1271///1272/// This intrinsic corresponds to the \c VPMINUD instruction.1273///1274/// \param __a1275/// A 256-bit vector of [8 x i32].1276/// \param __b1277/// A 256-bit vector of [8 x i32].1278/// \returns A 256-bit vector of [8 x i32] containing the result.1279static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1280_mm256_min_epu32(__m256i __a, __m256i __b) {1281 return (__m256i)__builtin_elementwise_min((__v8su)__a, (__v8su)__b);1282}1283 1284/// Creates a 32-bit integer mask from the most significant bit of each byte1285/// in the 256-bit integer vector in \a __a and returns the result.1286///1287/// \code{.operation}1288/// FOR i := 0 TO 311289/// j := i*81290/// result[i] := __a[j+7]1291/// ENDFOR1292/// \endcode1293///1294/// \headerfile <immintrin.h>1295///1296/// This intrinsic corresponds to the \c VPMOVMSKB instruction.1297///1298/// \param __a1299/// A 256-bit integer vector containing the source bytes.1300/// \returns The 32-bit integer mask.1301static __inline__ int __DEFAULT_FN_ATTRS256_CONSTEXPR1302_mm256_movemask_epi8(__m256i __a) {1303 return __builtin_ia32_pmovmskb256((__v32qi)__a);1304}1305 1306/// Sign-extends bytes from the 128-bit integer vector in \a __V and returns1307/// the 16-bit values in the corresponding elements of a 256-bit vector1308/// of [16 x i16].1309///1310/// \code{.operation}1311/// FOR i := 0 TO 151312/// j := i*81313/// k := i*161314/// result[k+15:k] := SignExtend(__V[j+7:j])1315/// ENDFOR1316/// \endcode1317///1318/// \headerfile <immintrin.h>1319///1320/// This intrinsic corresponds to the \c VPMOVSXBW instruction.1321///1322/// \param __V1323/// A 128-bit integer vector containing the source bytes.1324/// \returns A 256-bit vector of [16 x i16] containing the sign-extended1325/// values.1326static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1327_mm256_cvtepi8_epi16(__m128i __V) {1328 /* This function always performs a signed extension, but __v16qi is a char1329 which may be signed or unsigned, so use __v16qs. */1330 return (__m256i)__builtin_convertvector((__v16qs)__V, __v16hi);1331}1332 1333/// Sign-extends bytes from the lower half of the 128-bit integer vector in1334/// \a __V and returns the 32-bit values in the corresponding elements of a1335/// 256-bit vector of [8 x i32].1336///1337/// \code{.operation}1338/// FOR i := 0 TO 71339/// j := i*81340/// k := i*321341/// result[k+31:k] := SignExtend(__V[j+7:j])1342/// ENDFOR1343/// \endcode1344///1345/// \headerfile <immintrin.h>1346///1347/// This intrinsic corresponds to the \c VPMOVSXBD instruction.1348///1349/// \param __V1350/// A 128-bit integer vector containing the source bytes.1351/// \returns A 256-bit vector of [8 x i32] containing the sign-extended1352/// values.1353static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1354_mm256_cvtepi8_epi32(__m128i __V) {1355 /* This function always performs a signed extension, but __v16qi is a char1356 which may be signed or unsigned, so use __v16qs. */1357 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v16qs)__V, (__v16qs)__V, 0, 1, 2, 3, 4, 5, 6, 7), __v8si);1358}1359 1360/// Sign-extends the first four bytes from the 128-bit integer vector in1361/// \a __V and returns the 64-bit values in the corresponding elements of a1362/// 256-bit vector of [4 x i64].1363///1364/// \code{.operation}1365/// result[63:0] := SignExtend(__V[7:0])1366/// result[127:64] := SignExtend(__V[15:8])1367/// result[191:128] := SignExtend(__V[23:16])1368/// result[255:192] := SignExtend(__V[31:24])1369/// \endcode1370///1371/// \headerfile <immintrin.h>1372///1373/// This intrinsic corresponds to the \c VPMOVSXBQ instruction.1374///1375/// \param __V1376/// A 128-bit integer vector containing the source bytes.1377/// \returns A 256-bit vector of [4 x i64] containing the sign-extended1378/// values.1379static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1380_mm256_cvtepi8_epi64(__m128i __V) {1381 /* This function always performs a signed extension, but __v16qi is a char1382 which may be signed or unsigned, so use __v16qs. */1383 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v16qs)__V, (__v16qs)__V, 0, 1, 2, 3), __v4di);1384}1385 1386/// Sign-extends 16-bit elements from the 128-bit vector of [8 x i16] in1387/// \a __V and returns the 32-bit values in the corresponding elements of a1388/// 256-bit vector of [8 x i32].1389///1390/// \code{.operation}1391/// FOR i := 0 TO 71392/// j := i*161393/// k := i*321394/// result[k+31:k] := SignExtend(__V[j+15:j])1395/// ENDFOR1396/// \endcode1397///1398/// \headerfile <immintrin.h>1399///1400/// This intrinsic corresponds to the \c VPMOVSXWD instruction.1401///1402/// \param __V1403/// A 128-bit vector of [8 x i16] containing the source values.1404/// \returns A 256-bit vector of [8 x i32] containing the sign-extended1405/// values.1406static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1407_mm256_cvtepi16_epi32(__m128i __V) {1408 return (__m256i)__builtin_convertvector((__v8hi)__V, __v8si);1409}1410 1411/// Sign-extends 16-bit elements from the lower half of the 128-bit vector of1412/// [8 x i16] in \a __V and returns the 64-bit values in the corresponding1413/// elements of a 256-bit vector of [4 x i64].1414///1415/// \code{.operation}1416/// result[63:0] := SignExtend(__V[15:0])1417/// result[127:64] := SignExtend(__V[31:16])1418/// result[191:128] := SignExtend(__V[47:32])1419/// result[255:192] := SignExtend(__V[64:48])1420/// \endcode1421///1422/// \headerfile <immintrin.h>1423///1424/// This intrinsic corresponds to the \c VPMOVSXWQ instruction.1425///1426/// \param __V1427/// A 128-bit vector of [8 x i16] containing the source values.1428/// \returns A 256-bit vector of [4 x i64] containing the sign-extended1429/// values.1430static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1431_mm256_cvtepi16_epi64(__m128i __V) {1432 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v8hi)__V, (__v8hi)__V, 0, 1, 2, 3), __v4di);1433}1434 1435/// Sign-extends 32-bit elements from the 128-bit vector of [4 x i32] in1436/// \a __V and returns the 64-bit values in the corresponding elements of a1437/// 256-bit vector of [4 x i64].1438///1439/// \code{.operation}1440/// result[63:0] := SignExtend(__V[31:0])1441/// result[127:64] := SignExtend(__V[63:32])1442/// result[191:128] := SignExtend(__V[95:64])1443/// result[255:192] := SignExtend(__V[127:96])1444/// \endcode1445///1446/// \headerfile <immintrin.h>1447///1448/// This intrinsic corresponds to the \c VPMOVSXDQ instruction.1449///1450/// \param __V1451/// A 128-bit vector of [4 x i32] containing the source values.1452/// \returns A 256-bit vector of [4 x i64] containing the sign-extended1453/// values.1454static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1455_mm256_cvtepi32_epi64(__m128i __V) {1456 return (__m256i)__builtin_convertvector((__v4si)__V, __v4di);1457}1458 1459/// Zero-extends bytes from the 128-bit integer vector in \a __V and returns1460/// the 16-bit values in the corresponding elements of a 256-bit vector1461/// of [16 x i16].1462///1463/// \code{.operation}1464/// FOR i := 0 TO 151465/// j := i*81466/// k := i*161467/// result[k+15:k] := ZeroExtend(__V[j+7:j])1468/// ENDFOR1469/// \endcode1470///1471/// \headerfile <immintrin.h>1472///1473/// This intrinsic corresponds to the \c VPMOVZXBW instruction.1474///1475/// \param __V1476/// A 128-bit integer vector containing the source bytes.1477/// \returns A 256-bit vector of [16 x i16] containing the zero-extended1478/// values.1479static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1480_mm256_cvtepu8_epi16(__m128i __V) {1481 return (__m256i)__builtin_convertvector((__v16qu)__V, __v16hi);1482}1483 1484/// Zero-extends bytes from the lower half of the 128-bit integer vector in1485/// \a __V and returns the 32-bit values in the corresponding elements of a1486/// 256-bit vector of [8 x i32].1487///1488/// \code{.operation}1489/// FOR i := 0 TO 71490/// j := i*81491/// k := i*321492/// result[k+31:k] := ZeroExtend(__V[j+7:j])1493/// ENDFOR1494/// \endcode1495///1496/// \headerfile <immintrin.h>1497///1498/// This intrinsic corresponds to the \c VPMOVZXBD instruction.1499///1500/// \param __V1501/// A 128-bit integer vector containing the source bytes.1502/// \returns A 256-bit vector of [8 x i32] containing the zero-extended1503/// values.1504static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1505_mm256_cvtepu8_epi32(__m128i __V) {1506 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v16qu)__V, (__v16qu)__V, 0, 1, 2, 3, 4, 5, 6, 7), __v8si);1507}1508 1509/// Zero-extends the first four bytes from the 128-bit integer vector in1510/// \a __V and returns the 64-bit values in the corresponding elements of a1511/// 256-bit vector of [4 x i64].1512///1513/// \code{.operation}1514/// result[63:0] := ZeroExtend(__V[7:0])1515/// result[127:64] := ZeroExtend(__V[15:8])1516/// result[191:128] := ZeroExtend(__V[23:16])1517/// result[255:192] := ZeroExtend(__V[31:24])1518/// \endcode1519///1520/// \headerfile <immintrin.h>1521///1522/// This intrinsic corresponds to the \c VPMOVZXBQ instruction.1523///1524/// \param __V1525/// A 128-bit integer vector containing the source bytes.1526/// \returns A 256-bit vector of [4 x i64] containing the zero-extended1527/// values.1528static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1529_mm256_cvtepu8_epi64(__m128i __V) {1530 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v16qu)__V, (__v16qu)__V, 0, 1, 2, 3), __v4di);1531}1532 1533/// Zero-extends 16-bit elements from the 128-bit vector of [8 x i16] in1534/// \a __V and returns the 32-bit values in the corresponding elements of a1535/// 256-bit vector of [8 x i32].1536///1537/// \code{.operation}1538/// FOR i := 0 TO 71539/// j := i*161540/// k := i*321541/// result[k+31:k] := ZeroExtend(__V[j+15:j])1542/// ENDFOR1543/// \endcode1544///1545/// \headerfile <immintrin.h>1546///1547/// This intrinsic corresponds to the \c VPMOVZXWD instruction.1548///1549/// \param __V1550/// A 128-bit vector of [8 x i16] containing the source values.1551/// \returns A 256-bit vector of [8 x i32] containing the zero-extended1552/// values.1553static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1554_mm256_cvtepu16_epi32(__m128i __V) {1555 return (__m256i)__builtin_convertvector((__v8hu)__V, __v8si);1556}1557 1558/// Zero-extends 16-bit elements from the lower half of the 128-bit vector of1559/// [8 x i16] in \a __V and returns the 64-bit values in the corresponding1560/// elements of a 256-bit vector of [4 x i64].1561///1562/// \code{.operation}1563/// result[63:0] := ZeroExtend(__V[15:0])1564/// result[127:64] := ZeroExtend(__V[31:16])1565/// result[191:128] := ZeroExtend(__V[47:32])1566/// result[255:192] := ZeroExtend(__V[64:48])1567/// \endcode1568///1569/// \headerfile <immintrin.h>1570///1571/// This intrinsic corresponds to the \c VPMOVSXWQ instruction.1572///1573/// \param __V1574/// A 128-bit vector of [8 x i16] containing the source values.1575/// \returns A 256-bit vector of [4 x i64] containing the zero-extended1576/// values.1577static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1578_mm256_cvtepu16_epi64(__m128i __V) {1579 return (__m256i)__builtin_convertvector(__builtin_shufflevector((__v8hu)__V, (__v8hu)__V, 0, 1, 2, 3), __v4di);1580}1581 1582/// Zero-extends 32-bit elements from the 128-bit vector of [4 x i32] in1583/// \a __V and returns the 64-bit values in the corresponding elements of a1584/// 256-bit vector of [4 x i64].1585///1586/// \code{.operation}1587/// result[63:0] := ZeroExtend(__V[31:0])1588/// result[127:64] := ZeroExtend(__V[63:32])1589/// result[191:128] := ZeroExtend(__V[95:64])1590/// result[255:192] := ZeroExtend(__V[127:96])1591/// \endcode1592///1593/// \headerfile <immintrin.h>1594///1595/// This intrinsic corresponds to the \c VPMOVZXDQ instruction.1596///1597/// \param __V1598/// A 128-bit vector of [4 x i32] containing the source values.1599/// \returns A 256-bit vector of [4 x i64] containing the zero-extended1600/// values.1601static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1602_mm256_cvtepu32_epi64(__m128i __V) {1603 return (__m256i)__builtin_convertvector((__v4su)__V, __v4di);1604}1605 1606/// Multiplies signed 32-bit integers from even-numbered elements of two1607/// 256-bit vectors of [8 x i32] and returns the 64-bit products in the1608/// [4 x i64] result.1609///1610/// \code{.operation}1611/// result[63:0] := __a[31:0] * __b[31:0]1612/// result[127:64] := __a[95:64] * __b[95:64]1613/// result[191:128] := __a[159:128] * __b[159:128]1614/// result[255:192] := __a[223:192] * __b[223:192]1615/// \endcode1616///1617/// \headerfile <immintrin.h>1618///1619/// This intrinsic corresponds to the \c VPMULDQ instruction.1620///1621/// \param __a1622/// A 256-bit vector of [8 x i32] containing one of the source operands.1623/// \param __b1624/// A 256-bit vector of [8 x i32] containing one of the source operands.1625/// \returns A 256-bit vector of [4 x i64] containing the products.1626static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1627_mm256_mul_epi32(__m256i __a, __m256i __b) {1628 return (__m256i)__builtin_ia32_pmuldq256((__v8si)__a, (__v8si)__b);1629}1630 1631/// Multiplies signed 16-bit integer elements of two 256-bit vectors of1632/// [16 x i16], truncates the 32-bit results to the most significant 181633/// bits, rounds by adding 1, and returns bits [16:1] of each rounded1634/// product in the [16 x i16] result.1635///1636/// \code{.operation}1637/// FOR i := 0 TO 151638/// j := i*161639/// temp := ((__a[j+15:j] * __b[j+15:j]) >> 14) + 11640/// result[j+15:j] := temp[16:1]1641/// \endcode1642///1643/// \headerfile <immintrin.h>1644///1645/// This intrinsic corresponds to the \c VPMULHRSW instruction.1646///1647/// \param __a1648/// A 256-bit vector of [16 x i16] containing one of the source operands.1649/// \param __b1650/// A 256-bit vector of [16 x i16] containing one of the source operands.1651/// \returns A 256-bit vector of [16 x i16] containing the rounded products.1652static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1653_mm256_mulhrs_epi16(__m256i __a, __m256i __b) {1654 return (__m256i)__builtin_ia32_pmulhrsw256((__v16hi)__a, (__v16hi)__b);1655}1656 1657/// Multiplies unsigned 16-bit integer elements of two 256-bit vectors of1658/// [16 x i16], and returns the upper 16 bits of each 32-bit product in the1659/// [16 x i16] result.1660///1661/// \headerfile <immintrin.h>1662///1663/// This intrinsic corresponds to the \c VPMULHUW instruction.1664///1665/// \param __a1666/// A 256-bit vector of [16 x i16] containing one of the source operands.1667/// \param __b1668/// A 256-bit vector of [16 x i16] containing one of the source operands.1669/// \returns A 256-bit vector of [16 x i16] containing the products.1670static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1671_mm256_mulhi_epu16(__m256i __a, __m256i __b) {1672 return (__m256i)__builtin_ia32_pmulhuw256((__v16hu)__a, (__v16hu)__b);1673}1674 1675/// Multiplies signed 16-bit integer elements of two 256-bit vectors of1676/// [16 x i16], and returns the upper 16 bits of each 32-bit product in the1677/// [16 x i16] result.1678///1679/// \headerfile <immintrin.h>1680///1681/// This intrinsic corresponds to the \c VPMULHW instruction.1682///1683/// \param __a1684/// A 256-bit vector of [16 x i16] containing one of the source operands.1685/// \param __b1686/// A 256-bit vector of [16 x i16] containing one of the source operands.1687/// \returns A 256-bit vector of [16 x i16] containing the products.1688static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1689_mm256_mulhi_epi16(__m256i __a, __m256i __b)1690{1691 return (__m256i)__builtin_ia32_pmulhw256((__v16hi)__a, (__v16hi)__b);1692}1693 1694/// Multiplies signed 16-bit integer elements of two 256-bit vectors of1695/// [16 x i16], and returns the lower 16 bits of each 32-bit product in the1696/// [16 x i16] result.1697///1698/// \headerfile <immintrin.h>1699///1700/// This intrinsic corresponds to the \c VPMULLW instruction.1701///1702/// \param __a1703/// A 256-bit vector of [16 x i16] containing one of the source operands.1704/// \param __b1705/// A 256-bit vector of [16 x i16] containing one of the source operands.1706/// \returns A 256-bit vector of [16 x i16] containing the products.1707static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1708_mm256_mullo_epi16(__m256i __a, __m256i __b)1709{1710 return (__m256i)((__v16hu)__a * (__v16hu)__b);1711}1712 1713/// Multiplies signed 32-bit integer elements of two 256-bit vectors of1714/// [8 x i32], and returns the lower 32 bits of each 64-bit product in the1715/// [8 x i32] result.1716///1717/// \headerfile <immintrin.h>1718///1719/// This intrinsic corresponds to the \c VPMULLD instruction.1720///1721/// \param __a1722/// A 256-bit vector of [8 x i32] containing one of the source operands.1723/// \param __b1724/// A 256-bit vector of [8 x i32] containing one of the source operands.1725/// \returns A 256-bit vector of [8 x i32] containing the products.1726static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1727_mm256_mullo_epi32(__m256i __a, __m256i __b) {1728 return (__m256i)((__v8su)__a * (__v8su)__b);1729}1730 1731/// Multiplies unsigned 32-bit integers from even-numered elements of two1732/// 256-bit vectors of [8 x i32] and returns the 64-bit products in the1733/// [4 x i64] result.1734///1735/// \code{.operation}1736/// result[63:0] := __a[31:0] * __b[31:0]1737/// result[127:64] := __a[95:64] * __b[95:64]1738/// result[191:128] := __a[159:128] * __b[159:128]1739/// result[255:192] := __a[223:192] * __b[223:192]1740/// \endcode1741///1742/// \headerfile <immintrin.h>1743///1744/// This intrinsic corresponds to the \c VPMULUDQ instruction.1745///1746/// \param __a1747/// A 256-bit vector of [8 x i32] containing one of the source operands.1748/// \param __b1749/// A 256-bit vector of [8 x i32] containing one of the source operands.1750/// \returns A 256-bit vector of [4 x i64] containing the products.1751static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1752_mm256_mul_epu32(__m256i __a, __m256i __b) {1753 return __builtin_ia32_pmuludq256((__v8si)__a, (__v8si)__b);1754}1755 1756/// Computes the bitwise OR of the 256-bit integer vectors in \a __a and1757/// \a __b.1758///1759/// \headerfile <immintrin.h>1760///1761/// This intrinsic corresponds to the \c VPOR instruction.1762///1763/// \param __a1764/// A 256-bit integer vector.1765/// \param __b1766/// A 256-bit integer vector.1767/// \returns A 256-bit integer vector containing the result.1768static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1769_mm256_or_si256(__m256i __a, __m256i __b)1770{1771 return (__m256i)((__v4du)__a | (__v4du)__b);1772}1773 1774/// Computes four sum of absolute difference (SAD) operations on sets of eight1775/// unsigned 8-bit integers from the 256-bit integer vectors \a __a and1776/// \a __b.1777///1778/// One SAD result is computed for each set of eight bytes from \a __a and1779/// eight bytes from \a __b. The zero-extended SAD value is returned in the1780/// corresponding 64-bit element of the result.1781///1782/// A single SAD operation takes the differences between the corresponding1783/// bytes of \a __a and \a __b, takes the absolute value of each difference,1784/// and sums these eight values to form one 16-bit result. This operation1785/// is repeated four times with successive sets of eight bytes.1786///1787/// \code{.operation}1788/// FOR i := 0 TO 31789/// j := i*641790/// temp0 := ABS(__a[j+7:j] - __b[j+7:j])1791/// temp1 := ABS(__a[j+15:j+8] - __b[j+15:j+8])1792/// temp2 := ABS(__a[j+23:j+16] - __b[j+23:j+16])1793/// temp3 := ABS(__a[j+31:j+24] - __b[j+31:j+24])1794/// temp4 := ABS(__a[j+39:j+32] - __b[j+39:j+32])1795/// temp5 := ABS(__a[j+47:j+40] - __b[j+47:j+40])1796/// temp6 := ABS(__a[j+55:j+48] - __b[j+55:j+48])1797/// temp7 := ABS(__a[j+63:j+56] - __b[j+63:j+56])1798/// result[j+15:j] := temp0 + temp1 + temp2 + temp3 +1799/// temp4 + temp5 + temp6 + temp71800/// result[j+63:j+16] := 01801/// ENDFOR1802/// \endcode1803///1804/// \headerfile <immintrin.h>1805///1806/// This intrinsic corresponds to the \c VPSADBW instruction.1807///1808/// \param __a1809/// A 256-bit integer vector.1810/// \param __b1811/// A 256-bit integer vector.1812/// \returns A 256-bit integer vector containing the result.1813static __inline__ __m256i __DEFAULT_FN_ATTRS2561814_mm256_sad_epu8(__m256i __a, __m256i __b)1815{1816 return __builtin_ia32_psadbw256((__v32qi)__a, (__v32qi)__b);1817}1818 1819/// Shuffles 8-bit integers in the 256-bit integer vector \a __a according1820/// to control information in the 256-bit integer vector \a __b, and1821/// returns the 256-bit result. In effect there are two separate 128-bit1822/// shuffles in the lower and upper halves.1823///1824/// \code{.operation}1825/// FOR i := 0 TO 311826/// j := i*81827/// IF __b[j+7] == 11828/// result[j+7:j] := 01829/// ELSE1830/// k := __b[j+3:j] * 81831/// IF i > 151832/// k := k + 1281833/// FI1834/// result[j+7:j] := __a[k+7:k]1835/// FI1836/// ENDFOR1837/// \endcode1838///1839/// \headerfile <immintrin.h>1840///1841/// This intrinsic corresponds to the \c VPSHUFB instruction.1842///1843/// \param __a1844/// A 256-bit integer vector containing source values.1845/// \param __b1846/// A 256-bit integer vector containing control information to determine1847/// what goes into the corresponding byte of the result. If bit 7 of the1848/// control byte is 1, the result byte is 0; otherwise, bits 3:0 of the1849/// control byte specify the index (within the same 128-bit half) of \a __a1850/// to copy to the result byte.1851/// \returns A 256-bit integer vector containing the result.1852static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1853_mm256_shuffle_epi8(__m256i __a, __m256i __b) {1854 return (__m256i)__builtin_ia32_pshufb256((__v32qi)__a, (__v32qi)__b);1855}1856 1857/// Shuffles 32-bit integers from the 256-bit vector of [8 x i32] in \a a1858/// according to control information in the integer literal \a imm, and1859/// returns the 256-bit result. In effect there are two parallel 128-bit1860/// shuffles in the lower and upper halves.1861///1862/// \code{.operation}1863/// FOR i := 0 to 31864/// j := i*321865/// k := (imm >> i*2)[1:0] * 321866/// result[j+31:j] := a[k+31:k]1867/// result[128+j+31:128+j] := a[128+k+31:128+k]1868/// ENDFOR1869/// \endcode1870///1871/// \headerfile <immintrin.h>1872///1873/// \code1874/// __m256i _mm256_shuffle_epi32(__m256i a, const int imm);1875/// \endcode1876///1877/// This intrinsic corresponds to the \c VPSHUFB instruction.1878///1879/// \param a1880/// A 256-bit vector of [8 x i32] containing source values.1881/// \param imm1882/// An immediate 8-bit value specifying which elements to copy from \a a.1883/// \a imm[1:0] specifies the index in \a a for elements 0 and 4 of the1884/// result, \a imm[3:2] specifies the index for elements 1 and 5, and so1885/// forth.1886/// \returns A 256-bit vector of [8 x i32] containing the result.1887#define _mm256_shuffle_epi32(a, imm) \1888 ((__m256i)__builtin_ia32_pshufd256((__v8si)(__m256i)(a), (int)(imm)))1889 1890/// Shuffles 16-bit integers from the 256-bit vector of [16 x i16] in \a a1891/// according to control information in the integer literal \a imm, and1892/// returns the 256-bit result. The upper 64 bits of each 128-bit half1893/// are shuffled in parallel; the lower 64 bits of each 128-bit half are1894/// copied from \a a unchanged.1895///1896/// \code{.operation}1897/// result[63:0] := a[63:0]1898/// result[191:128] := a[191:128]1899/// FOR i := 0 TO 31900/// j := i * 16 + 641901/// k := (imm >> i*2)[1:0] * 16 + 641902/// result[j+15:j] := a[k+15:k]1903/// result[128+j+15:128+j] := a[128+k+15:128+k]1904/// ENDFOR1905/// \endcode1906///1907/// \headerfile <immintrin.h>1908///1909/// \code1910/// __m256i _mm256_shufflehi_epi16(__m256i a, const int imm);1911/// \endcode1912///1913/// This intrinsic corresponds to the \c VPSHUFHW instruction.1914///1915/// \param a1916/// A 256-bit vector of [16 x i16] containing source values.1917/// \param imm1918/// An immediate 8-bit value specifying which elements to copy from \a a.1919/// \a imm[1:0] specifies the index in \a a for elements 4 and 8 of the1920/// result, \a imm[3:2] specifies the index for elements 5 and 9, and so1921/// forth. Indexes are offset by 4 (so 0 means index 4, and so forth).1922/// \returns A 256-bit vector of [16 x i16] containing the result.1923#define _mm256_shufflehi_epi16(a, imm) \1924 ((__m256i)__builtin_ia32_pshufhw256((__v16hi)(__m256i)(a), (int)(imm)))1925 1926/// Shuffles 16-bit integers from the 256-bit vector of [16 x i16] \a a1927/// according to control information in the integer literal \a imm, and1928/// returns the 256-bit [16 x i16] result. The lower 64 bits of each1929/// 128-bit half are shuffled; the upper 64 bits of each 128-bit half are1930/// copied from \a a unchanged.1931///1932/// \code{.operation}1933/// result[127:64] := a[127:64]1934/// result[255:192] := a[255:192]1935/// FOR i := 0 TO 31936/// j := i * 161937/// k := (imm >> i*2)[1:0] * 161938/// result[j+15:j] := a[k+15:k]1939/// result[128+j+15:128+j] := a[128+k+15:128+k]1940/// ENDFOR1941/// \endcode1942///1943/// \headerfile <immintrin.h>1944///1945/// \code1946/// __m256i _mm256_shufflelo_epi16(__m256i a, const int imm);1947/// \endcode1948///1949/// This intrinsic corresponds to the \c VPSHUFLW instruction.1950///1951/// \param a1952/// A 256-bit vector of [16 x i16] to use as a source of data for the1953/// result.1954/// \param imm1955/// An immediate 8-bit value specifying which elements to copy from \a a.1956/// \a imm[1:0] specifies the index in \a a for elements 0 and 8 of the1957/// result, \a imm[3:2] specifies the index for elements 1 and 9, and so1958/// forth.1959/// \returns A 256-bit vector of [16 x i16] containing the result.1960#define _mm256_shufflelo_epi16(a, imm) \1961 ((__m256i)__builtin_ia32_pshuflw256((__v16hi)(__m256i)(a), (int)(imm)))1962 1963/// Sets each byte of the result to the corresponding byte of the 256-bit1964/// integer vector in \a __a, the negative of that byte, or zero, depending1965/// on whether the corresponding byte of the 256-bit integer vector in1966/// \a __b is greater than zero, less than zero, or equal to zero,1967/// respectively.1968///1969/// \headerfile <immintrin.h>1970///1971/// This intrinsic corresponds to the \c VPSIGNB instruction.1972///1973/// \param __a1974/// A 256-bit integer vector.1975/// \param __b1976/// A 256-bit integer vector].1977/// \returns A 256-bit integer vector containing the result.1978static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1979_mm256_sign_epi8(__m256i __a, __m256i __b) {1980 return (__m256i)__builtin_ia32_psignb256((__v32qi)__a, (__v32qi)__b);1981}1982 1983/// Sets each element of the result to the corresponding element of the1984/// 256-bit vector of [16 x i16] in \a __a, the negative of that element,1985/// or zero, depending on whether the corresponding element of the 256-bit1986/// vector of [16 x i16] in \a __b is greater than zero, less than zero, or1987/// equal to zero, respectively.1988///1989/// \headerfile <immintrin.h>1990///1991/// This intrinsic corresponds to the \c VPSIGNW instruction.1992///1993/// \param __a1994/// A 256-bit vector of [16 x i16].1995/// \param __b1996/// A 256-bit vector of [16 x i16].1997/// \returns A 256-bit vector of [16 x i16] containing the result.1998static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR1999_mm256_sign_epi16(__m256i __a, __m256i __b) {2000 return (__m256i)__builtin_ia32_psignw256((__v16hi)__a, (__v16hi)__b);2001}2002 2003/// Sets each element of the result to the corresponding element of the2004/// 256-bit vector of [8 x i32] in \a __a, the negative of that element, or2005/// zero, depending on whether the corresponding element of the 256-bit2006/// vector of [8 x i32] in \a __b is greater than zero, less than zero, or2007/// equal to zero, respectively.2008///2009/// \headerfile <immintrin.h>2010///2011/// This intrinsic corresponds to the \c VPSIGND instruction.2012///2013/// \param __a2014/// A 256-bit vector of [8 x i32].2015/// \param __b2016/// A 256-bit vector of [8 x i32].2017/// \returns A 256-bit vector of [8 x i32] containing the result.2018static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2019_mm256_sign_epi32(__m256i __a, __m256i __b) {2020 return (__m256i)__builtin_ia32_psignd256((__v8si)__a, (__v8si)__b);2021}2022 2023/// Shifts each 128-bit half of the 256-bit integer vector \a a left by2024/// \a imm bytes, shifting in zero bytes, and returns the result. If \a imm2025/// is greater than 15, the returned result is all zeroes.2026///2027/// \headerfile <immintrin.h>2028///2029/// \code2030/// __m256i _mm256_slli_si256(__m256i a, const int imm);2031/// \endcode2032///2033/// This intrinsic corresponds to the \c VPSLLDQ instruction.2034///2035/// \param a2036/// A 256-bit integer vector to be shifted.2037/// \param imm2038/// An unsigned immediate value specifying the shift count (in bytes).2039/// \returns A 256-bit integer vector containing the result.2040#define _mm256_slli_si256(a, imm) \2041 ((__m256i)__builtin_ia32_pslldqi256_byteshift((__v32qi)(__m256i)(a), \2042 (int)(imm)))2043 2044/// Shifts each 128-bit half of the 256-bit integer vector \a a left by2045/// \a imm bytes, shifting in zero bytes, and returns the result. If \a imm2046/// is greater than 15, the returned result is all zeroes.2047///2048/// \headerfile <immintrin.h>2049///2050/// \code2051/// __m256i _mm256_bslli_epi128(__m256i a, const int imm);2052/// \endcode2053///2054/// This intrinsic corresponds to the \c VPSLLDQ instruction.2055///2056/// \param a2057/// A 256-bit integer vector to be shifted.2058/// \param imm2059/// An unsigned immediate value specifying the shift count (in bytes).2060/// \returns A 256-bit integer vector containing the result.2061#define _mm256_bslli_epi128(a, imm) \2062 ((__m256i)__builtin_ia32_pslldqi256_byteshift((__v32qi)(__m256i)(a), \2063 (int)(imm)))2064 2065/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2066/// left by \a __count bits, shifting in zero bits, and returns the result.2067/// If \a __count is greater than 15, the returned result is all zeroes.2068///2069/// \headerfile <immintrin.h>2070///2071/// This intrinsic corresponds to the \c VPSLLW instruction.2072///2073/// \param __a2074/// A 256-bit vector of [16 x i16] to be shifted.2075/// \param __count2076/// An unsigned integer value specifying the shift count (in bits).2077/// \returns A 256-bit vector of [16 x i16] containing the result.2078static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2079_mm256_slli_epi16(__m256i __a, int __count) {2080 return (__m256i)__builtin_ia32_psllwi256((__v16hi)__a, __count);2081}2082 2083/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2084/// left by the number of bits specified by the lower 64 bits of \a __count,2085/// shifting in zero bits, and returns the result. If \a __count is greater2086/// than 15, the returned result is all zeroes.2087///2088/// \headerfile <immintrin.h>2089///2090/// This intrinsic corresponds to the \c VPSLLW instruction.2091///2092/// \param __a2093/// A 256-bit vector of [16 x i16] to be shifted.2094/// \param __count2095/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2096/// shift count (in bits). The upper element is ignored.2097/// \returns A 256-bit vector of [16 x i16] containing the result.2098static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2099_mm256_sll_epi16(__m256i __a, __m128i __count) {2100 return (__m256i)__builtin_ia32_psllw256((__v16hi)__a, (__v8hi)__count);2101}2102 2103/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2104/// left by \a __count bits, shifting in zero bits, and returns the result.2105/// If \a __count is greater than 31, the returned result is all zeroes.2106///2107/// \headerfile <immintrin.h>2108///2109/// This intrinsic corresponds to the \c VPSLLD instruction.2110///2111/// \param __a2112/// A 256-bit vector of [8 x i32] to be shifted.2113/// \param __count2114/// An unsigned integer value specifying the shift count (in bits).2115/// \returns A 256-bit vector of [8 x i32] containing the result.2116static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2117_mm256_slli_epi32(__m256i __a, int __count) {2118 return (__m256i)__builtin_ia32_pslldi256((__v8si)__a, __count);2119}2120 2121/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2122/// left by the number of bits given in the lower 64 bits of \a __count,2123/// shifting in zero bits, and returns the result. If \a __count is greater2124/// than 31, the returned result is all zeroes.2125///2126/// \headerfile <immintrin.h>2127///2128/// This intrinsic corresponds to the \c VPSLLD instruction.2129///2130/// \param __a2131/// A 256-bit vector of [8 x i32] to be shifted.2132/// \param __count2133/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2134/// shift count (in bits). The upper element is ignored.2135/// \returns A 256-bit vector of [8 x i32] containing the result.2136static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2137_mm256_sll_epi32(__m256i __a, __m128i __count) {2138 return (__m256i)__builtin_ia32_pslld256((__v8si)__a, (__v4si)__count);2139}2140 2141/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __a2142/// left by \a __count bits, shifting in zero bits, and returns the result.2143/// If \a __count is greater than 63, the returned result is all zeroes.2144///2145/// \headerfile <immintrin.h>2146///2147/// This intrinsic corresponds to the \c VPSLLQ instruction.2148///2149/// \param __a2150/// A 256-bit vector of [4 x i64] to be shifted.2151/// \param __count2152/// An unsigned integer value specifying the shift count (in bits).2153/// \returns A 256-bit vector of [4 x i64] containing the result.2154static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2155_mm256_slli_epi64(__m256i __a, int __count) {2156 return __builtin_ia32_psllqi256((__v4di)__a, __count);2157}2158 2159/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __a2160/// left by the number of bits given in the lower 64 bits of \a __count,2161/// shifting in zero bits, and returns the result. If \a __count is greater2162/// than 63, the returned result is all zeroes.2163///2164/// \headerfile <immintrin.h>2165///2166/// This intrinsic corresponds to the \c VPSLLQ instruction.2167///2168/// \param __a2169/// A 256-bit vector of [4 x i64] to be shifted.2170/// \param __count2171/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2172/// shift count (in bits). The upper element is ignored.2173/// \returns A 256-bit vector of [4 x i64] containing the result.2174static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2175_mm256_sll_epi64(__m256i __a, __m128i __count) {2176 return __builtin_ia32_psllq256((__v4di)__a, __count);2177}2178 2179/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2180/// right by \a __count bits, shifting in sign bits, and returns the result.2181/// If \a __count is greater than 15, each element of the result is either2182/// 0 or -1 according to the corresponding input sign bit.2183///2184/// \headerfile <immintrin.h>2185///2186/// This intrinsic corresponds to the \c VPSRAW instruction.2187///2188/// \param __a2189/// A 256-bit vector of [16 x i16] to be shifted.2190/// \param __count2191/// An unsigned integer value specifying the shift count (in bits).2192/// \returns A 256-bit vector of [16 x i16] containing the result.2193static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2194_mm256_srai_epi16(__m256i __a, int __count) {2195 return (__m256i)__builtin_ia32_psrawi256((__v16hi)__a, __count);2196}2197 2198/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2199/// right by the number of bits given in the lower 64 bits of \a __count,2200/// shifting in sign bits, and returns the result. If \a __count is greater2201/// than 15, each element of the result is either 0 or -1 according to the2202/// corresponding input sign bit.2203///2204/// \headerfile <immintrin.h>2205///2206/// This intrinsic corresponds to the \c VPSRAW instruction.2207///2208/// \param __a2209/// A 256-bit vector of [16 x i16] to be shifted.2210/// \param __count2211/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2212/// shift count (in bits). The upper element is ignored.2213/// \returns A 256-bit vector of [16 x i16] containing the result.2214static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2215_mm256_sra_epi16(__m256i __a, __m128i __count) {2216 return (__m256i)__builtin_ia32_psraw256((__v16hi)__a, (__v8hi)__count);2217}2218 2219/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2220/// right by \a __count bits, shifting in sign bits, and returns the result.2221/// If \a __count is greater than 31, each element of the result is either2222/// 0 or -1 according to the corresponding input sign bit.2223///2224/// \headerfile <immintrin.h>2225///2226/// This intrinsic corresponds to the \c VPSRAD instruction.2227///2228/// \param __a2229/// A 256-bit vector of [8 x i32] to be shifted.2230/// \param __count2231/// An unsigned integer value specifying the shift count (in bits).2232/// \returns A 256-bit vector of [8 x i32] containing the result.2233static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2234_mm256_srai_epi32(__m256i __a, int __count) {2235 return (__m256i)__builtin_ia32_psradi256((__v8si)__a, __count);2236}2237 2238/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2239/// right by the number of bits given in the lower 64 bits of \a __count,2240/// shifting in sign bits, and returns the result. If \a __count is greater2241/// than 31, each element of the result is either 0 or -1 according to the2242/// corresponding input sign bit.2243///2244/// \headerfile <immintrin.h>2245///2246/// This intrinsic corresponds to the \c VPSRAD instruction.2247///2248/// \param __a2249/// A 256-bit vector of [8 x i32] to be shifted.2250/// \param __count2251/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2252/// shift count (in bits). The upper element is ignored.2253/// \returns A 256-bit vector of [8 x i32] containing the result.2254static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2255_mm256_sra_epi32(__m256i __a, __m128i __count) {2256 return (__m256i)__builtin_ia32_psrad256((__v8si)__a, (__v4si)__count);2257}2258 2259/// Shifts each 128-bit half of the 256-bit integer vector in \a a right by2260/// \a imm bytes, shifting in zero bytes, and returns the result. If2261/// \a imm is greater than 15, the returned result is all zeroes.2262///2263/// \headerfile <immintrin.h>2264///2265/// \code2266/// __m256i _mm256_srli_si256(__m256i a, const int imm);2267/// \endcode2268///2269/// This intrinsic corresponds to the \c VPSRLDQ instruction.2270///2271/// \param a2272/// A 256-bit integer vector to be shifted.2273/// \param imm2274/// An unsigned immediate value specifying the shift count (in bytes).2275/// \returns A 256-bit integer vector containing the result.2276#define _mm256_srli_si256(a, imm) \2277 ((__m256i)__builtin_ia32_psrldqi256_byteshift((__v32qi)(__m256i)(a), \2278 (int)(imm)))2279 2280/// Shifts each 128-bit half of the 256-bit integer vector in \a a right by2281/// \a imm bytes, shifting in zero bytes, and returns the result. If2282/// \a imm is greater than 15, the returned result is all zeroes.2283///2284/// \headerfile <immintrin.h>2285///2286/// \code2287/// __m256i _mm256_bsrli_epi128(__m256i a, const int imm);2288/// \endcode2289///2290/// This intrinsic corresponds to the \c VPSRLDQ instruction.2291///2292/// \param a2293/// A 256-bit integer vector to be shifted.2294/// \param imm2295/// An unsigned immediate value specifying the shift count (in bytes).2296/// \returns A 256-bit integer vector containing the result.2297#define _mm256_bsrli_epi128(a, imm) \2298 ((__m256i)__builtin_ia32_psrldqi256_byteshift((__v32qi)(__m256i)(a), \2299 (int)(imm)))2300 2301/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2302/// right by \a __count bits, shifting in zero bits, and returns the result.2303/// If \a __count is greater than 15, the returned result is all zeroes.2304///2305/// \headerfile <immintrin.h>2306///2307/// This intrinsic corresponds to the \c VPSRLW instruction.2308///2309/// \param __a2310/// A 256-bit vector of [16 x i16] to be shifted.2311/// \param __count2312/// An unsigned integer value specifying the shift count (in bits).2313/// \returns A 256-bit vector of [16 x i16] containing the result.2314static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2315_mm256_srli_epi16(__m256i __a, int __count) {2316 return (__m256i)__builtin_ia32_psrlwi256((__v16hi)__a, __count);2317}2318 2319/// Shifts each 16-bit element of the 256-bit vector of [16 x i16] in \a __a2320/// right by the number of bits given in the lower 64 bits of \a __count,2321/// shifting in zero bits, and returns the result. If \a __count is greater2322/// than 15, the returned result is all zeroes.2323///2324/// \headerfile <immintrin.h>2325///2326/// This intrinsic corresponds to the \c VPSRLW instruction.2327///2328/// \param __a2329/// A 256-bit vector of [16 x i16] to be shifted.2330/// \param __count2331/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2332/// shift count (in bits). The upper element is ignored.2333/// \returns A 256-bit vector of [16 x i16] containing the result.2334static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2335_mm256_srl_epi16(__m256i __a, __m128i __count) {2336 return (__m256i)__builtin_ia32_psrlw256((__v16hi)__a, (__v8hi)__count);2337}2338 2339/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2340/// right by \a __count bits, shifting in zero bits, and returns the result.2341/// If \a __count is greater than 31, the returned result is all zeroes.2342///2343/// \headerfile <immintrin.h>2344///2345/// This intrinsic corresponds to the \c VPSRLD instruction.2346///2347/// \param __a2348/// A 256-bit vector of [8 x i32] to be shifted.2349/// \param __count2350/// An unsigned integer value specifying the shift count (in bits).2351/// \returns A 256-bit vector of [8 x i32] containing the result.2352static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2353_mm256_srli_epi32(__m256i __a, int __count) {2354 return (__m256i)__builtin_ia32_psrldi256((__v8si)__a, __count);2355}2356 2357/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __a2358/// right by the number of bits given in the lower 64 bits of \a __count,2359/// shifting in zero bits, and returns the result. If \a __count is greater2360/// than 31, the returned result is all zeroes.2361///2362/// \headerfile <immintrin.h>2363///2364/// This intrinsic corresponds to the \c VPSRLD instruction.2365///2366/// \param __a2367/// A 256-bit vector of [8 x i32] to be shifted.2368/// \param __count2369/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2370/// shift count (in bits). The upper element is ignored.2371/// \returns A 256-bit vector of [8 x i32] containing the result.2372static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2373_mm256_srl_epi32(__m256i __a, __m128i __count) {2374 return (__m256i)__builtin_ia32_psrld256((__v8si)__a, (__v4si)__count);2375}2376 2377/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __a2378/// right by \a __count bits, shifting in zero bits, and returns the result.2379/// If \a __count is greater than 63, the returned result is all zeroes.2380///2381/// \headerfile <immintrin.h>2382///2383/// This intrinsic corresponds to the \c VPSRLQ instruction.2384///2385/// \param __a2386/// A 256-bit vector of [4 x i64] to be shifted.2387/// \param __count2388/// An unsigned integer value specifying the shift count (in bits).2389/// \returns A 256-bit vector of [4 x i64] containing the result.2390static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2391_mm256_srli_epi64(__m256i __a, int __count) {2392 return __builtin_ia32_psrlqi256((__v4di)__a, __count);2393}2394 2395/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __a2396/// right by the number of bits given in the lower 64 bits of \a __count,2397/// shifting in zero bits, and returns the result. If \a __count is greater2398/// than 63, the returned result is all zeroes.2399///2400/// \headerfile <immintrin.h>2401///2402/// This intrinsic corresponds to the \c VPSRLQ instruction.2403///2404/// \param __a2405/// A 256-bit vector of [4 x i64] to be shifted.2406/// \param __count2407/// A 128-bit vector of [2 x i64] whose lower element gives the unsigned2408/// shift count (in bits). The upper element is ignored.2409/// \returns A 256-bit vector of [4 x i64] containing the result.2410static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2411_mm256_srl_epi64(__m256i __a, __m128i __count) {2412 return __builtin_ia32_psrlq256((__v4di)__a, __count);2413}2414 2415/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer2416/// vectors. Returns the lower 8 bits of each difference in the2417/// corresponding byte of the 256-bit integer vector result (overflow is2418/// ignored).2419///2420/// \code{.operation}2421/// FOR i := 0 TO 312422/// j := i*82423/// result[j+7:j] := __a[j+7:j] - __b[j+7:j]2424/// ENDFOR2425/// \endcode2426///2427/// \headerfile <immintrin.h>2428///2429/// This intrinsic corresponds to the \c VPSUBB instruction.2430///2431/// \param __a2432/// A 256-bit integer vector containing the minuends.2433/// \param __b2434/// A 256-bit integer vector containing the subtrahends.2435/// \returns A 256-bit integer vector containing the differences.2436static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2437_mm256_sub_epi8(__m256i __a, __m256i __b) {2438 return (__m256i)((__v32qu)__a - (__v32qu)__b);2439}2440 2441/// Subtracts 16-bit integers from corresponding elements of two 256-bit2442/// vectors of [16 x i16]. Returns the lower 16 bits of each difference in2443/// the corresponding element of the [16 x i16] result (overflow is2444/// ignored).2445///2446/// \code{.operation}2447/// FOR i := 0 TO 152448/// j := i*162449/// result[j+15:j] := __a[j+15:j] - __b[j+15:j]2450/// ENDFOR2451/// \endcode2452///2453/// \headerfile <immintrin.h>2454///2455/// This intrinsic corresponds to the \c VPSUBW instruction.2456///2457/// \param __a2458/// A 256-bit vector of [16 x i16] containing the minuends.2459/// \param __b2460/// A 256-bit vector of [16 x i16] containing the subtrahends.2461/// \returns A 256-bit vector of [16 x i16] containing the differences.2462static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2463_mm256_sub_epi16(__m256i __a, __m256i __b) {2464 return (__m256i)((__v16hu)__a - (__v16hu)__b);2465}2466 2467/// Subtracts 32-bit integers from corresponding elements of two 256-bit2468/// vectors of [8 x i32]. Returns the lower 32 bits of each difference in2469/// the corresponding element of the [8 x i32] result (overflow is ignored).2470///2471/// \code{.operation}2472/// FOR i := 0 TO 72473/// j := i*322474/// result[j+31:j] := __a[j+31:j] - __b[j+31:j]2475/// ENDFOR2476/// \endcode2477///2478/// \headerfile <immintrin.h>2479///2480/// This intrinsic corresponds to the \c VPSUBD instruction.2481///2482/// \param __a2483/// A 256-bit vector of [8 x i32] containing the minuends.2484/// \param __b2485/// A 256-bit vector of [8 x i32] containing the subtrahends.2486/// \returns A 256-bit vector of [8 x i32] containing the differences.2487static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2488_mm256_sub_epi32(__m256i __a, __m256i __b) {2489 return (__m256i)((__v8su)__a - (__v8su)__b);2490}2491 2492/// Subtracts 64-bit integers from corresponding elements of two 256-bit2493/// vectors of [4 x i64]. Returns the lower 64 bits of each difference in2494/// the corresponding element of the [4 x i64] result (overflow is ignored).2495///2496/// \code{.operation}2497/// FOR i := 0 TO 32498/// j := i*642499/// result[j+63:j] := __a[j+63:j] - __b[j+63:j]2500/// ENDFOR2501/// \endcode2502///2503/// \headerfile <immintrin.h>2504///2505/// This intrinsic corresponds to the \c VPSUBQ instruction.2506///2507/// \param __a2508/// A 256-bit vector of [4 x i64] containing the minuends.2509/// \param __b2510/// A 256-bit vector of [4 x i64] containing the subtrahends.2511/// \returns A 256-bit vector of [4 x i64] containing the differences.2512static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2513_mm256_sub_epi64(__m256i __a, __m256i __b) {2514 return (__m256i)((__v4du)__a - (__v4du)__b);2515}2516 2517/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer2518/// vectors using signed saturation, and returns each differences in the2519/// corresponding byte of the 256-bit integer vector result.2520///2521/// \code{.operation}2522/// FOR i := 0 TO 312523/// j := i*82524/// result[j+7:j] := SATURATE8(__a[j+7:j] - __b[j+7:j])2525/// ENDFOR2526/// \endcode2527///2528/// \headerfile <immintrin.h>2529///2530/// This intrinsic corresponds to the \c VPSUBSB instruction.2531///2532/// \param __a2533/// A 256-bit integer vector containing the minuends.2534/// \param __b2535/// A 256-bit integer vector containing the subtrahends.2536/// \returns A 256-bit integer vector containing the differences.2537static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2538_mm256_subs_epi8(__m256i __a, __m256i __b) {2539 return (__m256i)__builtin_elementwise_sub_sat((__v32qs)__a, (__v32qs)__b);2540}2541 2542/// Subtracts 16-bit integers from corresponding elements of two 256-bit2543/// vectors of [16 x i16] using signed saturation, and returns each2544/// difference in the corresponding element of the [16 x i16] result.2545///2546/// \code{.operation}2547/// FOR i := 0 TO 152548/// j := i*162549/// result[j+7:j] := SATURATE16(__a[j+7:j] - __b[j+7:j])2550/// ENDFOR2551/// \endcode2552///2553/// \headerfile <immintrin.h>2554///2555/// This intrinsic corresponds to the \c VPSUBSW instruction.2556///2557/// \param __a2558/// A 256-bit vector of [16 x i16] containing the minuends.2559/// \param __b2560/// A 256-bit vector of [16 x i16] containing the subtrahends.2561/// \returns A 256-bit vector of [16 x i16] containing the differences.2562static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2563_mm256_subs_epi16(__m256i __a, __m256i __b) {2564 return (__m256i)__builtin_elementwise_sub_sat((__v16hi)__a, (__v16hi)__b);2565}2566 2567/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer2568/// vectors using unsigned saturation, and returns each difference in the2569/// corresponding byte of the 256-bit integer vector result. For each byte,2570/// computes <c> result = __a - __b </c>.2571///2572/// \code{.operation}2573/// FOR i := 0 TO 312574/// j := i*82575/// result[j+7:j] := SATURATE8U(__a[j+7:j] - __b[j+7:j])2576/// ENDFOR2577/// \endcode2578///2579/// \headerfile <immintrin.h>2580///2581/// This intrinsic corresponds to the \c VPSUBUSB instruction.2582///2583/// \param __a2584/// A 256-bit integer vector containing the minuends.2585/// \param __b2586/// A 256-bit integer vector containing the subtrahends.2587/// \returns A 256-bit integer vector containing the differences.2588static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2589_mm256_subs_epu8(__m256i __a, __m256i __b) {2590 return (__m256i)__builtin_elementwise_sub_sat((__v32qu)__a, (__v32qu)__b);2591}2592 2593/// Subtracts 16-bit integers from corresponding elements of two 256-bit2594/// vectors of [16 x i16] using unsigned saturation, and returns each2595/// difference in the corresponding element of the [16 x i16] result.2596///2597/// \code{.operation}2598/// FOR i := 0 TO 152599/// j := i*162600/// result[j+15:j] := SATURATE16U(__a[j+15:j] - __b[j+15:j])2601/// ENDFOR2602/// \endcode2603///2604/// \headerfile <immintrin.h>2605///2606/// This intrinsic corresponds to the \c VPSUBUSW instruction.2607///2608/// \param __a2609/// A 256-bit vector of [16 x i16] containing the minuends.2610/// \param __b2611/// A 256-bit vector of [16 x i16] containing the subtrahends.2612/// \returns A 256-bit vector of [16 x i16] containing the differences.2613static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2614_mm256_subs_epu16(__m256i __a, __m256i __b) {2615 return (__m256i)__builtin_elementwise_sub_sat((__v16hu)__a, (__v16hu)__b);2616}2617 2618/// Unpacks and interleaves 8-bit integers from parts of the 256-bit integer2619/// vectors in \a __a and \a __b to form the 256-bit result. Specifically,2620/// uses the upper 64 bits of each 128-bit half of \a __a and \a __b as2621/// input; other bits in these parameters are ignored.2622///2623/// \code{.operation}2624/// result[7:0] := __a[71:64]2625/// result[15:8] := __b[71:64]2626/// result[23:16] := __a[79:72]2627/// result[31:24] := __b[79:72]2628/// . . .2629/// result[127:120] := __b[127:120]2630/// result[135:128] := __a[199:192]2631/// . . .2632/// result[255:248] := __b[255:248]2633/// \endcode2634///2635/// \headerfile <immintrin.h>2636///2637/// This intrinsic corresponds to the \c VPUNPCKHBW instruction.2638///2639/// \param __a2640/// A 256-bit integer vector used as the source for the even-numbered bytes2641/// of the result.2642/// \param __b2643/// A 256-bit integer vector used as the source for the odd-numbered bytes2644/// of the result.2645/// \returns A 256-bit integer vector containing the result.2646static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2647_mm256_unpackhi_epi8(__m256i __a, __m256i __b) {2648 return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 8, 32+8, 9, 32+9, 10, 32+10, 11, 32+11, 12, 32+12, 13, 32+13, 14, 32+14, 15, 32+15, 24, 32+24, 25, 32+25, 26, 32+26, 27, 32+27, 28, 32+28, 29, 32+29, 30, 32+30, 31, 32+31);2649}2650 2651/// Unpacks and interleaves 16-bit integers from parts of the 256-bit vectors2652/// of [16 x i16] in \a __a and \a __b to return the resulting 256-bit2653/// vector of [16 x i16]. Specifically, uses the upper 64 bits of each2654/// 128-bit half of \a __a and \a __b as input; other bits in these2655/// parameters are ignored.2656///2657/// \code{.operation}2658/// result[15:0] := __a[79:64]2659/// result[31:16] := __b[79:64]2660/// result[47:32] := __a[95:80]2661/// result[63:48] := __b[95:80]2662/// . . .2663/// result[127:112] := __b[127:112]2664/// result[143:128] := __a[211:196]2665/// . . .2666/// result[255:240] := __b[255:240]2667/// \endcode2668///2669/// \headerfile <immintrin.h>2670///2671/// This intrinsic corresponds to the \c VPUNPCKHWD instruction.2672///2673/// \param __a2674/// A 256-bit vector of [16 x i16] used as the source for the even-numbered2675/// elements of the result.2676/// \param __b2677/// A 256-bit vector of [16 x i16] used as the source for the odd-numbered2678/// elements of the result.2679/// \returns A 256-bit vector of [16 x i16] containing the result.2680static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2681_mm256_unpackhi_epi16(__m256i __a, __m256i __b) {2682 return (__m256i)__builtin_shufflevector((__v16hi)__a, (__v16hi)__b, 4, 16+4, 5, 16+5, 6, 16+6, 7, 16+7, 12, 16+12, 13, 16+13, 14, 16+14, 15, 16+15);2683}2684 2685/// Unpacks and interleaves 32-bit integers from parts of the 256-bit vectors2686/// of [8 x i32] in \a __a and \a __b to return the resulting 256-bit vector2687/// of [8 x i32]. Specifically, uses the upper 64 bits of each 128-bit half2688/// of \a __a and \a __b as input; other bits in these parameters are2689/// ignored.2690///2691/// \code{.operation}2692/// result[31:0] := __a[95:64]2693/// result[63:32] := __b[95:64]2694/// result[95:64] := __a[127:96]2695/// result[127:96] := __b[127:96]2696/// result[159:128] := __a[223:192]2697/// result[191:160] := __b[223:192]2698/// result[223:192] := __a[255:224]2699/// result[255:224] := __b[255:224]2700/// \endcode2701///2702/// \headerfile <immintrin.h>2703///2704/// This intrinsic corresponds to the \c VPUNPCKHDQ instruction.2705///2706/// \param __a2707/// A 256-bit vector of [8 x i32] used as the source for the even-numbered2708/// elements of the result.2709/// \param __b2710/// A 256-bit vector of [8 x i32] used as the source for the odd-numbered2711/// elements of the result.2712/// \returns A 256-bit vector of [8 x i32] containing the result.2713static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2714_mm256_unpackhi_epi32(__m256i __a, __m256i __b) {2715 return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 2, 8+2, 3, 8+3, 6, 8+6, 7, 8+7);2716}2717 2718/// Unpacks and interleaves 64-bit integers from parts of the 256-bit vectors2719/// of [4 x i64] in \a __a and \a __b to return the resulting 256-bit vector2720/// of [4 x i64]. Specifically, uses the upper 64 bits of each 128-bit half2721/// of \a __a and \a __b as input; other bits in these parameters are2722/// ignored.2723///2724/// \code{.operation}2725/// result[63:0] := __a[127:64]2726/// result[127:64] := __b[127:64]2727/// result[191:128] := __a[255:192]2728/// result[255:192] := __b[255:192]2729/// \endcode2730///2731/// \headerfile <immintrin.h>2732///2733/// This intrinsic corresponds to the \c VPUNPCKHQDQ instruction.2734///2735/// \param __a2736/// A 256-bit vector of [4 x i64] used as the source for the even-numbered2737/// elements of the result.2738/// \param __b2739/// A 256-bit vector of [4 x i64] used as the source for the odd-numbered2740/// elements of the result.2741/// \returns A 256-bit vector of [4 x i64] containing the result.2742static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2743_mm256_unpackhi_epi64(__m256i __a, __m256i __b) {2744 return (__m256i)__builtin_shufflevector((__v4di)__a, (__v4di)__b, 1, 4+1, 3, 4+3);2745}2746 2747/// Unpacks and interleaves 8-bit integers from parts of the 256-bit integer2748/// vectors in \a __a and \a __b to form the 256-bit result. Specifically,2749/// uses the lower 64 bits of each 128-bit half of \a __a and \a __b as2750/// input; other bits in these parameters are ignored.2751///2752/// \code{.operation}2753/// result[7:0] := __a[7:0]2754/// result[15:8] := __b[7:0]2755/// result[23:16] := __a[15:8]2756/// result[31:24] := __b[15:8]2757/// . . .2758/// result[127:120] := __b[63:56]2759/// result[135:128] := __a[135:128]2760/// . . .2761/// result[255:248] := __b[191:184]2762/// \endcode2763///2764/// \headerfile <immintrin.h>2765///2766/// This intrinsic corresponds to the \c VPUNPCKLBW instruction.2767///2768/// \param __a2769/// A 256-bit integer vector used as the source for the even-numbered bytes2770/// of the result.2771/// \param __b2772/// A 256-bit integer vector used as the source for the odd-numbered bytes2773/// of the result.2774/// \returns A 256-bit integer vector containing the result.2775static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2776_mm256_unpacklo_epi8(__m256i __a, __m256i __b) {2777 return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 0, 32+0, 1, 32+1, 2, 32+2, 3, 32+3, 4, 32+4, 5, 32+5, 6, 32+6, 7, 32+7, 16, 32+16, 17, 32+17, 18, 32+18, 19, 32+19, 20, 32+20, 21, 32+21, 22, 32+22, 23, 32+23);2778}2779 2780/// Unpacks and interleaves 16-bit integers from parts of the 256-bit vectors2781/// of [16 x i16] in \a __a and \a __b to return the resulting 256-bit2782/// vector of [16 x i16]. Specifically, uses the lower 64 bits of each2783/// 128-bit half of \a __a and \a __b as input; other bits in these2784/// parameters are ignored.2785///2786/// \code{.operation}2787/// result[15:0] := __a[15:0]2788/// result[31:16] := __b[15:0]2789/// result[47:32] := __a[31:16]2790/// result[63:48] := __b[31:16]2791/// . . .2792/// result[127:112] := __b[63:48]2793/// result[143:128] := __a[143:128]2794/// . . .2795/// result[255:239] := __b[191:176]2796/// \endcode2797///2798/// \headerfile <immintrin.h>2799///2800/// This intrinsic corresponds to the \c VPUNPCKLWD instruction.2801///2802/// \param __a2803/// A 256-bit vector of [16 x i16] used as the source for the even-numbered2804/// elements of the result.2805/// \param __b2806/// A 256-bit vector of [16 x i16] used as the source for the odd-numbered2807/// elements of the result.2808/// \returns A 256-bit vector of [16 x i16] containing the result.2809static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2810_mm256_unpacklo_epi16(__m256i __a, __m256i __b) {2811 return (__m256i)__builtin_shufflevector((__v16hi)__a, (__v16hi)__b, 0, 16+0, 1, 16+1, 2, 16+2, 3, 16+3, 8, 16+8, 9, 16+9, 10, 16+10, 11, 16+11);2812}2813 2814/// Unpacks and interleaves 32-bit integers from parts of the 256-bit vectors2815/// of [8 x i32] in \a __a and \a __b to return the resulting 256-bit vector2816/// of [8 x i32]. Specifically, uses the lower 64 bits of each 128-bit half2817/// of \a __a and \a __b as input; other bits in these parameters are2818/// ignored.2819///2820/// \code{.operation}2821/// result[31:0] := __a[31:0]2822/// result[63:32] := __b[31:0]2823/// result[95:64] := __a[63:32]2824/// result[127:96] := __b[63:32]2825/// result[159:128] := __a[159:128]2826/// result[191:160] := __b[159:128]2827/// result[223:192] := __a[191:160]2828/// result[255:224] := __b[191:190]2829/// \endcode2830///2831/// \headerfile <immintrin.h>2832///2833/// This intrinsic corresponds to the \c VPUNPCKLDQ instruction.2834///2835/// \param __a2836/// A 256-bit vector of [8 x i32] used as the source for the even-numbered2837/// elements of the result.2838/// \param __b2839/// A 256-bit vector of [8 x i32] used as the source for the odd-numbered2840/// elements of the result.2841/// \returns A 256-bit vector of [8 x i32] containing the result.2842static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2843_mm256_unpacklo_epi32(__m256i __a, __m256i __b) {2844 return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 0, 8+0, 1, 8+1, 4, 8+4, 5, 8+5);2845}2846 2847/// Unpacks and interleaves 64-bit integers from parts of the 256-bit vectors2848/// of [4 x i64] in \a __a and \a __b to return the resulting 256-bit vector2849/// of [4 x i64]. Specifically, uses the lower 64 bits of each 128-bit half2850/// of \a __a and \a __b as input; other bits in these parameters are2851/// ignored.2852///2853/// \code{.operation}2854/// result[63:0] := __a[63:0]2855/// result[127:64] := __b[63:0]2856/// result[191:128] := __a[191:128]2857/// result[255:192] := __b[191:128]2858/// \endcode2859///2860/// \headerfile <immintrin.h>2861///2862/// This intrinsic corresponds to the \c VPUNPCKLQDQ instruction.2863///2864/// \param __a2865/// A 256-bit vector of [4 x i64] used as the source for the even-numbered2866/// elements of the result.2867/// \param __b2868/// A 256-bit vector of [4 x i64] used as the source for the odd-numbered2869/// elements of the result.2870/// \returns A 256-bit vector of [4 x i64] containing the result.2871static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2872_mm256_unpacklo_epi64(__m256i __a, __m256i __b) {2873 return (__m256i)__builtin_shufflevector((__v4di)__a, (__v4di)__b, 0, 4+0, 2, 4+2);2874}2875 2876/// Computes the bitwise XOR of the 256-bit integer vectors in \a __a and2877/// \a __b.2878///2879/// \headerfile <immintrin.h>2880///2881/// This intrinsic corresponds to the \c VPXOR instruction.2882///2883/// \param __a2884/// A 256-bit integer vector.2885/// \param __b2886/// A 256-bit integer vector.2887/// \returns A 256-bit integer vector containing the result.2888static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2889_mm256_xor_si256(__m256i __a, __m256i __b)2890{2891 return (__m256i)((__v4du)__a ^ (__v4du)__b);2892}2893 2894/// Loads the 256-bit integer vector from memory \a __V using a non-temporal2895/// memory hint and returns the vector. \a __V must be aligned on a 32-byte2896/// boundary.2897///2898/// \headerfile <immintrin.h>2899///2900/// This intrinsic corresponds to the \c VMOVNTDQA instruction.2901///2902/// \param __V2903/// A pointer to the 32-byte aligned memory containing the vector to load.2904/// \returns A 256-bit integer vector loaded from memory.2905static __inline__ __m256i __DEFAULT_FN_ATTRS2562906_mm256_stream_load_si256(const void *__V)2907{2908 typedef __v4di __v4di_aligned __attribute__((aligned(32)));2909 return (__m256i)__builtin_nontemporal_load((const __v4di_aligned *)__V);2910}2911 2912/// Broadcasts the 32-bit floating-point value from the low element of the2913/// 128-bit vector of [4 x float] in \a __X to all elements of the result's2914/// 128-bit vector of [4 x float].2915///2916/// \headerfile <immintrin.h>2917///2918/// This intrinsic corresponds to the \c VBROADCASTSS instruction.2919///2920/// \param __X2921/// A 128-bit vector of [4 x float] whose low element will be broadcast.2922/// \returns A 128-bit vector of [4 x float] containing the result.2923static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR2924_mm_broadcastss_ps(__m128 __X) {2925 return (__m128)__builtin_shufflevector((__v4sf)__X, (__v4sf)__X, 0, 0, 0, 0);2926}2927 2928/// Broadcasts the 64-bit floating-point value from the low element of the2929/// 128-bit vector of [2 x double] in \a __a to both elements of the2930/// result's 128-bit vector of [2 x double].2931///2932/// \headerfile <immintrin.h>2933///2934/// This intrinsic corresponds to the \c MOVDDUP instruction.2935///2936/// \param __a2937/// A 128-bit vector of [2 x double] whose low element will be broadcast.2938/// \returns A 128-bit vector of [2 x double] containing the result.2939static __inline__ __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR2940_mm_broadcastsd_pd(__m128d __a) {2941 return __builtin_shufflevector((__v2df)__a, (__v2df)__a, 0, 0);2942}2943 2944/// Broadcasts the 32-bit floating-point value from the low element of the2945/// 128-bit vector of [4 x float] in \a __X to all elements of the2946/// result's 256-bit vector of [8 x float].2947///2948/// \headerfile <immintrin.h>2949///2950/// This intrinsic corresponds to the \c VBROADCASTSS instruction.2951///2952/// \param __X2953/// A 128-bit vector of [4 x float] whose low element will be broadcast.2954/// \returns A 256-bit vector of [8 x float] containing the result.2955static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR2956_mm256_broadcastss_ps(__m128 __X) {2957 return (__m256)__builtin_shufflevector((__v4sf)__X, (__v4sf)__X, 0, 0, 0, 0, 0, 0, 0, 0);2958}2959 2960/// Broadcasts the 64-bit floating-point value from the low element of the2961/// 128-bit vector of [2 x double] in \a __X to all elements of the2962/// result's 256-bit vector of [4 x double].2963///2964/// \headerfile <immintrin.h>2965///2966/// This intrinsic corresponds to the \c VBROADCASTSD instruction.2967///2968/// \param __X2969/// A 128-bit vector of [2 x double] whose low element will be broadcast.2970/// \returns A 256-bit vector of [4 x double] containing the result.2971static __inline__ __m256d __DEFAULT_FN_ATTRS256_CONSTEXPR2972_mm256_broadcastsd_pd(__m128d __X) {2973 return (__m256d)__builtin_shufflevector((__v2df)__X, (__v2df)__X, 0, 0, 0, 0);2974}2975 2976/// Broadcasts the 128-bit integer data from \a __X to both the lower and2977/// upper halves of the 256-bit result.2978///2979/// \headerfile <immintrin.h>2980///2981/// This intrinsic corresponds to the \c VBROADCASTI128 instruction.2982///2983/// \param __X2984/// A 128-bit integer vector to be broadcast.2985/// \returns A 256-bit integer vector containing the result.2986static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR2987_mm256_broadcastsi128_si256(__m128i __X) {2988 return (__m256i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 1, 0, 1);2989}2990 2991#define _mm_broadcastsi128_si256(X) _mm256_broadcastsi128_si256(X)2992 2993/// Merges 32-bit integer elements from either of the two 128-bit vectors of2994/// [4 x i32] in \a V1 or \a V2 to the result's 128-bit vector of [4 x i32],2995/// as specified by the immediate integer operand \a M.2996///2997/// \code{.operation}2998/// FOR i := 0 TO 32999/// j := i*323000/// IF M[i] == 03001/// result[31+j:j] := V1[31+j:j]3002/// ELSE3003/// result[31+j:j] := V2[32+j:j]3004/// FI3005/// ENDFOR3006/// \endcode3007///3008/// \headerfile <immintrin.h>3009///3010/// \code3011/// __m128i _mm_blend_epi32(__m128i V1, __m128i V2, const int M);3012/// \endcode3013///3014/// This intrinsic corresponds to the \c VPBLENDDD instruction.3015///3016/// \param V13017/// A 128-bit vector of [4 x i32] containing source values.3018/// \param V23019/// A 128-bit vector of [4 x i32] containing source values.3020/// \param M3021/// An immediate 8-bit integer operand, with bits [3:0] specifying the3022/// source for each element of the result. The position of the mask bit3023/// corresponds to the index of a copied value. When a mask bit is 0, the3024/// element is copied from \a V1; otherwise, it is copied from \a V2.3025/// \returns A 128-bit vector of [4 x i32] containing the result.3026#define _mm_blend_epi32(V1, V2, M) \3027 ((__m128i)__builtin_ia32_pblendd128((__v4si)(__m128i)(V1), \3028 (__v4si)(__m128i)(V2), (int)(M)))3029 3030/// Merges 32-bit integer elements from either of the two 256-bit vectors of3031/// [8 x i32] in \a V1 or \a V2 to return a 256-bit vector of [8 x i32],3032/// as specified by the immediate integer operand \a M.3033///3034/// \code{.operation}3035/// FOR i := 0 TO 73036/// j := i*323037/// IF M[i] == 03038/// result[31+j:j] := V1[31+j:j]3039/// ELSE3040/// result[31+j:j] := V2[32+j:j]3041/// FI3042/// ENDFOR3043/// \endcode3044///3045/// \headerfile <immintrin.h>3046///3047/// \code3048/// __m256i _mm256_blend_epi32(__m256i V1, __m256i V2, const int M);3049/// \endcode3050///3051/// This intrinsic corresponds to the \c VPBLENDDD instruction.3052///3053/// \param V13054/// A 256-bit vector of [8 x i32] containing source values.3055/// \param V23056/// A 256-bit vector of [8 x i32] containing source values.3057/// \param M3058/// An immediate 8-bit integer operand, with bits [7:0] specifying the3059/// source for each element of the result. The position of the mask bit3060/// corresponds to the index of a copied value. When a mask bit is 0, the3061/// element is copied from \a V1; otherwise, it is is copied from \a V2.3062/// \returns A 256-bit vector of [8 x i32] containing the result.3063#define _mm256_blend_epi32(V1, V2, M) \3064 ((__m256i)__builtin_ia32_pblendd256((__v8si)(__m256i)(V1), \3065 (__v8si)(__m256i)(V2), (int)(M)))3066 3067/// Broadcasts the low byte from the 128-bit integer vector in \a __X to all3068/// bytes of the 256-bit result.3069///3070/// \headerfile <immintrin.h>3071///3072/// This intrinsic corresponds to the \c VPBROADCASTB instruction.3073///3074/// \param __X3075/// A 128-bit integer vector whose low byte will be broadcast.3076/// \returns A 256-bit integer vector containing the result.3077static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3078_mm256_broadcastb_epi8(__m128i __X) {3079 return (__m256i)__builtin_shufflevector((__v16qi)__X, (__v16qi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);3080}3081 3082/// Broadcasts the low element from the 128-bit vector of [8 x i16] in \a __X3083/// to all elements of the result's 256-bit vector of [16 x i16].3084///3085/// \headerfile <immintrin.h>3086///3087/// This intrinsic corresponds to the \c VPBROADCASTW instruction.3088///3089/// \param __X3090/// A 128-bit vector of [8 x i16] whose low element will be broadcast.3091/// \returns A 256-bit vector of [16 x i16] containing the result.3092static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3093_mm256_broadcastw_epi16(__m128i __X) {3094 return (__m256i)__builtin_shufflevector((__v8hi)__X, (__v8hi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);3095}3096 3097/// Broadcasts the low element from the 128-bit vector of [4 x i32] in \a __X3098/// to all elements of the result's 256-bit vector of [8 x i32].3099///3100/// \headerfile <immintrin.h>3101///3102/// This intrinsic corresponds to the \c VPBROADCASTD instruction.3103///3104/// \param __X3105/// A 128-bit vector of [4 x i32] whose low element will be broadcast.3106/// \returns A 256-bit vector of [8 x i32] containing the result.3107static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3108_mm256_broadcastd_epi32(__m128i __X) {3109 return (__m256i)__builtin_shufflevector((__v4si)__X, (__v4si)__X, 0, 0, 0, 0, 0, 0, 0, 0);3110}3111 3112/// Broadcasts the low element from the 128-bit vector of [2 x i64] in \a __X3113/// to all elements of the result's 256-bit vector of [4 x i64].3114///3115/// \headerfile <immintrin.h>3116///3117/// This intrinsic corresponds to the \c VPBROADCASTQ instruction.3118///3119/// \param __X3120/// A 128-bit vector of [2 x i64] whose low element will be broadcast.3121/// \returns A 256-bit vector of [4 x i64] containing the result.3122static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3123_mm256_broadcastq_epi64(__m128i __X) {3124 return (__m256i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 0, 0, 0);3125}3126 3127/// Broadcasts the low byte from the 128-bit integer vector in \a __X to all3128/// bytes of the 128-bit result.3129///3130/// \headerfile <immintrin.h>3131///3132/// This intrinsic corresponds to the \c VPBROADCASTB instruction.3133///3134/// \param __X3135/// A 128-bit integer vector whose low byte will be broadcast.3136/// \returns A 128-bit integer vector containing the result.3137static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3138_mm_broadcastb_epi8(__m128i __X) {3139 return (__m128i)__builtin_shufflevector((__v16qi)__X, (__v16qi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);3140}3141 3142/// Broadcasts the low element from the 128-bit vector of [8 x i16] in3143/// \a __X to all elements of the result's 128-bit vector of [8 x i16].3144///3145/// \headerfile <immintrin.h>3146///3147/// This intrinsic corresponds to the \c VPBROADCASTW instruction.3148///3149/// \param __X3150/// A 128-bit vector of [8 x i16] whose low element will be broadcast.3151/// \returns A 128-bit vector of [8 x i16] containing the result.3152static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3153_mm_broadcastw_epi16(__m128i __X) {3154 return (__m128i)__builtin_shufflevector((__v8hi)__X, (__v8hi)__X, 0, 0, 0, 0, 0, 0, 0, 0);3155}3156 3157/// Broadcasts the low element from the 128-bit vector of [4 x i32] in \a __X3158/// to all elements of the result's vector of [4 x i32].3159///3160/// \headerfile <immintrin.h>3161///3162/// This intrinsic corresponds to the \c VPBROADCASTD instruction.3163///3164/// \param __X3165/// A 128-bit vector of [4 x i32] whose low element will be broadcast.3166/// \returns A 128-bit vector of [4 x i32] containing the result.3167static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3168_mm_broadcastd_epi32(__m128i __X) {3169 return (__m128i)__builtin_shufflevector((__v4si)__X, (__v4si)__X, 0, 0, 0, 0);3170}3171 3172/// Broadcasts the low element from the 128-bit vector of [2 x i64] in \a __X3173/// to both elements of the result's 128-bit vector of [2 x i64].3174///3175/// \headerfile <immintrin.h>3176///3177/// This intrinsic corresponds to the \c VPBROADCASTQ instruction.3178///3179/// \param __X3180/// A 128-bit vector of [2 x i64] whose low element will be broadcast.3181/// \returns A 128-bit vector of [2 x i64] containing the result.3182static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3183_mm_broadcastq_epi64(__m128i __X) {3184 return (__m128i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 0);3185}3186 3187/// Sets the result's 256-bit vector of [8 x i32] to copies of elements of the3188/// 256-bit vector of [8 x i32] in \a __a as specified by indexes in the3189/// elements of the 256-bit vector of [8 x i32] in \a __b.3190///3191/// \code{.operation}3192/// FOR i := 0 TO 73193/// j := i*323194/// k := __b[j+2:j] * 323195/// result[j+31:j] := __a[k+31:k]3196/// ENDFOR3197/// \endcode3198///3199/// \headerfile <immintrin.h>3200///3201/// This intrinsic corresponds to the \c VPERMD instruction.3202///3203/// \param __a3204/// A 256-bit vector of [8 x i32] containing the source values.3205/// \param __b3206/// A 256-bit vector of [8 x i32] containing indexes of values to use from3207/// \a __a.3208/// \returns A 256-bit vector of [8 x i32] containing the result.3209static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3210_mm256_permutevar8x32_epi32(__m256i __a, __m256i __b) {3211 return (__m256i)__builtin_ia32_permvarsi256((__v8si)__a, (__v8si)__b);3212}3213 3214/// Sets the result's 256-bit vector of [4 x double] to copies of elements of3215/// the 256-bit vector of [4 x double] in \a V as specified by the3216/// immediate value \a M.3217///3218/// \code{.operation}3219/// FOR i := 0 TO 33220/// j := i*643221/// k := (M >> i*2)[1:0] * 643222/// result[j+63:j] := V[k+63:k]3223/// ENDFOR3224/// \endcode3225///3226/// \headerfile <immintrin.h>3227///3228/// \code3229/// __m256d _mm256_permute4x64_pd(__m256d V, const int M);3230/// \endcode3231///3232/// This intrinsic corresponds to the \c VPERMPD instruction.3233///3234/// \param V3235/// A 256-bit vector of [4 x double] containing the source values.3236/// \param M3237/// An immediate 8-bit value specifying which elements to copy from \a V.3238/// \a M[1:0] specifies the index in \a a for element 0 of the result,3239/// \a M[3:2] specifies the index for element 1, and so forth.3240/// \returns A 256-bit vector of [4 x double] containing the result.3241#define _mm256_permute4x64_pd(V, M) \3242 ((__m256d)__builtin_ia32_permdf256((__v4df)(__m256d)(V), (int)(M)))3243 3244/// Sets the result's 256-bit vector of [8 x float] to copies of elements of3245/// the 256-bit vector of [8 x float] in \a __a as specified by indexes in3246/// the elements of the 256-bit vector of [8 x i32] in \a __b.3247///3248/// \code{.operation}3249/// FOR i := 0 TO 73250/// j := i*323251/// k := __b[j+2:j] * 323252/// result[j+31:j] := __a[k+31:k]3253/// ENDFOR3254/// \endcode3255///3256/// \headerfile <immintrin.h>3257///3258/// This intrinsic corresponds to the \c VPERMPS instruction.3259///3260/// \param __a3261/// A 256-bit vector of [8 x float] containing the source values.3262/// \param __b3263/// A 256-bit vector of [8 x i32] containing indexes of values to use from3264/// \a __a.3265/// \returns A 256-bit vector of [8 x float] containing the result.3266static __inline__ __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR3267_mm256_permutevar8x32_ps(__m256 __a, __m256i __b) {3268 return (__m256)__builtin_ia32_permvarsf256((__v8sf)__a, (__v8si)__b);3269}3270 3271/// Sets the result's 256-bit vector of [4 x i64] result to copies of elements3272/// of the 256-bit vector of [4 x i64] in \a V as specified by the3273/// immediate value \a M.3274///3275/// \code{.operation}3276/// FOR i := 0 TO 33277/// j := i*643278/// k := (M >> i*2)[1:0] * 643279/// result[j+63:j] := V[k+63:k]3280/// ENDFOR3281/// \endcode3282///3283/// \headerfile <immintrin.h>3284///3285/// \code3286/// __m256i _mm256_permute4x64_epi64(__m256i V, const int M);3287/// \endcode3288///3289/// This intrinsic corresponds to the \c VPERMQ instruction.3290///3291/// \param V3292/// A 256-bit vector of [4 x i64] containing the source values.3293/// \param M3294/// An immediate 8-bit value specifying which elements to copy from \a V.3295/// \a M[1:0] specifies the index in \a a for element 0 of the result,3296/// \a M[3:2] specifies the index for element 1, and so forth.3297/// \returns A 256-bit vector of [4 x i64] containing the result.3298#define _mm256_permute4x64_epi64(V, M) \3299 ((__m256i)__builtin_ia32_permdi256((__v4di)(__m256i)(V), (int)(M)))3300 3301/// Sets each half of the 256-bit result either to zero or to one of the3302/// four possible 128-bit halves of the 256-bit vectors \a V1 and \a V2,3303/// as specified by the immediate value \a M.3304///3305/// \code{.operation}3306/// FOR i := 0 TO 13307/// j := i*1283308/// k := M >> (i*4)3309/// IF k[3] == 03310/// CASE (k[1:0]) OF3311/// 0: result[127+j:j] := V1[127:0]3312/// 1: result[127+j:j] := V1[255:128]3313/// 2: result[127+j:j] := V2[127:0]3314/// 3: result[127+j:j] := V2[255:128]3315/// ESAC3316/// ELSE3317/// result[127+j:j] := 03318/// FI3319/// ENDFOR3320/// \endcode3321///3322/// \headerfile <immintrin.h>3323///3324/// \code3325/// __m256i _mm256_permute2x128_si256(__m256i V1, __m256i V2, const int M);3326/// \endcode3327///3328/// This intrinsic corresponds to the \c VPERM2I128 instruction.3329///3330/// \param V13331/// A 256-bit integer vector containing source values.3332/// \param V23333/// A 256-bit integer vector containing source values.3334/// \param M3335/// An immediate value specifying how to form the result. Bits [3:0]3336/// control the lower half of the result, bits [7:4] control the upper half.3337/// Within each 4-bit control value, if bit 3 is 1, the result is zero,3338/// otherwise bits [1:0] determine the source as follows. \n3339/// 0: the lower half of \a V1 \n3340/// 1: the upper half of \a V1 \n3341/// 2: the lower half of \a V2 \n3342/// 3: the upper half of \a V23343/// \returns A 256-bit integer vector containing the result.3344#define _mm256_permute2x128_si256(V1, V2, M) \3345 ((__m256i)__builtin_ia32_permti256((__m256i)(V1), (__m256i)(V2), (int)(M)))3346 3347/// Extracts half of the 256-bit vector \a V to the 128-bit result. If bit 03348/// of the immediate \a M is zero, extracts the lower half of the result;3349/// otherwise, extracts the upper half.3350///3351/// \headerfile <immintrin.h>3352///3353/// \code3354/// __m128i _mm256_extracti128_si256(__m256i V, const int M);3355/// \endcode3356///3357/// This intrinsic corresponds to the \c VEXTRACTI128 instruction.3358///3359/// \param V3360/// A 256-bit integer vector containing the source values.3361/// \param M3362/// An immediate value specifying which half of \a V to extract.3363/// \returns A 128-bit integer vector containing the result.3364#define _mm256_extracti128_si256(V, M) \3365 ((__m128i)__builtin_ia32_extract128i256((__v4di)(__m256i)(V), (int)(M)))3366 3367/// Copies the 256-bit vector \a V1 to the result, then overwrites half of the3368/// result with the 128-bit vector \a V2. If bit 0 of the immediate \a M3369/// is zero, overwrites the lower half of the result; otherwise,3370/// overwrites the upper half.3371///3372/// \headerfile <immintrin.h>3373///3374/// \code3375/// __m256i _mm256_inserti128_si256(__m256i V1, __m128i V2, const int M);3376/// \endcode3377///3378/// This intrinsic corresponds to the \c VINSERTI128 instruction.3379///3380/// \param V13381/// A 256-bit integer vector containing a source value.3382/// \param V23383/// A 128-bit integer vector containing a source value.3384/// \param M3385/// An immediate value specifying where to put \a V2 in the result.3386/// \returns A 256-bit integer vector containing the result.3387#define _mm256_inserti128_si256(V1, V2, M) \3388 ((__m256i)__builtin_ia32_insert128i256((__v4di)(__m256i)(V1), \3389 (__v2di)(__m128i)(V2), (int)(M)))3390 3391/// Conditionally loads eight 32-bit integer elements from memory \a __X, if3392/// the most significant bit of the corresponding element in the mask3393/// \a __M is set; otherwise, sets that element of the result to zero.3394/// Returns the 256-bit [8 x i32] result.3395///3396/// \code{.operation}3397/// FOR i := 0 TO 73398/// j := i*323399/// IF __M[j+31] == 13400/// result[j+31:j] := Load32(__X+(i*4))3401/// ELSE3402/// result[j+31:j] := 03403/// FI3404/// ENDFOR3405/// \endcode3406///3407/// \headerfile <immintrin.h>3408///3409/// This intrinsic corresponds to the \c VPMASKMOVD instruction.3410///3411/// \param __X3412/// A pointer to the memory used for loading values.3413/// \param __M3414/// A 256-bit vector of [8 x i32] containing the mask bits.3415/// \returns A 256-bit vector of [8 x i32] containing the loaded or zeroed3416/// elements.3417static __inline__ __m256i __DEFAULT_FN_ATTRS2563418_mm256_maskload_epi32(int const *__X, __m256i __M)3419{3420 return (__m256i)__builtin_ia32_maskloadd256((const __v8si *)__X, (__v8si)__M);3421}3422 3423/// Conditionally loads four 64-bit integer elements from memory \a __X, if3424/// the most significant bit of the corresponding element in the mask3425/// \a __M is set; otherwise, sets that element of the result to zero.3426/// Returns the 256-bit [4 x i64] result.3427///3428/// \code{.operation}3429/// FOR i := 0 TO 33430/// j := i*643431/// IF __M[j+63] == 13432/// result[j+63:j] := Load64(__X+(i*8))3433/// ELSE3434/// result[j+63:j] := 03435/// FI3436/// ENDFOR3437/// \endcode3438///3439/// \headerfile <immintrin.h>3440///3441/// This intrinsic corresponds to the \c VPMASKMOVQ instruction.3442///3443/// \param __X3444/// A pointer to the memory used for loading values.3445/// \param __M3446/// A 256-bit vector of [4 x i64] containing the mask bits.3447/// \returns A 256-bit vector of [4 x i64] containing the loaded or zeroed3448/// elements.3449static __inline__ __m256i __DEFAULT_FN_ATTRS2563450_mm256_maskload_epi64(long long const *__X, __m256i __M)3451{3452 return (__m256i)__builtin_ia32_maskloadq256((const __v4di *)__X, (__v4di)__M);3453}3454 3455/// Conditionally loads four 32-bit integer elements from memory \a __X, if3456/// the most significant bit of the corresponding element in the mask3457/// \a __M is set; otherwise, sets that element of the result to zero.3458/// Returns the 128-bit [4 x i32] result.3459///3460/// \code{.operation}3461/// FOR i := 0 TO 33462/// j := i*323463/// IF __M[j+31] == 13464/// result[j+31:j] := Load32(__X+(i*4))3465/// ELSE3466/// result[j+31:j] := 03467/// FI3468/// ENDFOR3469/// \endcode3470///3471/// \headerfile <immintrin.h>3472///3473/// This intrinsic corresponds to the \c VPMASKMOVD instruction.3474///3475/// \param __X3476/// A pointer to the memory used for loading values.3477/// \param __M3478/// A 128-bit vector of [4 x i32] containing the mask bits.3479/// \returns A 128-bit vector of [4 x i32] containing the loaded or zeroed3480/// elements.3481static __inline__ __m128i __DEFAULT_FN_ATTRS1283482_mm_maskload_epi32(int const *__X, __m128i __M)3483{3484 return (__m128i)__builtin_ia32_maskloadd((const __v4si *)__X, (__v4si)__M);3485}3486 3487/// Conditionally loads two 64-bit integer elements from memory \a __X, if3488/// the most significant bit of the corresponding element in the mask3489/// \a __M is set; otherwise, sets that element of the result to zero.3490/// Returns the 128-bit [2 x i64] result.3491///3492/// \code{.operation}3493/// FOR i := 0 TO 13494/// j := i*643495/// IF __M[j+63] == 13496/// result[j+63:j] := Load64(__X+(i*8))3497/// ELSE3498/// result[j+63:j] := 03499/// FI3500/// ENDFOR3501/// \endcode3502///3503/// \headerfile <immintrin.h>3504///3505/// This intrinsic corresponds to the \c VPMASKMOVQ instruction.3506///3507/// \param __X3508/// A pointer to the memory used for loading values.3509/// \param __M3510/// A 128-bit vector of [2 x i64] containing the mask bits.3511/// \returns A 128-bit vector of [2 x i64] containing the loaded or zeroed3512/// elements.3513static __inline__ __m128i __DEFAULT_FN_ATTRS1283514_mm_maskload_epi64(long long const *__X, __m128i __M)3515{3516 return (__m128i)__builtin_ia32_maskloadq((const __v2di *)__X, (__v2di)__M);3517}3518 3519/// Conditionally stores eight 32-bit integer elements from the 256-bit vector3520/// of [8 x i32] in \a __Y to memory \a __X, if the most significant bit of3521/// the corresponding element in the mask \a __M is set; otherwise, the3522/// memory element is unchanged.3523///3524/// \code{.operation}3525/// FOR i := 0 TO 73526/// j := i*323527/// IF __M[j+31] == 13528/// Store32(__X+(i*4), __Y[j+31:j])3529/// FI3530/// ENDFOR3531/// \endcode3532///3533/// \headerfile <immintrin.h>3534///3535/// This intrinsic corresponds to the \c VPMASKMOVD instruction.3536///3537/// \param __X3538/// A pointer to the memory used for storing values.3539/// \param __M3540/// A 256-bit vector of [8 x i32] containing the mask bits.3541/// \param __Y3542/// A 256-bit vector of [8 x i32] containing the values to store.3543static __inline__ void __DEFAULT_FN_ATTRS2563544_mm256_maskstore_epi32(int *__X, __m256i __M, __m256i __Y)3545{3546 __builtin_ia32_maskstored256((__v8si *)__X, (__v8si)__M, (__v8si)__Y);3547}3548 3549/// Conditionally stores four 64-bit integer elements from the 256-bit vector3550/// of [4 x i64] in \a __Y to memory \a __X, if the most significant bit of3551/// the corresponding element in the mask \a __M is set; otherwise, the3552/// memory element is unchanged.3553///3554/// \code{.operation}3555/// FOR i := 0 TO 33556/// j := i*643557/// IF __M[j+63] == 13558/// Store64(__X+(i*8), __Y[j+63:j])3559/// FI3560/// ENDFOR3561/// \endcode3562///3563/// \headerfile <immintrin.h>3564///3565/// This intrinsic corresponds to the \c VPMASKMOVQ instruction.3566///3567/// \param __X3568/// A pointer to the memory used for storing values.3569/// \param __M3570/// A 256-bit vector of [4 x i64] containing the mask bits.3571/// \param __Y3572/// A 256-bit vector of [4 x i64] containing the values to store.3573static __inline__ void __DEFAULT_FN_ATTRS2563574_mm256_maskstore_epi64(long long *__X, __m256i __M, __m256i __Y)3575{3576 __builtin_ia32_maskstoreq256((__v4di *)__X, (__v4di)__M, (__v4di)__Y);3577}3578 3579/// Conditionally stores four 32-bit integer elements from the 128-bit vector3580/// of [4 x i32] in \a __Y to memory \a __X, if the most significant bit of3581/// the corresponding element in the mask \a __M is set; otherwise, the3582/// memory element is unchanged.3583///3584/// \code{.operation}3585/// FOR i := 0 TO 33586/// j := i*323587/// IF __M[j+31] == 13588/// Store32(__X+(i*4), __Y[j+31:j])3589/// FI3590/// ENDFOR3591/// \endcode3592///3593/// \headerfile <immintrin.h>3594///3595/// This intrinsic corresponds to the \c VPMASKMOVD instruction.3596///3597/// \param __X3598/// A pointer to the memory used for storing values.3599/// \param __M3600/// A 128-bit vector of [4 x i32] containing the mask bits.3601/// \param __Y3602/// A 128-bit vector of [4 x i32] containing the values to store.3603static __inline__ void __DEFAULT_FN_ATTRS1283604_mm_maskstore_epi32(int *__X, __m128i __M, __m128i __Y)3605{3606 __builtin_ia32_maskstored((__v4si *)__X, (__v4si)__M, (__v4si)__Y);3607}3608 3609/// Conditionally stores two 64-bit integer elements from the 128-bit vector3610/// of [2 x i64] in \a __Y to memory \a __X, if the most significant bit of3611/// the corresponding element in the mask \a __M is set; otherwise, the3612/// memory element is unchanged.3613///3614/// \code{.operation}3615/// FOR i := 0 TO 13616/// j := i*643617/// IF __M[j+63] == 13618/// Store64(__X+(i*8), __Y[j+63:j])3619/// FI3620/// ENDFOR3621/// \endcode3622///3623/// \headerfile <immintrin.h>3624///3625/// This intrinsic corresponds to the \c VPMASKMOVQ instruction.3626///3627/// \param __X3628/// A pointer to the memory used for storing values.3629/// \param __M3630/// A 128-bit vector of [2 x i64] containing the mask bits.3631/// \param __Y3632/// A 128-bit vector of [2 x i64] containing the values to store.3633static __inline__ void __DEFAULT_FN_ATTRS1283634_mm_maskstore_epi64(long long *__X, __m128i __M, __m128i __Y)3635{3636 __builtin_ia32_maskstoreq(( __v2di *)__X, (__v2di)__M, (__v2di)__Y);3637}3638 3639/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __X3640/// left by the number of bits given in the corresponding element of the3641/// 256-bit vector of [8 x i32] in \a __Y, shifting in zero bits, and3642/// returns the result. If the shift count for any element is greater than3643/// 31, the result for that element is zero.3644///3645/// \headerfile <immintrin.h>3646///3647/// This intrinsic corresponds to the \c VPSLLVD instruction.3648///3649/// \param __X3650/// A 256-bit vector of [8 x i32] to be shifted.3651/// \param __Y3652/// A 256-bit vector of [8 x i32] containing the unsigned shift counts (in3653/// bits).3654/// \returns A 256-bit vector of [8 x i32] containing the result.3655static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3656_mm256_sllv_epi32(__m256i __X, __m256i __Y)3657{3658 return (__m256i)__builtin_ia32_psllv8si((__v8si)__X, (__v8si)__Y);3659}3660 3661/// Shifts each 32-bit element of the 128-bit vector of [4 x i32] in \a __X3662/// left by the number of bits given in the corresponding element of the3663/// 128-bit vector of [4 x i32] in \a __Y, shifting in zero bits, and3664/// returns the result. If the shift count for any element is greater than3665/// 31, the result for that element is zero.3666///3667/// \headerfile <immintrin.h>3668///3669/// This intrinsic corresponds to the \c VPSLLVD instruction.3670///3671/// \param __X3672/// A 128-bit vector of [4 x i32] to be shifted.3673/// \param __Y3674/// A 128-bit vector of [4 x i32] containing the unsigned shift counts (in3675/// bits).3676/// \returns A 128-bit vector of [4 x i32] containing the result.3677static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3678_mm_sllv_epi32(__m128i __X, __m128i __Y)3679{3680 return (__m128i)__builtin_ia32_psllv4si((__v4si)__X, (__v4si)__Y);3681}3682 3683/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __X3684/// left by the number of bits given in the corresponding element of the3685/// 128-bit vector of [4 x i64] in \a __Y, shifting in zero bits, and3686/// returns the result. If the shift count for any element is greater than3687/// 63, the result for that element is zero.3688///3689/// \headerfile <immintrin.h>3690///3691/// This intrinsic corresponds to the \c VPSLLVQ instruction.3692///3693/// \param __X3694/// A 256-bit vector of [4 x i64] to be shifted.3695/// \param __Y3696/// A 256-bit vector of [4 x i64] containing the unsigned shift counts (in3697/// bits).3698/// \returns A 256-bit vector of [4 x i64] containing the result.3699static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3700_mm256_sllv_epi64(__m256i __X, __m256i __Y)3701{3702 return (__m256i)__builtin_ia32_psllv4di((__v4di)__X, (__v4di)__Y);3703}3704 3705/// Shifts each 64-bit element of the 128-bit vector of [2 x i64] in \a __X3706/// left by the number of bits given in the corresponding element of the3707/// 128-bit vector of [2 x i64] in \a __Y, shifting in zero bits, and3708/// returns the result. If the shift count for any element is greater than3709/// 63, the result for that element is zero.3710///3711/// \headerfile <immintrin.h>3712///3713/// This intrinsic corresponds to the \c VPSLLVQ instruction.3714///3715/// \param __X3716/// A 128-bit vector of [2 x i64] to be shifted.3717/// \param __Y3718/// A 128-bit vector of [2 x i64] containing the unsigned shift counts (in3719/// bits).3720/// \returns A 128-bit vector of [2 x i64] containing the result.3721static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3722_mm_sllv_epi64(__m128i __X, __m128i __Y)3723{3724 return (__m128i)__builtin_ia32_psllv2di((__v2di)__X, (__v2di)__Y);3725}3726 3727/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __X3728/// right by the number of bits given in the corresponding element of the3729/// 256-bit vector of [8 x i32] in \a __Y, shifting in sign bits, and3730/// returns the result. If the shift count for any element is greater than3731/// 31, the result for that element is 0 or -1 according to the sign bit3732/// for that element.3733///3734/// \headerfile <immintrin.h>3735///3736/// This intrinsic corresponds to the \c VPSRAVD instruction.3737///3738/// \param __X3739/// A 256-bit vector of [8 x i32] to be shifted.3740/// \param __Y3741/// A 256-bit vector of [8 x i32] containing the unsigned shift counts (in3742/// bits).3743/// \returns A 256-bit vector of [8 x i32] containing the result.3744static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3745_mm256_srav_epi32(__m256i __X, __m256i __Y)3746{3747 return (__m256i)__builtin_ia32_psrav8si((__v8si)__X, (__v8si)__Y);3748}3749 3750/// Shifts each 32-bit element of the 128-bit vector of [4 x i32] in \a __X3751/// right by the number of bits given in the corresponding element of the3752/// 128-bit vector of [4 x i32] in \a __Y, shifting in sign bits, and3753/// returns the result. If the shift count for any element is greater than3754/// 31, the result for that element is 0 or -1 according to the sign bit3755/// for that element.3756///3757/// \headerfile <immintrin.h>3758///3759/// This intrinsic corresponds to the \c VPSRAVD instruction.3760///3761/// \param __X3762/// A 128-bit vector of [4 x i32] to be shifted.3763/// \param __Y3764/// A 128-bit vector of [4 x i32] containing the unsigned shift counts (in3765/// bits).3766/// \returns A 128-bit vector of [4 x i32] containing the result.3767static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3768_mm_srav_epi32(__m128i __X, __m128i __Y)3769{3770 return (__m128i)__builtin_ia32_psrav4si((__v4si)__X, (__v4si)__Y);3771}3772 3773/// Shifts each 32-bit element of the 256-bit vector of [8 x i32] in \a __X3774/// right by the number of bits given in the corresponding element of the3775/// 256-bit vector of [8 x i32] in \a __Y, shifting in zero bits, and3776/// returns the result. If the shift count for any element is greater than3777/// 31, the result for that element is zero.3778///3779/// \headerfile <immintrin.h>3780///3781/// This intrinsic corresponds to the \c VPSRLVD instruction.3782///3783/// \param __X3784/// A 256-bit vector of [8 x i32] to be shifted.3785/// \param __Y3786/// A 256-bit vector of [8 x i32] containing the unsigned shift counts (in3787/// bits).3788/// \returns A 256-bit vector of [8 x i32] containing the result.3789static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3790_mm256_srlv_epi32(__m256i __X, __m256i __Y)3791{3792 return (__m256i)__builtin_ia32_psrlv8si((__v8si)__X, (__v8si)__Y);3793}3794 3795/// Shifts each 32-bit element of the 128-bit vector of [4 x i32] in \a __X3796/// right by the number of bits given in the corresponding element of the3797/// 128-bit vector of [4 x i32] in \a __Y, shifting in zero bits, and3798/// returns the result. If the shift count for any element is greater than3799/// 31, the result for that element is zero.3800///3801/// \headerfile <immintrin.h>3802///3803/// This intrinsic corresponds to the \c VPSRLVD instruction.3804///3805/// \param __X3806/// A 128-bit vector of [4 x i32] to be shifted.3807/// \param __Y3808/// A 128-bit vector of [4 x i32] containing the unsigned shift counts (in3809/// bits).3810/// \returns A 128-bit vector of [4 x i32] containing the result.3811static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3812_mm_srlv_epi32(__m128i __X, __m128i __Y)3813{3814 return (__m128i)__builtin_ia32_psrlv4si((__v4si)__X, (__v4si)__Y);3815}3816 3817/// Shifts each 64-bit element of the 256-bit vector of [4 x i64] in \a __X3818/// right by the number of bits given in the corresponding element of the3819/// 128-bit vector of [4 x i64] in \a __Y, shifting in zero bits, and3820/// returns the result. If the shift count for any element is greater than3821/// 63, the result for that element is zero.3822///3823/// \headerfile <immintrin.h>3824///3825/// This intrinsic corresponds to the \c VPSRLVQ instruction.3826///3827/// \param __X3828/// A 256-bit vector of [4 x i64] to be shifted.3829/// \param __Y3830/// A 256-bit vector of [4 x i64] containing the unsigned shift counts (in3831/// bits).3832/// \returns A 256-bit vector of [4 x i64] containing the result.3833static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR3834_mm256_srlv_epi64(__m256i __X, __m256i __Y)3835{3836 return (__m256i)__builtin_ia32_psrlv4di((__v4di)__X, (__v4di)__Y);3837}3838 3839/// Shifts each 64-bit element of the 128-bit vector of [2 x i64] in \a __X3840/// right by the number of bits given in the corresponding element of the3841/// 128-bit vector of [2 x i64] in \a __Y, shifting in zero bits, and3842/// returns the result. If the shift count for any element is greater than3843/// 63, the result for that element is zero.3844///3845/// \headerfile <immintrin.h>3846///3847/// This intrinsic corresponds to the \c VPSRLVQ instruction.3848///3849/// \param __X3850/// A 128-bit vector of [2 x i64] to be shifted.3851/// \param __Y3852/// A 128-bit vector of [2 x i64] containing the unsigned shift counts (in3853/// bits).3854/// \returns A 128-bit vector of [2 x i64] containing the result.3855static __inline__ __m128i __DEFAULT_FN_ATTRS128_CONSTEXPR3856_mm_srlv_epi64(__m128i __X, __m128i __Y)3857{3858 return (__m128i)__builtin_ia32_psrlv2di((__v2di)__X, (__v2di)__Y);3859}3860 3861/// Conditionally gathers two 64-bit floating-point values, either from the3862/// 128-bit vector of [2 x double] in \a a, or from memory \a m using scaled3863/// indexes from the 128-bit vector of [4 x i32] in \a i. The 128-bit vector3864/// of [2 x double] in \a mask determines the source for each element.3865///3866/// \code{.operation}3867/// FOR element := 0 to 13868/// j := element*643869/// k := element*323870/// IF mask[j+63] == 03871/// result[j+63:j] := a[j+63:j]3872/// ELSE3873/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)3874/// FI3875/// ENDFOR3876/// \endcode3877///3878/// \headerfile <immintrin.h>3879///3880/// \code3881/// __m128d _mm_mask_i32gather_pd(__m128d a, const double *m, __m128i i,3882/// __m128d mask, const int s);3883/// \endcode3884///3885/// This intrinsic corresponds to the \c VGATHERDPD instruction.3886///3887/// \param a3888/// A 128-bit vector of [2 x double] used as the source when a mask bit is3889/// zero.3890/// \param m3891/// A pointer to the memory used for loading values.3892/// \param i3893/// A 128-bit vector of [4 x i32] containing signed indexes into \a m. Only3894/// the first two elements are used.3895/// \param mask3896/// A 128-bit vector of [2 x double] containing the mask. The most3897/// significant bit of each element in the mask vector represents the mask3898/// bits. If a mask bit is zero, the corresponding value from vector \a a3899/// is gathered; otherwise the value is loaded from memory.3900/// \param s3901/// A literal constant scale factor for the indexes in \a i. Must be3902/// 1, 2, 4, or 8.3903/// \returns A 128-bit vector of [2 x double] containing the gathered values.3904#define _mm_mask_i32gather_pd(a, m, i, mask, s) \3905 ((__m128d)__builtin_ia32_gatherd_pd((__v2df)(__m128i)(a), \3906 (double const *)(m), \3907 (__v4si)(__m128i)(i), \3908 (__v2df)(__m128d)(mask), (s)))3909 3910/// Conditionally gathers four 64-bit floating-point values, either from the3911/// 256-bit vector of [4 x double] in \a a, or from memory \a m using scaled3912/// indexes from the 128-bit vector of [4 x i32] in \a i. The 256-bit vector3913/// of [4 x double] in \a mask determines the source for each element.3914///3915/// \code{.operation}3916/// FOR element := 0 to 33917/// j := element*643918/// k := element*323919/// IF mask[j+63] == 03920/// result[j+63:j] := a[j+63:j]3921/// ELSE3922/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)3923/// FI3924/// ENDFOR3925/// \endcode3926///3927/// \headerfile <immintrin.h>3928///3929/// \code3930/// __m256d _mm256_mask_i32gather_pd(__m256d a, const double *m, __m128i i,3931/// __m256d mask, const int s);3932/// \endcode3933///3934/// This intrinsic corresponds to the \c VGATHERDPD instruction.3935///3936/// \param a3937/// A 256-bit vector of [4 x double] used as the source when a mask bit is3938/// zero.3939/// \param m3940/// A pointer to the memory used for loading values.3941/// \param i3942/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.3943/// \param mask3944/// A 256-bit vector of [4 x double] containing the mask. The most3945/// significant bit of each element in the mask vector represents the mask3946/// bits. If a mask bit is zero, the corresponding value from vector \a a3947/// is gathered; otherwise the value is loaded from memory.3948/// \param s3949/// A literal constant scale factor for the indexes in \a i. Must be3950/// 1, 2, 4, or 8.3951/// \returns A 256-bit vector of [4 x double] containing the gathered values.3952#define _mm256_mask_i32gather_pd(a, m, i, mask, s) \3953 ((__m256d)__builtin_ia32_gatherd_pd256((__v4df)(__m256d)(a), \3954 (double const *)(m), \3955 (__v4si)(__m128i)(i), \3956 (__v4df)(__m256d)(mask), (s)))3957 3958/// Conditionally gathers two 64-bit floating-point values, either from the3959/// 128-bit vector of [2 x double] in \a a, or from memory \a m using scaled3960/// indexes from the 128-bit vector of [2 x i64] in \a i. The 128-bit vector3961/// of [2 x double] in \a mask determines the source for each element.3962///3963/// \code{.operation}3964/// FOR element := 0 to 13965/// j := element*643966/// k := element*643967/// IF mask[j+63] == 03968/// result[j+63:j] := a[j+63:j]3969/// ELSE3970/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)3971/// FI3972/// ENDFOR3973/// \endcode3974///3975/// \headerfile <immintrin.h>3976///3977/// \code3978/// __m128d _mm_mask_i64gather_pd(__m128d a, const double *m, __m128i i,3979/// __m128d mask, const int s);3980/// \endcode3981///3982/// This intrinsic corresponds to the \c VGATHERQPD instruction.3983///3984/// \param a3985/// A 128-bit vector of [2 x double] used as the source when a mask bit is3986/// zero.3987/// \param m3988/// A pointer to the memory used for loading values.3989/// \param i3990/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.3991/// \param mask3992/// A 128-bit vector of [2 x double] containing the mask. The most3993/// significant bit of each element in the mask vector represents the mask3994/// bits. If a mask bit is zero, the corresponding value from vector \a a3995/// is gathered; otherwise the value is loaded from memory.3996/// \param s3997/// A literal constant scale factor for the indexes in \a i. Must be3998/// 1, 2, 4, or 8.3999/// \returns A 128-bit vector of [2 x double] containing the gathered values.4000#define _mm_mask_i64gather_pd(a, m, i, mask, s) \4001 ((__m128d)__builtin_ia32_gatherq_pd((__v2df)(__m128d)(a), \4002 (double const *)(m), \4003 (__v2di)(__m128i)(i), \4004 (__v2df)(__m128d)(mask), (s)))4005 4006/// Conditionally gathers four 64-bit floating-point values, either from the4007/// 256-bit vector of [4 x double] in \a a, or from memory \a m using scaled4008/// indexes from the 256-bit vector of [4 x i64] in \a i. The 256-bit vector4009/// of [4 x double] in \a mask determines the source for each element.4010///4011/// \code{.operation}4012/// FOR element := 0 to 34013/// j := element*644014/// k := element*644015/// IF mask[j+63] == 04016/// result[j+63:j] := a[j+63:j]4017/// ELSE4018/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)4019/// FI4020/// ENDFOR4021/// \endcode4022///4023/// \headerfile <immintrin.h>4024///4025/// \code4026/// __m256d _mm256_mask_i64gather_pd(__m256d a, const double *m, __m256i i,4027/// __m256d mask, const int s);4028/// \endcode4029///4030/// This intrinsic corresponds to the \c VGATHERQPD instruction.4031///4032/// \param a4033/// A 256-bit vector of [4 x double] used as the source when a mask bit is4034/// zero.4035/// \param m4036/// A pointer to the memory used for loading values.4037/// \param i4038/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4039/// \param mask4040/// A 256-bit vector of [4 x double] containing the mask. The most4041/// significant bit of each element in the mask vector represents the mask4042/// bits. If a mask bit is zero, the corresponding value from vector \a a4043/// is gathered; otherwise the value is loaded from memory.4044/// \param s4045/// A literal constant scale factor for the indexes in \a i. Must be4046/// 1, 2, 4, or 8.4047/// \returns A 256-bit vector of [4 x double] containing the gathered values.4048#define _mm256_mask_i64gather_pd(a, m, i, mask, s) \4049 ((__m256d)__builtin_ia32_gatherq_pd256((__v4df)(__m256d)(a), \4050 (double const *)(m), \4051 (__v4di)(__m256i)(i), \4052 (__v4df)(__m256d)(mask), (s)))4053 4054/// Conditionally gathers four 32-bit floating-point values, either from the4055/// 128-bit vector of [4 x float] in \a a, or from memory \a m using scaled4056/// indexes from the 128-bit vector of [4 x i32] in \a i. The 128-bit vector4057/// of [4 x float] in \a mask determines the source for each element.4058///4059/// \code{.operation}4060/// FOR element := 0 to 34061/// j := element*324062/// k := element*324063/// IF mask[j+31] == 04064/// result[j+31:j] := a[j+31:j]4065/// ELSE4066/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4067/// FI4068/// ENDFOR4069/// \endcode4070///4071/// \headerfile <immintrin.h>4072///4073/// \code4074/// __m128 _mm_mask_i32gather_ps(__m128 a, const float *m, __m128i i,4075/// __m128 mask, const int s);4076/// \endcode4077///4078/// This intrinsic corresponds to the \c VGATHERDPS instruction.4079///4080/// \param a4081/// A 128-bit vector of [4 x float] used as the source when a mask bit is4082/// zero.4083/// \param m4084/// A pointer to the memory used for loading values.4085/// \param i4086/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4087/// \param mask4088/// A 128-bit vector of [4 x float] containing the mask. The most4089/// significant bit of each element in the mask vector represents the mask4090/// bits. If a mask bit is zero, the corresponding value from vector \a a4091/// is gathered; otherwise the value is loaded from memory.4092/// \param s4093/// A literal constant scale factor for the indexes in \a i. Must be4094/// 1, 2, 4, or 8.4095/// \returns A 128-bit vector of [4 x float] containing the gathered values.4096#define _mm_mask_i32gather_ps(a, m, i, mask, s) \4097 ((__m128)__builtin_ia32_gatherd_ps((__v4sf)(__m128)(a), \4098 (float const *)(m), \4099 (__v4si)(__m128i)(i), \4100 (__v4sf)(__m128)(mask), (s)))4101 4102/// Conditionally gathers eight 32-bit floating-point values, either from the4103/// 256-bit vector of [8 x float] in \a a, or from memory \a m using scaled4104/// indexes from the 256-bit vector of [8 x i32] in \a i. The 256-bit vector4105/// of [8 x float] in \a mask determines the source for each element.4106///4107/// \code{.operation}4108/// FOR element := 0 to 74109/// j := element*324110/// k := element*324111/// IF mask[j+31] == 04112/// result[j+31:j] := a[j+31:j]4113/// ELSE4114/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4115/// FI4116/// ENDFOR4117/// \endcode4118///4119/// \headerfile <immintrin.h>4120///4121/// \code4122/// __m256 _mm256_mask_i32gather_ps(__m256 a, const float *m, __m256i i,4123/// __m256 mask, const int s);4124/// \endcode4125///4126/// This intrinsic corresponds to the \c VGATHERDPS instruction.4127///4128/// \param a4129/// A 256-bit vector of [8 x float] used as the source when a mask bit is4130/// zero.4131/// \param m4132/// A pointer to the memory used for loading values.4133/// \param i4134/// A 256-bit vector of [8 x i32] containing signed indexes into \a m.4135/// \param mask4136/// A 256-bit vector of [8 x float] containing the mask. The most4137/// significant bit of each element in the mask vector represents the mask4138/// bits. If a mask bit is zero, the corresponding value from vector \a a4139/// is gathered; otherwise the value is loaded from memory.4140/// \param s4141/// A literal constant scale factor for the indexes in \a i. Must be4142/// 1, 2, 4, or 8.4143/// \returns A 256-bit vector of [8 x float] containing the gathered values.4144#define _mm256_mask_i32gather_ps(a, m, i, mask, s) \4145 ((__m256)__builtin_ia32_gatherd_ps256((__v8sf)(__m256)(a), \4146 (float const *)(m), \4147 (__v8si)(__m256i)(i), \4148 (__v8sf)(__m256)(mask), (s)))4149 4150/// Conditionally gathers two 32-bit floating-point values, either from the4151/// 128-bit vector of [4 x float] in \a a, or from memory \a m using scaled4152/// indexes from the 128-bit vector of [2 x i64] in \a i. The 128-bit vector4153/// of [4 x float] in \a mask determines the source for the lower two4154/// elements. The upper two elements of the result are zeroed.4155///4156/// \code{.operation}4157/// FOR element := 0 to 14158/// j := element*324159/// k := element*644160/// IF mask[j+31] == 04161/// result[j+31:j] := a[j+31:j]4162/// ELSE4163/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4164/// FI4165/// ENDFOR4166/// result[127:64] := 04167/// \endcode4168///4169/// \headerfile <immintrin.h>4170///4171/// \code4172/// __m128 _mm_mask_i64gather_ps(__m128 a, const float *m, __m128i i,4173/// __m128 mask, const int s);4174/// \endcode4175///4176/// This intrinsic corresponds to the \c VGATHERQPS instruction.4177///4178/// \param a4179/// A 128-bit vector of [4 x float] used as the source when a mask bit is4180/// zero. Only the first two elements are used.4181/// \param m4182/// A pointer to the memory used for loading values.4183/// \param i4184/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.4185/// \param mask4186/// A 128-bit vector of [4 x float] containing the mask. The most4187/// significant bit of each element in the mask vector represents the mask4188/// bits. If a mask bit is zero, the corresponding value from vector \a a4189/// is gathered; otherwise the value is loaded from memory. Only the first4190/// two elements are used.4191/// \param s4192/// A literal constant scale factor for the indexes in \a i. Must be4193/// 1, 2, 4, or 8.4194/// \returns A 128-bit vector of [4 x float] containing the gathered values.4195#define _mm_mask_i64gather_ps(a, m, i, mask, s) \4196 ((__m128)__builtin_ia32_gatherq_ps((__v4sf)(__m128)(a), \4197 (float const *)(m), \4198 (__v2di)(__m128i)(i), \4199 (__v4sf)(__m128)(mask), (s)))4200 4201/// Conditionally gathers four 32-bit floating-point values, either from the4202/// 128-bit vector of [4 x float] in \a a, or from memory \a m using scaled4203/// indexes from the 256-bit vector of [4 x i64] in \a i. The 128-bit vector4204/// of [4 x float] in \a mask determines the source for each element.4205///4206/// \code{.operation}4207/// FOR element := 0 to 34208/// j := element*324209/// k := element*644210/// IF mask[j+31] == 04211/// result[j+31:j] := a[j+31:j]4212/// ELSE4213/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4214/// FI4215/// ENDFOR4216/// \endcode4217///4218/// \headerfile <immintrin.h>4219///4220/// \code4221/// __m128 _mm256_mask_i64gather_ps(__m128 a, const float *m, __m256i i,4222/// __m128 mask, const int s);4223/// \endcode4224///4225/// This intrinsic corresponds to the \c VGATHERQPS instruction.4226///4227/// \param a4228/// A 128-bit vector of [4 x float] used as the source when a mask bit is4229/// zero.4230/// \param m4231/// A pointer to the memory used for loading values.4232/// \param i4233/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4234/// \param mask4235/// A 128-bit vector of [4 x float] containing the mask. The most4236/// significant bit of each element in the mask vector represents the mask4237/// bits. If a mask bit is zero, the corresponding value from vector \a a4238/// is gathered; otherwise the value is loaded from memory.4239/// \param s4240/// A literal constant scale factor for the indexes in \a i. Must be4241/// 1, 2, 4, or 8.4242/// \returns A 128-bit vector of [4 x float] containing the gathered values.4243#define _mm256_mask_i64gather_ps(a, m, i, mask, s) \4244 ((__m128)__builtin_ia32_gatherq_ps256((__v4sf)(__m128)(a), \4245 (float const *)(m), \4246 (__v4di)(__m256i)(i), \4247 (__v4sf)(__m128)(mask), (s)))4248 4249/// Conditionally gathers four 32-bit integer values, either from the4250/// 128-bit vector of [4 x i32] in \a a, or from memory \a m using scaled4251/// indexes from the 128-bit vector of [4 x i32] in \a i. The 128-bit vector4252/// of [4 x i32] in \a mask determines the source for each element.4253///4254/// \code{.operation}4255/// FOR element := 0 to 34256/// j := element*324257/// k := element*324258/// IF mask[j+31] == 04259/// result[j+31:j] := a[j+31:j]4260/// ELSE4261/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4262/// FI4263/// ENDFOR4264/// \endcode4265///4266/// \headerfile <immintrin.h>4267///4268/// \code4269/// __m128i _mm_mask_i32gather_epi32(__m128i a, const int *m, __m128i i,4270/// __m128i mask, const int s);4271/// \endcode4272///4273/// This intrinsic corresponds to the \c VPGATHERDD instruction.4274///4275/// \param a4276/// A 128-bit vector of [4 x i32] used as the source when a mask bit is4277/// zero.4278/// \param m4279/// A pointer to the memory used for loading values.4280/// \param i4281/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4282/// \param mask4283/// A 128-bit vector of [4 x i32] containing the mask. The most significant4284/// bit of each element in the mask vector represents the mask bits. If a4285/// mask bit is zero, the corresponding value from vector \a a is gathered;4286/// otherwise the value is loaded from memory.4287/// \param s4288/// A literal constant scale factor for the indexes in \a i. Must be4289/// 1, 2, 4, or 8.4290/// \returns A 128-bit vector of [4 x i32] containing the gathered values.4291#define _mm_mask_i32gather_epi32(a, m, i, mask, s) \4292 ((__m128i)__builtin_ia32_gatherd_d((__v4si)(__m128i)(a), \4293 (int const *)(m), \4294 (__v4si)(__m128i)(i), \4295 (__v4si)(__m128i)(mask), (s)))4296 4297/// Conditionally gathers eight 32-bit integer values, either from the4298/// 256-bit vector of [8 x i32] in \a a, or from memory \a m using scaled4299/// indexes from the 256-bit vector of [8 x i32] in \a i. The 256-bit vector4300/// of [8 x i32] in \a mask determines the source for each element.4301///4302/// \code{.operation}4303/// FOR element := 0 to 74304/// j := element*324305/// k := element*324306/// IF mask[j+31] == 04307/// result[j+31:j] := a[j+31:j]4308/// ELSE4309/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4310/// FI4311/// ENDFOR4312/// \endcode4313///4314/// \headerfile <immintrin.h>4315///4316/// \code4317/// __m256i _mm256_mask_i32gather_epi32(__m256i a, const int *m, __m256i i,4318/// __m256i mask, const int s);4319/// \endcode4320///4321/// This intrinsic corresponds to the \c VPGATHERDD instruction.4322///4323/// \param a4324/// A 256-bit vector of [8 x i32] used as the source when a mask bit is4325/// zero.4326/// \param m4327/// A pointer to the memory used for loading values.4328/// \param i4329/// A 256-bit vector of [8 x i32] containing signed indexes into \a m.4330/// \param mask4331/// A 256-bit vector of [8 x i32] containing the mask. The most significant4332/// bit of each element in the mask vector represents the mask bits. If a4333/// mask bit is zero, the corresponding value from vector \a a is gathered;4334/// otherwise the value is loaded from memory.4335/// \param s4336/// A literal constant scale factor for the indexes in \a i. Must be4337/// 1, 2, 4, or 8.4338/// \returns A 256-bit vector of [8 x i32] containing the gathered values.4339#define _mm256_mask_i32gather_epi32(a, m, i, mask, s) \4340 ((__m256i)__builtin_ia32_gatherd_d256((__v8si)(__m256i)(a), \4341 (int const *)(m), \4342 (__v8si)(__m256i)(i), \4343 (__v8si)(__m256i)(mask), (s)))4344 4345/// Conditionally gathers two 32-bit integer values, either from the4346/// 128-bit vector of [4 x i32] in \a a, or from memory \a m using scaled4347/// indexes from the 128-bit vector of [2 x i64] in \a i. The 128-bit vector4348/// of [4 x i32] in \a mask determines the source for the lower two4349/// elements. The upper two elements of the result are zeroed.4350///4351/// \code{.operation}4352/// FOR element := 0 to 14353/// j := element*324354/// k := element*644355/// IF mask[j+31] == 04356/// result[j+31:j] := a[j+31:j]4357/// ELSE4358/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4359/// FI4360/// ENDFOR4361/// result[127:64] := 04362/// \endcode4363///4364/// \headerfile <immintrin.h>4365///4366/// \code4367/// __m128i _mm_mask_i64gather_epi32(__m128i a, const int *m, __m128i i,4368/// __m128i mask, const int s);4369/// \endcode4370///4371/// This intrinsic corresponds to the \c VPGATHERQD instruction.4372///4373/// \param a4374/// A 128-bit vector of [4 x i32] used as the source when a mask bit is4375/// zero. Only the first two elements are used.4376/// \param m4377/// A pointer to the memory used for loading values.4378/// \param i4379/// A 128-bit vector of [2 x i64] containing indexes into \a m.4380/// \param mask4381/// A 128-bit vector of [4 x i32] containing the mask. The most significant4382/// bit of each element in the mask vector represents the mask bits. If a4383/// mask bit is zero, the corresponding value from vector \a a is gathered;4384/// otherwise the value is loaded from memory. Only the first two elements4385/// are used.4386/// \param s4387/// A literal constant scale factor for the indexes in \a i. Must be4388/// 1, 2, 4, or 8.4389/// \returns A 128-bit vector of [4 x i32] containing the gathered values.4390#define _mm_mask_i64gather_epi32(a, m, i, mask, s) \4391 ((__m128i)__builtin_ia32_gatherq_d((__v4si)(__m128i)(a), \4392 (int const *)(m), \4393 (__v2di)(__m128i)(i), \4394 (__v4si)(__m128i)(mask), (s)))4395 4396/// Conditionally gathers four 32-bit integer values, either from the4397/// 128-bit vector of [4 x i32] in \a a, or from memory \a m using scaled4398/// indexes from the 256-bit vector of [4 x i64] in \a i. The 128-bit vector4399/// of [4 x i32] in \a mask determines the source for each element.4400///4401/// \code{.operation}4402/// FOR element := 0 to 34403/// j := element*324404/// k := element*644405/// IF mask[j+31] == 04406/// result[j+31:j] := a[j+31:j]4407/// ELSE4408/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4409/// FI4410/// ENDFOR4411/// \endcode4412///4413/// \headerfile <immintrin.h>4414///4415/// \code4416/// __m128i _mm256_mask_i64gather_epi32(__m128i a, const int *m, __m256i i,4417/// __m128i mask, const int s);4418/// \endcode4419///4420/// This intrinsic corresponds to the \c VPGATHERQD instruction.4421///4422/// \param a4423/// A 128-bit vector of [4 x i32] used as the source when a mask bit is4424/// zero.4425/// \param m4426/// A pointer to the memory used for loading values.4427/// \param i4428/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4429/// \param mask4430/// A 128-bit vector of [4 x i32] containing the mask. The most significant4431/// bit of each element in the mask vector represents the mask bits. If a4432/// mask bit is zero, the corresponding value from vector \a a is gathered;4433/// otherwise the value is loaded from memory.4434/// \param s4435/// A literal constant scale factor for the indexes in \a i. Must be4436/// 1, 2, 4, or 8.4437/// \returns A 128-bit vector of [4 x i32] containing the gathered values.4438#define _mm256_mask_i64gather_epi32(a, m, i, mask, s) \4439 ((__m128i)__builtin_ia32_gatherq_d256((__v4si)(__m128i)(a), \4440 (int const *)(m), \4441 (__v4di)(__m256i)(i), \4442 (__v4si)(__m128i)(mask), (s)))4443 4444/// Conditionally gathers two 64-bit integer values, either from the4445/// 128-bit vector of [2 x i64] in \a a, or from memory \a m using scaled4446/// indexes from the 128-bit vector of [4 x i32] in \a i. The 128-bit vector4447/// of [2 x i64] in \a mask determines the source for each element.4448///4449/// \code{.operation}4450/// FOR element := 0 to 14451/// j := element*644452/// k := element*324453/// IF mask[j+63] == 04454/// result[j+63:j] := a[j+63:j]4455/// ELSE4456/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)4457/// FI4458/// ENDFOR4459/// \endcode4460///4461/// \headerfile <immintrin.h>4462///4463/// \code4464/// __m128i _mm_mask_i32gather_epi64(__m128i a, const long long *m, __m128i i,4465/// __m128i mask, const int s);4466/// \endcode4467///4468/// This intrinsic corresponds to the \c VPGATHERDQ instruction.4469///4470/// \param a4471/// A 128-bit vector of [2 x i64] used as the source when a mask bit is4472/// zero.4473/// \param m4474/// A pointer to the memory used for loading values.4475/// \param i4476/// A 128-bit vector of [4 x i32] containing signed indexes into \a m. Only4477/// the first two elements are used.4478/// \param mask4479/// A 128-bit vector of [2 x i64] containing the mask. The most significant4480/// bit of each element in the mask vector represents the mask bits. If a4481/// mask bit is zero, the corresponding value from vector \a a is gathered;4482/// otherwise the value is loaded from memory.4483/// \param s4484/// A literal constant scale factor for the indexes in \a i. Must be4485/// 1, 2, 4, or 8.4486/// \returns A 128-bit vector of [2 x i64] containing the gathered values.4487#define _mm_mask_i32gather_epi64(a, m, i, mask, s) \4488 ((__m128i)__builtin_ia32_gatherd_q((__v2di)(__m128i)(a), \4489 (long long const *)(m), \4490 (__v4si)(__m128i)(i), \4491 (__v2di)(__m128i)(mask), (s)))4492 4493/// Conditionally gathers four 64-bit integer values, either from the4494/// 256-bit vector of [4 x i64] in \a a, or from memory \a m using scaled4495/// indexes from the 128-bit vector of [4 x i32] in \a i. The 256-bit vector4496/// of [4 x i64] in \a mask determines the source for each element.4497///4498/// \code{.operation}4499/// FOR element := 0 to 34500/// j := element*644501/// k := element*324502/// IF mask[j+63] == 04503/// result[j+63:j] := a[j+63:j]4504/// ELSE4505/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)4506/// FI4507/// ENDFOR4508/// \endcode4509///4510/// \headerfile <immintrin.h>4511///4512/// \code4513/// __m256i _mm256_mask_i32gather_epi64(__m256i a, const long long *m,4514/// __m128i i, __m256i mask, const int s);4515/// \endcode4516///4517/// This intrinsic corresponds to the \c VPGATHERDQ instruction.4518///4519/// \param a4520/// A 256-bit vector of [4 x i64] used as the source when a mask bit is4521/// zero.4522/// \param m4523/// A pointer to the memory used for loading values.4524/// \param i4525/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4526/// \param mask4527/// A 256-bit vector of [4 x i64] containing the mask. The most significant4528/// bit of each element in the mask vector represents the mask bits. If a4529/// mask bit is zero, the corresponding value from vector \a a is gathered;4530/// otherwise the value is loaded from memory.4531/// \param s4532/// A literal constant scale factor for the indexes in \a i. Must be4533/// 1, 2, 4, or 8.4534/// \returns A 256-bit vector of [4 x i64] containing the gathered values.4535#define _mm256_mask_i32gather_epi64(a, m, i, mask, s) \4536 ((__m256i)__builtin_ia32_gatherd_q256((__v4di)(__m256i)(a), \4537 (long long const *)(m), \4538 (__v4si)(__m128i)(i), \4539 (__v4di)(__m256i)(mask), (s)))4540 4541/// Conditionally gathers two 64-bit integer values, either from the4542/// 128-bit vector of [2 x i64] in \a a, or from memory \a m using scaled4543/// indexes from the 128-bit vector of [2 x i64] in \a i. The 128-bit vector4544/// of [2 x i64] in \a mask determines the source for each element.4545///4546/// \code{.operation}4547/// FOR element := 0 to 14548/// j := element*644549/// k := element*644550/// IF mask[j+63] == 04551/// result[j+63:j] := a[j+63:j]4552/// ELSE4553/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)4554/// FI4555/// ENDFOR4556/// \endcode4557///4558/// \headerfile <immintrin.h>4559///4560/// \code4561/// __m128i _mm_mask_i64gather_epi64(__m128i a, const long long *m, __m128i i,4562/// __m128i mask, const int s);4563/// \endcode4564///4565/// This intrinsic corresponds to the \c VPGATHERQQ instruction.4566///4567/// \param a4568/// A 128-bit vector of [2 x i64] used as the source when a mask bit is4569/// zero.4570/// \param m4571/// A pointer to the memory used for loading values.4572/// \param i4573/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.4574/// \param mask4575/// A 128-bit vector of [2 x i64] containing the mask. The most significant4576/// bit of each element in the mask vector represents the mask bits. If a4577/// mask bit is zero, the corresponding value from vector \a a is gathered;4578/// otherwise the value is loaded from memory.4579/// \param s4580/// A literal constant scale factor for the indexes in \a i. Must be4581/// 1, 2, 4, or 8.4582/// \returns A 128-bit vector of [2 x i64] containing the gathered values.4583#define _mm_mask_i64gather_epi64(a, m, i, mask, s) \4584 ((__m128i)__builtin_ia32_gatherq_q((__v2di)(__m128i)(a), \4585 (long long const *)(m), \4586 (__v2di)(__m128i)(i), \4587 (__v2di)(__m128i)(mask), (s)))4588 4589/// Conditionally gathers four 64-bit integer values, either from the4590/// 256-bit vector of [4 x i64] in \a a, or from memory \a m using scaled4591/// indexes from the 256-bit vector of [4 x i64] in \a i. The 256-bit vector4592/// of [4 x i64] in \a mask determines the source for each element.4593///4594/// \code{.operation}4595/// FOR element := 0 to 34596/// j := element*644597/// k := element*644598/// IF mask[j+63] == 04599/// result[j+63:j] := a[j+63:j]4600/// ELSE4601/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)4602/// FI4603/// ENDFOR4604/// \endcode4605///4606/// \headerfile <immintrin.h>4607///4608/// \code4609/// __m256i _mm256_mask_i64gather_epi64(__m256i a, const long long *m,4610/// __m256i i, __m256i mask, const int s);4611/// \endcode4612///4613/// This intrinsic corresponds to the \c VPGATHERQQ instruction.4614///4615/// \param a4616/// A 256-bit vector of [4 x i64] used as the source when a mask bit is4617/// zero.4618/// \param m4619/// A pointer to the memory used for loading values.4620/// \param i4621/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4622/// \param mask4623/// A 256-bit vector of [4 x i64] containing the mask. The most significant4624/// bit of each element in the mask vector represents the mask bits. If a4625/// mask bit is zero, the corresponding value from vector \a a is gathered;4626/// otherwise the value is loaded from memory.4627/// \param s4628/// A literal constant scale factor for the indexes in \a i. Must be4629/// 1, 2, 4, or 8.4630/// \returns A 256-bit vector of [4 x i64] containing the gathered values.4631#define _mm256_mask_i64gather_epi64(a, m, i, mask, s) \4632 ((__m256i)__builtin_ia32_gatherq_q256((__v4di)(__m256i)(a), \4633 (long long const *)(m), \4634 (__v4di)(__m256i)(i), \4635 (__v4di)(__m256i)(mask), (s)))4636 4637/// Gathers two 64-bit floating-point values from memory \a m using scaled4638/// indexes from the 128-bit vector of [4 x i32] in \a i.4639///4640/// \code{.operation}4641/// FOR element := 0 to 14642/// j := element*644643/// k := element*324644/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)4645/// ENDFOR4646/// \endcode4647///4648/// \headerfile <immintrin.h>4649///4650/// \code4651/// __m128d _mm_i32gather_pd(const double *m, __m128i i, const int s);4652/// \endcode4653///4654/// This intrinsic corresponds to the \c VGATHERDPD instruction.4655///4656/// \param m4657/// A pointer to the memory used for loading values.4658/// \param i4659/// A 128-bit vector of [4 x i32] containing signed indexes into \a m. Only4660/// the first two elements are used.4661/// \param s4662/// A literal constant scale factor for the indexes in \a i. Must be4663/// 1, 2, 4, or 8.4664/// \returns A 128-bit vector of [2 x double] containing the gathered values.4665#define _mm_i32gather_pd(m, i, s) \4666 ((__m128d)__builtin_ia32_gatherd_pd((__v2df)_mm_undefined_pd(), \4667 (double const *)(m), \4668 (__v4si)(__m128i)(i), \4669 (__v2df)_mm_cmpeq_pd(_mm_setzero_pd(), \4670 _mm_setzero_pd()), \4671 (s)))4672 4673/// Gathers four 64-bit floating-point values from memory \a m using scaled4674/// indexes from the 128-bit vector of [4 x i32] in \a i.4675///4676/// \code{.operation}4677/// FOR element := 0 to 34678/// j := element*644679/// k := element*324680/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)4681/// ENDFOR4682/// \endcode4683///4684/// \headerfile <immintrin.h>4685///4686/// \code4687/// __m256d _mm256_i32gather_pd(const double *m, __m128i i, const int s);4688/// \endcode4689///4690/// This intrinsic corresponds to the \c VGATHERDPD instruction.4691///4692/// \param m4693/// A pointer to the memory used for loading values.4694/// \param i4695/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4696/// \param s4697/// A literal constant scale factor for the indexes in \a i. Must be4698/// 1, 2, 4, or 8.4699/// \returns A 256-bit vector of [4 x double] containing the gathered values.4700#define _mm256_i32gather_pd(m, i, s) \4701 ((__m256d)__builtin_ia32_gatherd_pd256((__v4df)_mm256_undefined_pd(), \4702 (double const *)(m), \4703 (__v4si)(__m128i)(i), \4704 (__v4df)_mm256_cmp_pd(_mm256_setzero_pd(), \4705 _mm256_setzero_pd(), \4706 _CMP_EQ_OQ), \4707 (s)))4708 4709/// Gathers two 64-bit floating-point values from memory \a m using scaled4710/// indexes from the 128-bit vector of [2 x i64] in \a i.4711///4712/// \code{.operation}4713/// FOR element := 0 to 14714/// j := element*644715/// k := element*644716/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)4717/// ENDFOR4718/// \endcode4719///4720/// \headerfile <immintrin.h>4721///4722/// \code4723/// __m128d _mm_i64gather_pd(const double *m, __m128i i, const int s);4724/// \endcode4725///4726/// This intrinsic corresponds to the \c VGATHERQPD instruction.4727///4728/// \param m4729/// A pointer to the memory used for loading values.4730/// \param i4731/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.4732/// \param s4733/// A literal constant scale factor for the indexes in \a i. Must be4734/// 1, 2, 4, or 8.4735/// \returns A 128-bit vector of [2 x double] containing the gathered values.4736#define _mm_i64gather_pd(m, i, s) \4737 ((__m128d)__builtin_ia32_gatherq_pd((__v2df)_mm_undefined_pd(), \4738 (double const *)(m), \4739 (__v2di)(__m128i)(i), \4740 (__v2df)_mm_cmpeq_pd(_mm_setzero_pd(), \4741 _mm_setzero_pd()), \4742 (s)))4743 4744/// Gathers four 64-bit floating-point values from memory \a m using scaled4745/// indexes from the 256-bit vector of [4 x i64] in \a i.4746///4747/// \code{.operation}4748/// FOR element := 0 to 34749/// j := element*644750/// k := element*644751/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)4752/// ENDFOR4753/// \endcode4754///4755/// \headerfile <immintrin.h>4756///4757/// \code4758/// __m256d _mm256_i64gather_pd(const double *m, __m256i i, const int s);4759/// \endcode4760///4761/// This intrinsic corresponds to the \c VGATHERQPD instruction.4762///4763/// \param m4764/// A pointer to the memory used for loading values.4765/// \param i4766/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4767/// \param s4768/// A literal constant scale factor for the indexes in \a i. Must be4769/// 1, 2, 4, or 8.4770/// \returns A 256-bit vector of [4 x double] containing the gathered values.4771#define _mm256_i64gather_pd(m, i, s) \4772 ((__m256d)__builtin_ia32_gatherq_pd256((__v4df)_mm256_undefined_pd(), \4773 (double const *)(m), \4774 (__v4di)(__m256i)(i), \4775 (__v4df)_mm256_cmp_pd(_mm256_setzero_pd(), \4776 _mm256_setzero_pd(), \4777 _CMP_EQ_OQ), \4778 (s)))4779 4780/// Gathers four 32-bit floating-point values from memory \a m using scaled4781/// indexes from the 128-bit vector of [4 x i32] in \a i.4782///4783/// \code{.operation}4784/// FOR element := 0 to 34785/// j := element*324786/// k := element*324787/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4788/// ENDFOR4789/// \endcode4790///4791/// \headerfile <immintrin.h>4792///4793/// \code4794/// __m128 _mm_i32gather_ps(const float *m, __m128i i, const int s);4795/// \endcode4796///4797/// This intrinsic corresponds to the \c VGATHERDPS instruction.4798///4799/// \param m4800/// A pointer to the memory used for loading values.4801/// \param i4802/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4803/// \param s4804/// A literal constant scale factor for the indexes in \a i. Must be4805/// 1, 2, 4, or 8.4806/// \returns A 128-bit vector of [4 x float] containing the gathered values.4807#define _mm_i32gather_ps(m, i, s) \4808 ((__m128)__builtin_ia32_gatherd_ps((__v4sf)_mm_undefined_ps(), \4809 (float const *)(m), \4810 (__v4si)(__m128i)(i), \4811 (__v4sf)_mm_cmpeq_ps(_mm_setzero_ps(), \4812 _mm_setzero_ps()), \4813 (s)))4814 4815/// Gathers eight 32-bit floating-point values from memory \a m using scaled4816/// indexes from the 256-bit vector of [8 x i32] in \a i.4817///4818/// \code{.operation}4819/// FOR element := 0 to 74820/// j := element*324821/// k := element*324822/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4823/// ENDFOR4824/// \endcode4825///4826/// \headerfile <immintrin.h>4827///4828/// \code4829/// __m256 _mm256_i32gather_ps(const float *m, __m256i i, const int s);4830/// \endcode4831///4832/// This intrinsic corresponds to the \c VGATHERDPS instruction.4833///4834/// \param m4835/// A pointer to the memory used for loading values.4836/// \param i4837/// A 256-bit vector of [8 x i32] containing signed indexes into \a m.4838/// \param s4839/// A literal constant scale factor for the indexes in \a i. Must be4840/// 1, 2, 4, or 8.4841/// \returns A 256-bit vector of [8 x float] containing the gathered values.4842#define _mm256_i32gather_ps(m, i, s) \4843 ((__m256)__builtin_ia32_gatherd_ps256((__v8sf)_mm256_undefined_ps(), \4844 (float const *)(m), \4845 (__v8si)(__m256i)(i), \4846 (__v8sf)_mm256_cmp_ps(_mm256_setzero_ps(), \4847 _mm256_setzero_ps(), \4848 _CMP_EQ_OQ), \4849 (s)))4850 4851/// Gathers two 32-bit floating-point values from memory \a m using scaled4852/// indexes from the 128-bit vector of [2 x i64] in \a i. The upper two4853/// elements of the result are zeroed.4854///4855/// \code{.operation}4856/// FOR element := 0 to 14857/// j := element*324858/// k := element*644859/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4860/// ENDFOR4861/// result[127:64] := 04862/// \endcode4863///4864/// \headerfile <immintrin.h>4865///4866/// \code4867/// __m128 _mm_i64gather_ps(const float *m, __m128i i, const int s);4868/// \endcode4869///4870/// This intrinsic corresponds to the \c VGATHERQPS instruction.4871///4872/// \param m4873/// A pointer to the memory used for loading values.4874/// \param i4875/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.4876/// \param s4877/// A literal constant scale factor for the indexes in \a i. Must be4878/// 1, 2, 4, or 8.4879/// \returns A 128-bit vector of [4 x float] containing the gathered values.4880#define _mm_i64gather_ps(m, i, s) \4881 ((__m128)__builtin_ia32_gatherq_ps((__v4sf)_mm_undefined_ps(), \4882 (float const *)(m), \4883 (__v2di)(__m128i)(i), \4884 (__v4sf)_mm_cmpeq_ps(_mm_setzero_ps(), \4885 _mm_setzero_ps()), \4886 (s)))4887 4888/// Gathers four 32-bit floating-point values from memory \a m using scaled4889/// indexes from the 256-bit vector of [4 x i64] in \a i.4890///4891/// \code{.operation}4892/// FOR element := 0 to 34893/// j := element*324894/// k := element*644895/// result[j+31:j] := Load32(m + SignExtend(i[k+64:k])*s)4896/// ENDFOR4897/// \endcode4898///4899/// \headerfile <immintrin.h>4900///4901/// \code4902/// __m128 _mm256_i64gather_ps(const float *m, __m256i i, const int s);4903/// \endcode4904///4905/// This intrinsic corresponds to the \c VGATHERQPS instruction.4906///4907/// \param m4908/// A pointer to the memory used for loading values.4909/// \param i4910/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.4911/// \param s4912/// A literal constant scale factor for the indexes in \a i. Must be4913/// 1, 2, 4, or 8.4914/// \returns A 128-bit vector of [4 x float] containing the gathered values.4915#define _mm256_i64gather_ps(m, i, s) \4916 ((__m128)__builtin_ia32_gatherq_ps256((__v4sf)_mm_undefined_ps(), \4917 (float const *)(m), \4918 (__v4di)(__m256i)(i), \4919 (__v4sf)_mm_cmpeq_ps(_mm_setzero_ps(), \4920 _mm_setzero_ps()), \4921 (s)))4922 4923/// Gathers four 32-bit floating-point values from memory \a m using scaled4924/// indexes from the 128-bit vector of [4 x i32] in \a i.4925///4926/// \code{.operation}4927/// FOR element := 0 to 34928/// j := element*324929/// k := element*324930/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4931/// ENDFOR4932/// \endcode4933///4934/// \headerfile <immintrin.h>4935///4936/// \code4937/// __m128i _mm_i32gather_epi32(const int *m, __m128i i, const int s);4938/// \endcode4939///4940/// This intrinsic corresponds to the \c VPGATHERDD instruction.4941///4942/// \param m4943/// A pointer to the memory used for loading values.4944/// \param i4945/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.4946/// \param s4947/// A literal constant scale factor for the indexes in \a i. Must be4948/// 1, 2, 4, or 8.4949/// \returns A 128-bit vector of [4 x i32] containing the gathered values.4950#define _mm_i32gather_epi32(m, i, s) \4951 ((__m128i)__builtin_ia32_gatherd_d((__v4si)_mm_undefined_si128(), \4952 (int const *)(m), (__v4si)(__m128i)(i), \4953 (__v4si)_mm_set1_epi32(-1), (s)))4954 4955/// Gathers eight 32-bit floating-point values from memory \a m using scaled4956/// indexes from the 256-bit vector of [8 x i32] in \a i.4957///4958/// \code{.operation}4959/// FOR element := 0 to 74960/// j := element*324961/// k := element*324962/// result[j+31:j] := Load32(m + SignExtend(i[k+31:k])*s)4963/// ENDFOR4964/// \endcode4965///4966/// \headerfile <immintrin.h>4967///4968/// \code4969/// __m256i _mm256_i32gather_epi32(const int *m, __m256i i, const int s);4970/// \endcode4971///4972/// This intrinsic corresponds to the \c VPGATHERDD instruction.4973///4974/// \param m4975/// A pointer to the memory used for loading values.4976/// \param i4977/// A 256-bit vector of [8 x i32] containing signed indexes into \a m.4978/// \param s4979/// A literal constant scale factor for the indexes in \a i. Must be4980/// 1, 2, 4, or 8.4981/// \returns A 256-bit vector of [8 x i32] containing the gathered values.4982#define _mm256_i32gather_epi32(m, i, s) \4983 ((__m256i)__builtin_ia32_gatherd_d256((__v8si)_mm256_undefined_si256(), \4984 (int const *)(m), (__v8si)(__m256i)(i), \4985 (__v8si)_mm256_set1_epi32(-1), (s)))4986 4987/// Gathers two 32-bit integer values from memory \a m using scaled indexes4988/// from the 128-bit vector of [2 x i64] in \a i. The upper two elements4989/// of the result are zeroed.4990///4991/// \code{.operation}4992/// FOR element := 0 to 14993/// j := element*324994/// k := element*644995/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)4996/// ENDFOR4997/// result[127:64] := 04998/// \endcode4999///5000/// \headerfile <immintrin.h>5001///5002/// \code5003/// __m128i _mm_i64gather_epi32(const int *m, __m128i i, const int s);5004/// \endcode5005///5006/// This intrinsic corresponds to the \c VPGATHERQD instruction.5007///5008/// \param m5009/// A pointer to the memory used for loading values.5010/// \param i5011/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.5012/// \param s5013/// A literal constant scale factor for the indexes in \a i. Must be5014/// 1, 2, 4, or 8.5015/// \returns A 128-bit vector of [4 x i32] containing the gathered values.5016#define _mm_i64gather_epi32(m, i, s) \5017 ((__m128i)__builtin_ia32_gatherq_d((__v4si)_mm_undefined_si128(), \5018 (int const *)(m), (__v2di)(__m128i)(i), \5019 (__v4si)_mm_set1_epi32(-1), (s)))5020 5021/// Gathers four 32-bit integer values from memory \a m using scaled indexes5022/// from the 256-bit vector of [4 x i64] in \a i.5023///5024/// \code{.operation}5025/// FOR element := 0 to 35026/// j := element*325027/// k := element*645028/// result[j+31:j] := Load32(m + SignExtend(i[k+63:k])*s)5029/// ENDFOR5030/// \endcode5031///5032/// \headerfile <immintrin.h>5033///5034/// \code5035/// __m128i _mm256_i64gather_epi32(const int *m, __m256i i, const int s);5036/// \endcode5037///5038/// This intrinsic corresponds to the \c VPGATHERQD instruction.5039///5040/// \param m5041/// A pointer to the memory used for loading values.5042/// \param i5043/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.5044/// \param s5045/// A literal constant scale factor for the indexes in \a i. Must be5046/// 1, 2, 4, or 8.5047/// \returns A 128-bit vector of [4 x i32] containing the gathered values.5048#define _mm256_i64gather_epi32(m, i, s) \5049 ((__m128i)__builtin_ia32_gatherq_d256((__v4si)_mm_undefined_si128(), \5050 (int const *)(m), (__v4di)(__m256i)(i), \5051 (__v4si)_mm_set1_epi32(-1), (s)))5052 5053/// Gathers two 64-bit integer values from memory \a m using scaled indexes5054/// from the 128-bit vector of [4 x i32] in \a i.5055///5056/// \code{.operation}5057/// FOR element := 0 to 15058/// j := element*645059/// k := element*325060/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)5061/// ENDFOR5062/// \endcode5063///5064/// \headerfile <immintrin.h>5065///5066/// \code5067/// __m128i _mm_i32gather_epi64(const long long *m, __m128i i, const int s);5068/// \endcode5069///5070/// This intrinsic corresponds to the \c VPGATHERDQ instruction.5071///5072/// \param m5073/// A pointer to the memory used for loading values.5074/// \param i5075/// A 128-bit vector of [4 x i32] containing signed indexes into \a m. Only5076/// the first two elements are used.5077/// \param s5078/// A literal constant scale factor for the indexes in \a i. Must be5079/// 1, 2, 4, or 8.5080/// \returns A 128-bit vector of [2 x i64] containing the gathered values.5081#define _mm_i32gather_epi64(m, i, s) \5082 ((__m128i)__builtin_ia32_gatherd_q((__v2di)_mm_undefined_si128(), \5083 (long long const *)(m), \5084 (__v4si)(__m128i)(i), \5085 (__v2di)_mm_set1_epi64x(-1), (s)))5086 5087/// Gathers four 64-bit integer values from memory \a m using scaled indexes5088/// from the 128-bit vector of [4 x i32] in \a i.5089///5090/// \code{.operation}5091/// FOR element := 0 to 35092/// j := element*645093/// k := element*325094/// result[j+63:j] := Load64(m + SignExtend(i[k+31:k])*s)5095/// ENDFOR5096/// \endcode5097///5098/// \headerfile <immintrin.h>5099///5100/// \code5101/// __m256i _mm256_i32gather_epi64(const long long *m, __m128i i, const int s);5102/// \endcode5103///5104/// This intrinsic corresponds to the \c VPGATHERDQ instruction.5105///5106/// \param m5107/// A pointer to the memory used for loading values.5108/// \param i5109/// A 128-bit vector of [4 x i32] containing signed indexes into \a m.5110/// \param s5111/// A literal constant scale factor for the indexes in \a i. Must be5112/// 1, 2, 4, or 8.5113/// \returns A 256-bit vector of [4 x i64] containing the gathered values.5114#define _mm256_i32gather_epi64(m, i, s) \5115 ((__m256i)__builtin_ia32_gatherd_q256((__v4di)_mm256_undefined_si256(), \5116 (long long const *)(m), \5117 (__v4si)(__m128i)(i), \5118 (__v4di)_mm256_set1_epi64x(-1), (s)))5119 5120/// Gathers two 64-bit integer values from memory \a m using scaled indexes5121/// from the 128-bit vector of [2 x i64] in \a i.5122///5123/// \code{.operation}5124/// FOR element := 0 to 15125/// j := element*645126/// k := element*645127/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)5128/// ENDFOR5129/// \endcode5130///5131/// \headerfile <immintrin.h>5132///5133/// \code5134/// __m128i _mm_i64gather_epi64(const long long *m, __m128i i, const int s);5135/// \endcode5136///5137/// This intrinsic corresponds to the \c VPGATHERQQ instruction.5138///5139/// \param m5140/// A pointer to the memory used for loading values.5141/// \param i5142/// A 128-bit vector of [2 x i64] containing signed indexes into \a m.5143/// \param s5144/// A literal constant scale factor for the indexes in \a i. Must be5145/// 1, 2, 4, or 8.5146/// \returns A 128-bit vector of [2 x i64] containing the gathered values.5147#define _mm_i64gather_epi64(m, i, s) \5148 ((__m128i)__builtin_ia32_gatherq_q((__v2di)_mm_undefined_si128(), \5149 (long long const *)(m), \5150 (__v2di)(__m128i)(i), \5151 (__v2di)_mm_set1_epi64x(-1), (s)))5152 5153/// Gathers four 64-bit integer values from memory \a m using scaled indexes5154/// from the 256-bit vector of [4 x i64] in \a i.5155///5156/// \code{.operation}5157/// FOR element := 0 to 35158/// j := element*645159/// k := element*645160/// result[j+63:j] := Load64(m + SignExtend(i[k+63:k])*s)5161/// ENDFOR5162/// \endcode5163///5164/// \headerfile <immintrin.h>5165///5166/// \code5167/// __m256i _mm256_i64gather_epi64(const long long *m, __m256i i, const int s);5168/// \endcode5169///5170/// This intrinsic corresponds to the \c VPGATHERQQ instruction.5171///5172/// \param m5173/// A pointer to the memory used for loading values.5174/// \param i5175/// A 256-bit vector of [4 x i64] containing signed indexes into \a m.5176/// \param s5177/// A literal constant scale factor for the indexes in \a i. Must be5178/// 1, 2, 4, or 8.5179/// \returns A 256-bit vector of [4 x i64] containing the gathered values.5180#define _mm256_i64gather_epi64(m, i, s) \5181 ((__m256i)__builtin_ia32_gatherq_q256((__v4di)_mm256_undefined_si256(), \5182 (long long const *)(m), \5183 (__v4di)(__m256i)(i), \5184 (__v4di)_mm256_set1_epi64x(-1), (s)))5185 5186#undef __DEFAULT_FN_ATTRS2565187#undef __DEFAULT_FN_ATTRS1285188#undef __DEFAULT_FN_ATTRS256_CONSTEXPR5189#undef __DEFAULT_FN_ATTRS128_CONSTEXPR5190 5191#endif /* __AVX2INTRIN_H */5192