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1/*===------------- avx512vlvnniintrin.h - VNNI intrinsics ------------------===2 *3 *4 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.5 * See https://llvm.org/LICENSE.txt for license information.6 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 *8 *===-----------------------------------------------------------------------===9 */10#ifndef __IMMINTRIN_H11#error "Never use <avx512vlvnniintrin.h> directly; include <immintrin.h> instead."12#endif13 14#ifndef __AVX512VLVNNIINTRIN_H15#define __AVX512VLVNNIINTRIN_H16 17/* Define the default attributes for the functions in this file. */18#define __DEFAULT_FN_ATTRS128 \19 __attribute__((__always_inline__, __nodebug__, \20 __target__("avx512vl,avx512vnni"), \21 __min_vector_width__(128)))22#define __DEFAULT_FN_ATTRS256 \23 __attribute__((__always_inline__, __nodebug__, \24 __target__("avx512vl,avx512vnni"), \25 __min_vector_width__(256)))26 27/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with28/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed29/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer30/// in \a S, and store the packed 32-bit results in DST.31///32/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.33///34/// \code{.operation}35/// FOR j := 0 to 736/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))37/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))38/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))39/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))40/// DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp441/// ENDFOR42/// DST[MAX:256] := 043/// \endcode44#define _mm256_dpbusd_epi32(S, A, B) \45 ((__m256i)__builtin_ia32_vpdpbusd256((__v8si)(S), (__v32qu)(A), (__v32qi)(B)))46 47/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with48/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed49/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer50/// in \a S using signed saturation, and store the packed 32-bit results in DST.51///52/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.53///54/// \code{.operation}55/// FOR j := 0 to 756/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))57/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))58/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))59/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))60/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)61/// ENDFOR62/// DST[MAX:256] := 063/// \endcode64#define _mm256_dpbusds_epi32(S, A, B) \65 ((__m256i)__builtin_ia32_vpdpbusds256((__v8si)(S), (__v32qu)(A), \66 (__v32qi)(B)))67 68/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with69/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit70/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,71/// and store the packed 32-bit results in DST.72///73/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.74///75/// \code{.operation}76/// FOR j := 0 to 777/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])78/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])79/// DST.dword[j] := S.dword[j] + tmp1 + tmp280/// ENDFOR81/// DST[MAX:256] := 082/// \endcode83#define _mm256_dpwssd_epi32(S, A, B) \84 ((__m256i)__builtin_ia32_vpdpwssd256((__v8si)(S), (__v8si)(A), (__v8si)(B)))85 86/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with87/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit88/// results. Sum these 2 results with the corresponding 32-bit integer in \a S89/// using signed saturation, and store the packed 32-bit results in DST.90///91/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.92///93/// \code{.operation}94/// FOR j := 0 to 795/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])96/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])97/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)98/// ENDFOR99/// DST[MAX:256] := 0100/// \endcode101#define _mm256_dpwssds_epi32(S, A, B) \102 ((__m256i)__builtin_ia32_vpdpwssds256((__v8si)(S), (__v8si)(A), (__v8si)(B)))103 104/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with105/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed106/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer107/// in \a S, and store the packed 32-bit results in DST.108///109/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.110///111/// \code{.operation}112/// FOR j := 0 to 3113/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))114/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))115/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))116/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))117/// DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4118/// ENDFOR119/// DST[MAX:128] := 0120/// \endcode121#define _mm_dpbusd_epi32(S, A, B) \122 ((__m128i)__builtin_ia32_vpdpbusd128((__v4si)(S), (__v16qu)(A), (__v16qi)(B)))123 124/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with125/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed126/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer127/// in \a S using signed saturation, and store the packed 32-bit results in DST.128///129/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.130///131/// \code{.operation}132/// FOR j := 0 to 3133/// tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))134/// tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))135/// tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))136/// tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))137/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)138/// ENDFOR139/// DST[MAX:128] := 0140/// \endcode141#define _mm_dpbusds_epi32(S, A, B) \142 ((__m128i)__builtin_ia32_vpdpbusds128((__v4si)(S), (__v16qu)(A), \143 (__v16qi)(B)))144 145/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with146/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit147/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,148/// and store the packed 32-bit results in DST.149///150/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.151///152/// \code{.operation}153/// FOR j := 0 to 3154/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])155/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])156/// DST.dword[j] := S.dword[j] + tmp1 + tmp2157/// ENDFOR158/// DST[MAX:128] := 0159/// \endcode160#define _mm_dpwssd_epi32(S, A, B) \161 ((__m128i)__builtin_ia32_vpdpwssd128((__v4si)(S), (__v4si)(A), (__v4si)(B)))162 163/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with164/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit165/// results. Sum these 2 results with the corresponding 32-bit integer in \a S166/// using signed saturation, and store the packed 32-bit results in DST.167///168/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.169///170/// \code{.operation}171/// FOR j := 0 to 3172/// tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])173/// tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])174/// DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)175/// ENDFOR176/// DST[MAX:128] := 0177/// \endcode178#define _mm_dpwssds_epi32(S, A, B) \179 ((__m128i)__builtin_ia32_vpdpwssds128((__v4si)(S), (__v4si)(A), (__v4si)(B)))180 181static __inline__ __m256i __DEFAULT_FN_ATTRS256182_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)183{184 return (__m256i)__builtin_ia32_selectd_256(__U,185 (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),186 (__v8si)__S);187}188 189static __inline__ __m256i __DEFAULT_FN_ATTRS256190_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)191{192 return (__m256i)__builtin_ia32_selectd_256(__U,193 (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),194 (__v8si)_mm256_setzero_si256());195}196 197static __inline__ __m256i __DEFAULT_FN_ATTRS256198_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)199{200 return (__m256i)__builtin_ia32_selectd_256(__U,201 (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),202 (__v8si)__S);203}204 205static __inline__ __m256i __DEFAULT_FN_ATTRS256206_mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)207{208 return (__m256i)__builtin_ia32_selectd_256(__U,209 (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),210 (__v8si)_mm256_setzero_si256());211}212 213static __inline__ __m256i __DEFAULT_FN_ATTRS256214_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)215{216 return (__m256i)__builtin_ia32_selectd_256(__U,217 (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),218 (__v8si)__S);219}220 221static __inline__ __m256i __DEFAULT_FN_ATTRS256222_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)223{224 return (__m256i)__builtin_ia32_selectd_256(__U,225 (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),226 (__v8si)_mm256_setzero_si256());227}228 229static __inline__ __m256i __DEFAULT_FN_ATTRS256230_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)231{232 return (__m256i)__builtin_ia32_selectd_256(__U,233 (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),234 (__v8si)__S);235}236 237static __inline__ __m256i __DEFAULT_FN_ATTRS256238_mm256_maskz_dpwssds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)239{240 return (__m256i)__builtin_ia32_selectd_256(__U,241 (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),242 (__v8si)_mm256_setzero_si256());243}244 245static __inline__ __m128i __DEFAULT_FN_ATTRS128246_mm_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)247{248 return (__m128i)__builtin_ia32_selectd_128(__U,249 (__v4si)_mm_dpbusd_epi32(__S, __A, __B),250 (__v4si)__S);251}252 253static __inline__ __m128i __DEFAULT_FN_ATTRS128254_mm_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)255{256 return (__m128i)__builtin_ia32_selectd_128(__U,257 (__v4si)_mm_dpbusd_epi32(__S, __A, __B),258 (__v4si)_mm_setzero_si128());259}260 261static __inline__ __m128i __DEFAULT_FN_ATTRS128262_mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)263{264 return (__m128i)__builtin_ia32_selectd_128(__U,265 (__v4si)_mm_dpbusds_epi32(__S, __A, __B),266 (__v4si)__S);267}268 269static __inline__ __m128i __DEFAULT_FN_ATTRS128270_mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)271{272 return (__m128i)__builtin_ia32_selectd_128(__U,273 (__v4si)_mm_dpbusds_epi32(__S, __A, __B),274 (__v4si)_mm_setzero_si128());275}276 277static __inline__ __m128i __DEFAULT_FN_ATTRS128278_mm_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)279{280 return (__m128i)__builtin_ia32_selectd_128(__U,281 (__v4si)_mm_dpwssd_epi32(__S, __A, __B),282 (__v4si)__S);283}284 285static __inline__ __m128i __DEFAULT_FN_ATTRS128286_mm_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)287{288 return (__m128i)__builtin_ia32_selectd_128(__U,289 (__v4si)_mm_dpwssd_epi32(__S, __A, __B),290 (__v4si)_mm_setzero_si128());291}292 293static __inline__ __m128i __DEFAULT_FN_ATTRS128294_mm_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)295{296 return (__m128i)__builtin_ia32_selectd_128(__U,297 (__v4si)_mm_dpwssds_epi32(__S, __A, __B),298 (__v4si)__S);299}300 301static __inline__ __m128i __DEFAULT_FN_ATTRS128302_mm_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)303{304 return (__m128i)__builtin_ia32_selectd_128(__U,305 (__v4si)_mm_dpwssds_epi32(__S, __A, __B),306 (__v4si)_mm_setzero_si128());307}308 309#undef __DEFAULT_FN_ATTRS128310#undef __DEFAULT_FN_ATTRS256311 312#endif313