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1/*===---- avxintrin.h - AVX intrinsics -------------------------------------===2 *3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4 * See https://llvm.org/LICENSE.txt for license information.5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6 *7 *===-----------------------------------------------------------------------===8 */9 10#ifndef __IMMINTRIN_H11#error "Never use <avxintrin.h> directly; include <immintrin.h> instead."12#endif13 14#ifndef __AVXINTRIN_H15#define __AVXINTRIN_H16 17typedef double __v4df __attribute__ ((__vector_size__ (32)));18typedef float __v8sf __attribute__ ((__vector_size__ (32)));19typedef long long __v4di __attribute__ ((__vector_size__ (32)));20typedef int __v8si __attribute__ ((__vector_size__ (32)));21typedef short __v16hi __attribute__ ((__vector_size__ (32)));22typedef char __v32qi __attribute__ ((__vector_size__ (32)));23 24/* Unsigned types */25typedef unsigned long long __v4du __attribute__ ((__vector_size__ (32)));26typedef unsigned int __v8su __attribute__ ((__vector_size__ (32)));27typedef unsigned short __v16hu __attribute__ ((__vector_size__ (32)));28typedef unsigned char __v32qu __attribute__ ((__vector_size__ (32)));29 30/* We need an explicitly signed variant for char. Note that this shouldn't31 * appear in the interface though. */32typedef signed char __v32qs __attribute__((__vector_size__(32)));33 34typedef float __m256 __attribute__ ((__vector_size__ (32), __aligned__(32)));35typedef double __m256d __attribute__((__vector_size__(32), __aligned__(32)));36typedef long long __m256i __attribute__((__vector_size__(32), __aligned__(32)));37 38typedef float __m256_u __attribute__ ((__vector_size__ (32), __aligned__(1)));39typedef double __m256d_u __attribute__((__vector_size__(32), __aligned__(1)));40typedef long long __m256i_u __attribute__((__vector_size__(32), __aligned__(1)));41 42#ifdef __SSE2__43/* Both _Float16 and __bf16 require SSE2 being enabled. */44typedef _Float16 __v16hf __attribute__((__vector_size__(32), __aligned__(32)));45typedef _Float16 __m256h __attribute__((__vector_size__(32), __aligned__(32)));46typedef _Float16 __m256h_u __attribute__((__vector_size__(32), __aligned__(1)));47 48typedef __bf16 __v16bf __attribute__((__vector_size__(32), __aligned__(32)));49typedef __bf16 __m256bh __attribute__((__vector_size__(32), __aligned__(32)));50#endif51 52/* Define the default attributes for the functions in this file. */53#define __DEFAULT_FN_ATTRS \54 __attribute__((__always_inline__, __nodebug__, __target__("avx"), \55 __min_vector_width__(256)))56#define __DEFAULT_FN_ATTRS128 \57 __attribute__((__always_inline__, __nodebug__, __target__("avx"), \58 __min_vector_width__(128)))59 60#if defined(__cplusplus) && (__cplusplus >= 201103L)61#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr62#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr63#else64#define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS65#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS12866#endif67 68/* Arithmetic */69/// Adds two 256-bit vectors of [4 x double].70///71/// \headerfile <x86intrin.h>72///73/// This intrinsic corresponds to the <c> VADDPD </c> instruction.74///75/// \param __a76/// A 256-bit vector of [4 x double] containing one of the source operands.77/// \param __b78/// A 256-bit vector of [4 x double] containing one of the source operands.79/// \returns A 256-bit vector of [4 x double] containing the sums of both80/// operands.81static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR82_mm256_add_pd(__m256d __a, __m256d __b) {83 return (__m256d)((__v4df)__a+(__v4df)__b);84}85 86/// Adds two 256-bit vectors of [8 x float].87///88/// \headerfile <x86intrin.h>89///90/// This intrinsic corresponds to the <c> VADDPS </c> instruction.91///92/// \param __a93/// A 256-bit vector of [8 x float] containing one of the source operands.94/// \param __b95/// A 256-bit vector of [8 x float] containing one of the source operands.96/// \returns A 256-bit vector of [8 x float] containing the sums of both97/// operands.98static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_add_ps(__m256 __a,99 __m256 __b) {100 return (__m256)((__v8sf)__a+(__v8sf)__b);101}102 103/// Subtracts two 256-bit vectors of [4 x double].104///105/// \headerfile <x86intrin.h>106///107/// This intrinsic corresponds to the <c> VSUBPD </c> instruction.108///109/// \param __a110/// A 256-bit vector of [4 x double] containing the minuend.111/// \param __b112/// A 256-bit vector of [4 x double] containing the subtrahend.113/// \returns A 256-bit vector of [4 x double] containing the differences between114/// both operands.115static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR116_mm256_sub_pd(__m256d __a, __m256d __b) {117 return (__m256d)((__v4df)__a-(__v4df)__b);118}119 120/// Subtracts two 256-bit vectors of [8 x float].121///122/// \headerfile <x86intrin.h>123///124/// This intrinsic corresponds to the <c> VSUBPS </c> instruction.125///126/// \param __a127/// A 256-bit vector of [8 x float] containing the minuend.128/// \param __b129/// A 256-bit vector of [8 x float] containing the subtrahend.130/// \returns A 256-bit vector of [8 x float] containing the differences between131/// both operands.132static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_sub_ps(__m256 __a,133 __m256 __b) {134 return (__m256)((__v8sf)__a-(__v8sf)__b);135}136 137/// Adds the even-indexed values and subtracts the odd-indexed values of138/// two 256-bit vectors of [4 x double].139///140/// \headerfile <x86intrin.h>141///142/// This intrinsic corresponds to the <c> VADDSUBPD </c> instruction.143///144/// \param __a145/// A 256-bit vector of [4 x double] containing the left source operand.146/// \param __b147/// A 256-bit vector of [4 x double] containing the right source operand.148/// \returns A 256-bit vector of [4 x double] containing the alternating sums149/// and differences between both operands.150static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR151_mm256_addsub_pd(__m256d __a, __m256d __b) {152 return (__m256d)__builtin_ia32_addsubpd256((__v4df)__a, (__v4df)__b);153}154 155/// Adds the even-indexed values and subtracts the odd-indexed values of156/// two 256-bit vectors of [8 x float].157///158/// \headerfile <x86intrin.h>159///160/// This intrinsic corresponds to the <c> VADDSUBPS </c> instruction.161///162/// \param __a163/// A 256-bit vector of [8 x float] containing the left source operand.164/// \param __b165/// A 256-bit vector of [8 x float] containing the right source operand.166/// \returns A 256-bit vector of [8 x float] containing the alternating sums and167/// differences between both operands.168static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR169_mm256_addsub_ps(__m256 __a, __m256 __b) {170 return (__m256)__builtin_ia32_addsubps256((__v8sf)__a, (__v8sf)__b);171}172 173/// Divides two 256-bit vectors of [4 x double].174///175/// \headerfile <x86intrin.h>176///177/// This intrinsic corresponds to the <c> VDIVPD </c> instruction.178///179/// \param __a180/// A 256-bit vector of [4 x double] containing the dividend.181/// \param __b182/// A 256-bit vector of [4 x double] containing the divisor.183/// \returns A 256-bit vector of [4 x double] containing the quotients of both184/// operands.185static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR186_mm256_div_pd(__m256d __a, __m256d __b) {187 return (__m256d)((__v4df)__a/(__v4df)__b);188}189 190/// Divides two 256-bit vectors of [8 x float].191///192/// \headerfile <x86intrin.h>193///194/// This intrinsic corresponds to the <c> VDIVPS </c> instruction.195///196/// \param __a197/// A 256-bit vector of [8 x float] containing the dividend.198/// \param __b199/// A 256-bit vector of [8 x float] containing the divisor.200/// \returns A 256-bit vector of [8 x float] containing the quotients of both201/// operands.202static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_div_ps(__m256 __a,203 __m256 __b) {204 return (__m256)((__v8sf)__a/(__v8sf)__b);205}206 207/// Compares two 256-bit vectors of [4 x double] and returns the greater208/// of each pair of values.209///210/// If either value in a comparison is NaN, returns the value from \a __b.211///212/// \headerfile <x86intrin.h>213///214/// This intrinsic corresponds to the <c> VMAXPD </c> instruction.215///216/// \param __a217/// A 256-bit vector of [4 x double] containing one of the operands.218/// \param __b219/// A 256-bit vector of [4 x double] containing one of the operands.220/// \returns A 256-bit vector of [4 x double] containing the maximum values221/// between both operands.222static __inline __m256d __DEFAULT_FN_ATTRS223_mm256_max_pd(__m256d __a, __m256d __b)224{225 return (__m256d)__builtin_ia32_maxpd256((__v4df)__a, (__v4df)__b);226}227 228/// Compares two 256-bit vectors of [8 x float] and returns the greater229/// of each pair of values.230///231/// If either value in a comparison is NaN, returns the value from \a __b.232///233/// \headerfile <x86intrin.h>234///235/// This intrinsic corresponds to the <c> VMAXPS </c> instruction.236///237/// \param __a238/// A 256-bit vector of [8 x float] containing one of the operands.239/// \param __b240/// A 256-bit vector of [8 x float] containing one of the operands.241/// \returns A 256-bit vector of [8 x float] containing the maximum values242/// between both operands.243static __inline __m256 __DEFAULT_FN_ATTRS244_mm256_max_ps(__m256 __a, __m256 __b)245{246 return (__m256)__builtin_ia32_maxps256((__v8sf)__a, (__v8sf)__b);247}248 249/// Compares two 256-bit vectors of [4 x double] and returns the lesser250/// of each pair of values.251///252/// If either value in a comparison is NaN, returns the value from \a __b.253///254/// \headerfile <x86intrin.h>255///256/// This intrinsic corresponds to the <c> VMINPD </c> instruction.257///258/// \param __a259/// A 256-bit vector of [4 x double] containing one of the operands.260/// \param __b261/// A 256-bit vector of [4 x double] containing one of the operands.262/// \returns A 256-bit vector of [4 x double] containing the minimum values263/// between both operands.264static __inline __m256d __DEFAULT_FN_ATTRS265_mm256_min_pd(__m256d __a, __m256d __b)266{267 return (__m256d)__builtin_ia32_minpd256((__v4df)__a, (__v4df)__b);268}269 270/// Compares two 256-bit vectors of [8 x float] and returns the lesser271/// of each pair of values.272///273/// If either value in a comparison is NaN, returns the value from \a __b.274///275/// \headerfile <x86intrin.h>276///277/// This intrinsic corresponds to the <c> VMINPS </c> instruction.278///279/// \param __a280/// A 256-bit vector of [8 x float] containing one of the operands.281/// \param __b282/// A 256-bit vector of [8 x float] containing one of the operands.283/// \returns A 256-bit vector of [8 x float] containing the minimum values284/// between both operands.285static __inline __m256 __DEFAULT_FN_ATTRS286_mm256_min_ps(__m256 __a, __m256 __b)287{288 return (__m256)__builtin_ia32_minps256((__v8sf)__a, (__v8sf)__b);289}290 291/// Multiplies two 256-bit vectors of [4 x double].292///293/// \headerfile <x86intrin.h>294///295/// This intrinsic corresponds to the <c> VMULPD </c> instruction.296///297/// \param __a298/// A 256-bit vector of [4 x double] containing one of the operands.299/// \param __b300/// A 256-bit vector of [4 x double] containing one of the operands.301/// \returns A 256-bit vector of [4 x double] containing the products of both302/// operands.303static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR304_mm256_mul_pd(__m256d __a, __m256d __b) {305 return (__m256d)((__v4df)__a * (__v4df)__b);306}307 308/// Multiplies two 256-bit vectors of [8 x float].309///310/// \headerfile <x86intrin.h>311///312/// This intrinsic corresponds to the <c> VMULPS </c> instruction.313///314/// \param __a315/// A 256-bit vector of [8 x float] containing one of the operands.316/// \param __b317/// A 256-bit vector of [8 x float] containing one of the operands.318/// \returns A 256-bit vector of [8 x float] containing the products of both319/// operands.320static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_mul_ps(__m256 __a,321 __m256 __b) {322 return (__m256)((__v8sf)__a * (__v8sf)__b);323}324 325/// Calculates the square roots of the values in a 256-bit vector of326/// [4 x double].327///328/// \headerfile <x86intrin.h>329///330/// This intrinsic corresponds to the <c> VSQRTPD </c> instruction.331///332/// \param __a333/// A 256-bit vector of [4 x double].334/// \returns A 256-bit vector of [4 x double] containing the square roots of the335/// values in the operand.336static __inline __m256d __DEFAULT_FN_ATTRS _mm256_sqrt_pd(__m256d __a) {337 return __builtin_elementwise_sqrt(__a);338}339 340/// Calculates the square roots of the values in a 256-bit vector of341/// [8 x float].342///343/// \headerfile <x86intrin.h>344///345/// This intrinsic corresponds to the <c> VSQRTPS </c> instruction.346///347/// \param __a348/// A 256-bit vector of [8 x float].349/// \returns A 256-bit vector of [8 x float] containing the square roots of the350/// values in the operand.351static __inline __m256 __DEFAULT_FN_ATTRS _mm256_sqrt_ps(__m256 __a) {352 return __builtin_elementwise_sqrt(__a);353}354 355/// Calculates the reciprocal square roots of the values in a 256-bit356/// vector of [8 x float].357///358/// \headerfile <x86intrin.h>359///360/// This intrinsic corresponds to the <c> VRSQRTPS </c> instruction.361///362/// \param __a363/// A 256-bit vector of [8 x float].364/// \returns A 256-bit vector of [8 x float] containing the reciprocal square365/// roots of the values in the operand.366static __inline __m256 __DEFAULT_FN_ATTRS367_mm256_rsqrt_ps(__m256 __a)368{369 return (__m256)__builtin_ia32_rsqrtps256((__v8sf)__a);370}371 372/// Calculates the reciprocals of the values in a 256-bit vector of373/// [8 x float].374///375/// \headerfile <x86intrin.h>376///377/// This intrinsic corresponds to the <c> VRCPPS </c> instruction.378///379/// \param __a380/// A 256-bit vector of [8 x float].381/// \returns A 256-bit vector of [8 x float] containing the reciprocals of the382/// values in the operand.383static __inline __m256 __DEFAULT_FN_ATTRS384_mm256_rcp_ps(__m256 __a)385{386 return (__m256)__builtin_ia32_rcpps256((__v8sf)__a);387}388 389/// Rounds the values in a 256-bit vector of [4 x double] as specified390/// by the byte operand. The source values are rounded to integer values and391/// returned as 64-bit double-precision floating-point values.392///393/// \headerfile <x86intrin.h>394///395/// \code396/// __m256d _mm256_round_pd(__m256d V, const int M);397/// \endcode398///399/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction.400///401/// \param V402/// A 256-bit vector of [4 x double].403/// \param M404/// An integer value that specifies the rounding operation. \n405/// Bits [7:4] are reserved. \n406/// Bit [3] is a precision exception value: \n407/// 0: A normal PE exception is used. \n408/// 1: The PE field is not updated. \n409/// Bit [2] is the rounding control source: \n410/// 0: Use bits [1:0] of \a M. \n411/// 1: Use the current MXCSR setting. \n412/// Bits [1:0] contain the rounding control definition: \n413/// 00: Nearest. \n414/// 01: Downward (toward negative infinity). \n415/// 10: Upward (toward positive infinity). \n416/// 11: Truncated.417/// \returns A 256-bit vector of [4 x double] containing the rounded values.418#define _mm256_round_pd(V, M) \419 ((__m256d)__builtin_ia32_roundpd256((__v4df)(__m256d)(V), (M)))420 421/// Rounds the values stored in a 256-bit vector of [8 x float] as422/// specified by the byte operand. The source values are rounded to integer423/// values and returned as floating-point values.424///425/// \headerfile <x86intrin.h>426///427/// \code428/// __m256 _mm256_round_ps(__m256 V, const int M);429/// \endcode430///431/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction.432///433/// \param V434/// A 256-bit vector of [8 x float].435/// \param M436/// An integer value that specifies the rounding operation. \n437/// Bits [7:4] are reserved. \n438/// Bit [3] is a precision exception value: \n439/// 0: A normal PE exception is used. \n440/// 1: The PE field is not updated. \n441/// Bit [2] is the rounding control source: \n442/// 0: Use bits [1:0] of \a M. \n443/// 1: Use the current MXCSR setting. \n444/// Bits [1:0] contain the rounding control definition: \n445/// 00: Nearest. \n446/// 01: Downward (toward negative infinity). \n447/// 10: Upward (toward positive infinity). \n448/// 11: Truncated.449/// \returns A 256-bit vector of [8 x float] containing the rounded values.450#define _mm256_round_ps(V, M) \451 ((__m256)__builtin_ia32_roundps256((__v8sf)(__m256)(V), (M)))452 453/// Rounds up the values stored in a 256-bit vector of [4 x double]. The454/// source values are rounded up to integer values and returned as 64-bit455/// double-precision floating-point values.456///457/// \headerfile <x86intrin.h>458///459/// \code460/// __m256d _mm256_ceil_pd(__m256d V);461/// \endcode462///463/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction.464///465/// \param V466/// A 256-bit vector of [4 x double].467/// \returns A 256-bit vector of [4 x double] containing the rounded up values.468#define _mm256_ceil_pd(V) _mm256_round_pd((V), _MM_FROUND_CEIL)469 470/// Rounds down the values stored in a 256-bit vector of [4 x double].471/// The source values are rounded down to integer values and returned as472/// 64-bit double-precision floating-point values.473///474/// \headerfile <x86intrin.h>475///476/// \code477/// __m256d _mm256_floor_pd(__m256d V);478/// \endcode479///480/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction.481///482/// \param V483/// A 256-bit vector of [4 x double].484/// \returns A 256-bit vector of [4 x double] containing the rounded down485/// values.486#define _mm256_floor_pd(V) _mm256_round_pd((V), _MM_FROUND_FLOOR)487 488/// Rounds up the values stored in a 256-bit vector of [8 x float]. The489/// source values are rounded up to integer values and returned as490/// floating-point values.491///492/// \headerfile <x86intrin.h>493///494/// \code495/// __m256 _mm256_ceil_ps(__m256 V);496/// \endcode497///498/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction.499///500/// \param V501/// A 256-bit vector of [8 x float].502/// \returns A 256-bit vector of [8 x float] containing the rounded up values.503#define _mm256_ceil_ps(V) _mm256_round_ps((V), _MM_FROUND_CEIL)504 505/// Rounds down the values stored in a 256-bit vector of [8 x float]. The506/// source values are rounded down to integer values and returned as507/// floating-point values.508///509/// \headerfile <x86intrin.h>510///511/// \code512/// __m256 _mm256_floor_ps(__m256 V);513/// \endcode514///515/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction.516///517/// \param V518/// A 256-bit vector of [8 x float].519/// \returns A 256-bit vector of [8 x float] containing the rounded down values.520#define _mm256_floor_ps(V) _mm256_round_ps((V), _MM_FROUND_FLOOR)521 522/* Logical */523/// Performs a bitwise AND of two 256-bit vectors of [4 x double].524///525/// \headerfile <x86intrin.h>526///527/// This intrinsic corresponds to the <c> VANDPD </c> instruction.528///529/// \param __a530/// A 256-bit vector of [4 x double] containing one of the source operands.531/// \param __b532/// A 256-bit vector of [4 x double] containing one of the source operands.533/// \returns A 256-bit vector of [4 x double] containing the bitwise AND of the534/// values between both operands.535static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR536_mm256_and_pd(__m256d __a, __m256d __b)537{538 return (__m256d)((__v4du)__a & (__v4du)__b);539}540 541/// Performs a bitwise AND of two 256-bit vectors of [8 x float].542///543/// \headerfile <x86intrin.h>544///545/// This intrinsic corresponds to the <c> VANDPS </c> instruction.546///547/// \param __a548/// A 256-bit vector of [8 x float] containing one of the source operands.549/// \param __b550/// A 256-bit vector of [8 x float] containing one of the source operands.551/// \returns A 256-bit vector of [8 x float] containing the bitwise AND of the552/// values between both operands.553static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR554_mm256_and_ps(__m256 __a, __m256 __b)555{556 return (__m256)((__v8su)__a & (__v8su)__b);557}558 559/// Performs a bitwise AND of two 256-bit vectors of [4 x double], using560/// the one's complement of the values contained in the first source operand.561///562/// \headerfile <x86intrin.h>563///564/// This intrinsic corresponds to the <c> VANDNPD </c> instruction.565///566/// \param __a567/// A 256-bit vector of [4 x double] containing the left source operand. The568/// one's complement of this value is used in the bitwise AND.569/// \param __b570/// A 256-bit vector of [4 x double] containing the right source operand.571/// \returns A 256-bit vector of [4 x double] containing the bitwise AND of the572/// values of the second operand and the one's complement of the first573/// operand.574static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR575_mm256_andnot_pd(__m256d __a, __m256d __b)576{577 return (__m256d)(~(__v4du)__a & (__v4du)__b);578}579 580/// Performs a bitwise AND of two 256-bit vectors of [8 x float], using581/// the one's complement of the values contained in the first source operand.582///583/// \headerfile <x86intrin.h>584///585/// This intrinsic corresponds to the <c> VANDNPS </c> instruction.586///587/// \param __a588/// A 256-bit vector of [8 x float] containing the left source operand. The589/// one's complement of this value is used in the bitwise AND.590/// \param __b591/// A 256-bit vector of [8 x float] containing the right source operand.592/// \returns A 256-bit vector of [8 x float] containing the bitwise AND of the593/// values of the second operand and the one's complement of the first594/// operand.595static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR596_mm256_andnot_ps(__m256 __a, __m256 __b)597{598 return (__m256)(~(__v8su)__a & (__v8su)__b);599}600 601/// Performs a bitwise OR of two 256-bit vectors of [4 x double].602///603/// \headerfile <x86intrin.h>604///605/// This intrinsic corresponds to the <c> VORPD </c> instruction.606///607/// \param __a608/// A 256-bit vector of [4 x double] containing one of the source operands.609/// \param __b610/// A 256-bit vector of [4 x double] containing one of the source operands.611/// \returns A 256-bit vector of [4 x double] containing the bitwise OR of the612/// values between both operands.613static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR614_mm256_or_pd(__m256d __a, __m256d __b)615{616 return (__m256d)((__v4du)__a | (__v4du)__b);617}618 619/// Performs a bitwise OR of two 256-bit vectors of [8 x float].620///621/// \headerfile <x86intrin.h>622///623/// This intrinsic corresponds to the <c> VORPS </c> instruction.624///625/// \param __a626/// A 256-bit vector of [8 x float] containing one of the source operands.627/// \param __b628/// A 256-bit vector of [8 x float] containing one of the source operands.629/// \returns A 256-bit vector of [8 x float] containing the bitwise OR of the630/// values between both operands.631static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR632_mm256_or_ps(__m256 __a, __m256 __b)633{634 return (__m256)((__v8su)__a | (__v8su)__b);635}636 637/// Performs a bitwise XOR of two 256-bit vectors of [4 x double].638///639/// \headerfile <x86intrin.h>640///641/// This intrinsic corresponds to the <c> VXORPD </c> instruction.642///643/// \param __a644/// A 256-bit vector of [4 x double] containing one of the source operands.645/// \param __b646/// A 256-bit vector of [4 x double] containing one of the source operands.647/// \returns A 256-bit vector of [4 x double] containing the bitwise XOR of the648/// values between both operands.649static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR650_mm256_xor_pd(__m256d __a, __m256d __b)651{652 return (__m256d)((__v4du)__a ^ (__v4du)__b);653}654 655/// Performs a bitwise XOR of two 256-bit vectors of [8 x float].656///657/// \headerfile <x86intrin.h>658///659/// This intrinsic corresponds to the <c> VXORPS </c> instruction.660///661/// \param __a662/// A 256-bit vector of [8 x float] containing one of the source operands.663/// \param __b664/// A 256-bit vector of [8 x float] containing one of the source operands.665/// \returns A 256-bit vector of [8 x float] containing the bitwise XOR of the666/// values between both operands.667static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR668_mm256_xor_ps(__m256 __a, __m256 __b)669{670 return (__m256)((__v8su)__a ^ (__v8su)__b);671}672 673/* Horizontal arithmetic */674/// Horizontally adds the adjacent pairs of values contained in two675/// 256-bit vectors of [4 x double].676///677/// \headerfile <x86intrin.h>678///679/// This intrinsic corresponds to the <c> VHADDPD </c> instruction.680///681/// \param __a682/// A 256-bit vector of [4 x double] containing one of the source operands.683/// The horizontal sums of the values are returned in the even-indexed684/// elements of a vector of [4 x double].685/// \param __b686/// A 256-bit vector of [4 x double] containing one of the source operands.687/// The horizontal sums of the values are returned in the odd-indexed688/// elements of a vector of [4 x double].689/// \returns A 256-bit vector of [4 x double] containing the horizontal sums of690/// both operands.691static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR692_mm256_hadd_pd(__m256d __a, __m256d __b) {693 return (__m256d)__builtin_ia32_haddpd256((__v4df)__a, (__v4df)__b);694}695 696/// Horizontally adds the adjacent pairs of values contained in two697/// 256-bit vectors of [8 x float].698///699/// \headerfile <x86intrin.h>700///701/// This intrinsic corresponds to the <c> VHADDPS </c> instruction.702///703/// \param __a704/// A 256-bit vector of [8 x float] containing one of the source operands.705/// The horizontal sums of the values are returned in the elements with706/// index 0, 1, 4, 5 of a vector of [8 x float].707/// \param __b708/// A 256-bit vector of [8 x float] containing one of the source operands.709/// The horizontal sums of the values are returned in the elements with710/// index 2, 3, 6, 7 of a vector of [8 x float].711/// \returns A 256-bit vector of [8 x float] containing the horizontal sums of712/// both operands.713static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_hadd_ps(__m256 __a,714 __m256 __b) {715 return (__m256)__builtin_ia32_haddps256((__v8sf)__a, (__v8sf)__b);716}717 718/// Horizontally subtracts the adjacent pairs of values contained in two719/// 256-bit vectors of [4 x double].720///721/// \headerfile <x86intrin.h>722///723/// This intrinsic corresponds to the <c> VHSUBPD </c> instruction.724///725/// \param __a726/// A 256-bit vector of [4 x double] containing one of the source operands.727/// The horizontal differences between the values are returned in the728/// even-indexed elements of a vector of [4 x double].729/// \param __b730/// A 256-bit vector of [4 x double] containing one of the source operands.731/// The horizontal differences between the values are returned in the732/// odd-indexed elements of a vector of [4 x double].733/// \returns A 256-bit vector of [4 x double] containing the horizontal734/// differences of both operands.735static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR736_mm256_hsub_pd(__m256d __a, __m256d __b) {737 return (__m256d)__builtin_ia32_hsubpd256((__v4df)__a, (__v4df)__b);738}739 740/// Horizontally subtracts the adjacent pairs of values contained in two741/// 256-bit vectors of [8 x float].742///743/// \headerfile <x86intrin.h>744///745/// This intrinsic corresponds to the <c> VHSUBPS </c> instruction.746///747/// \param __a748/// A 256-bit vector of [8 x float] containing one of the source operands.749/// The horizontal differences between the values are returned in the750/// elements with index 0, 1, 4, 5 of a vector of [8 x float].751/// \param __b752/// A 256-bit vector of [8 x float] containing one of the source operands.753/// The horizontal differences between the values are returned in the754/// elements with index 2, 3, 6, 7 of a vector of [8 x float].755/// \returns A 256-bit vector of [8 x float] containing the horizontal756/// differences of both operands.757static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_hsub_ps(__m256 __a,758 __m256 __b) {759 return (__m256)__builtin_ia32_hsubps256((__v8sf)__a, (__v8sf)__b);760}761 762/* Vector permutations */763/// Copies the values in a 128-bit vector of [2 x double] as specified764/// by the 128-bit integer vector operand.765///766/// \headerfile <x86intrin.h>767///768/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction.769///770/// \param __a771/// A 128-bit vector of [2 x double].772/// \param __c773/// A 128-bit integer vector operand specifying how the values are to be774/// copied. \n775/// Bit [1]: \n776/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned777/// vector. \n778/// 1: Bits [127:64] of the source are copied to bits [63:0] of the779/// returned vector. \n780/// Bit [65]: \n781/// 0: Bits [63:0] of the source are copied to bits [127:64] of the782/// returned vector. \n783/// 1: Bits [127:64] of the source are copied to bits [127:64] of the784/// returned vector.785/// \returns A 128-bit vector of [2 x double] containing the copied values.786static __inline __m128d __DEFAULT_FN_ATTRS128_CONSTEXPR787_mm_permutevar_pd(__m128d __a, __m128i __c) {788 return (__m128d)__builtin_ia32_vpermilvarpd((__v2df)__a, (__v2di)__c);789}790 791/// Copies the values in a 256-bit vector of [4 x double] as specified792/// by the 256-bit integer vector operand.793///794/// \headerfile <x86intrin.h>795///796/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction.797///798/// \param __a799/// A 256-bit vector of [4 x double].800/// \param __c801/// A 256-bit integer vector operand specifying how the values are to be802/// copied. \n803/// Bit [1]: \n804/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned805/// vector. \n806/// 1: Bits [127:64] of the source are copied to bits [63:0] of the807/// returned vector. \n808/// Bit [65]: \n809/// 0: Bits [63:0] of the source are copied to bits [127:64] of the810/// returned vector. \n811/// 1: Bits [127:64] of the source are copied to bits [127:64] of the812/// returned vector. \n813/// Bit [129]: \n814/// 0: Bits [191:128] of the source are copied to bits [191:128] of the815/// returned vector. \n816/// 1: Bits [255:192] of the source are copied to bits [191:128] of the817/// returned vector. \n818/// Bit [193]: \n819/// 0: Bits [191:128] of the source are copied to bits [255:192] of the820/// returned vector. \n821/// 1: Bits [255:192] of the source are copied to bits [255:192] of the822/// returned vector.823/// \returns A 256-bit vector of [4 x double] containing the copied values.824static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR825_mm256_permutevar_pd(__m256d __a, __m256i __c) {826 return (__m256d)__builtin_ia32_vpermilvarpd256((__v4df)__a, (__v4di)__c);827}828 829/// Copies the values stored in a 128-bit vector of [4 x float] as830/// specified by the 128-bit integer vector operand.831///832/// \headerfile <x86intrin.h>833///834/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction.835///836/// \param __a837/// A 128-bit vector of [4 x float].838/// \param __c839/// A 128-bit integer vector operand specifying how the values are to be840/// copied. \n841/// Bits [1:0]: \n842/// 00: Bits [31:0] of the source are copied to bits [31:0] of the843/// returned vector. \n844/// 01: Bits [63:32] of the source are copied to bits [31:0] of the845/// returned vector. \n846/// 10: Bits [95:64] of the source are copied to bits [31:0] of the847/// returned vector. \n848/// 11: Bits [127:96] of the source are copied to bits [31:0] of the849/// returned vector. \n850/// Bits [33:32]: \n851/// 00: Bits [31:0] of the source are copied to bits [63:32] of the852/// returned vector. \n853/// 01: Bits [63:32] of the source are copied to bits [63:32] of the854/// returned vector. \n855/// 10: Bits [95:64] of the source are copied to bits [63:32] of the856/// returned vector. \n857/// 11: Bits [127:96] of the source are copied to bits [63:32] of the858/// returned vector. \n859/// Bits [65:64]: \n860/// 00: Bits [31:0] of the source are copied to bits [95:64] of the861/// returned vector. \n862/// 01: Bits [63:32] of the source are copied to bits [95:64] of the863/// returned vector. \n864/// 10: Bits [95:64] of the source are copied to bits [95:64] of the865/// returned vector. \n866/// 11: Bits [127:96] of the source are copied to bits [95:64] of the867/// returned vector. \n868/// Bits [97:96]: \n869/// 00: Bits [31:0] of the source are copied to bits [127:96] of the870/// returned vector. \n871/// 01: Bits [63:32] of the source are copied to bits [127:96] of the872/// returned vector. \n873/// 10: Bits [95:64] of the source are copied to bits [127:96] of the874/// returned vector. \n875/// 11: Bits [127:96] of the source are copied to bits [127:96] of the876/// returned vector.877/// \returns A 128-bit vector of [4 x float] containing the copied values.878static __inline __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR879_mm_permutevar_ps(__m128 __a, __m128i __c) {880 return (__m128)__builtin_ia32_vpermilvarps((__v4sf)__a, (__v4si)__c);881}882 883/// Copies the values stored in a 256-bit vector of [8 x float] as884/// specified by the 256-bit integer vector operand.885///886/// \headerfile <x86intrin.h>887///888/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction.889///890/// \param __a891/// A 256-bit vector of [8 x float].892/// \param __c893/// A 256-bit integer vector operand specifying how the values are to be894/// copied. \n895/// Bits [1:0]: \n896/// 00: Bits [31:0] of the source are copied to bits [31:0] of the897/// returned vector. \n898/// 01: Bits [63:32] of the source are copied to bits [31:0] of the899/// returned vector. \n900/// 10: Bits [95:64] of the source are copied to bits [31:0] of the901/// returned vector. \n902/// 11: Bits [127:96] of the source are copied to bits [31:0] of the903/// returned vector. \n904/// Bits [33:32]: \n905/// 00: Bits [31:0] of the source are copied to bits [63:32] of the906/// returned vector. \n907/// 01: Bits [63:32] of the source are copied to bits [63:32] of the908/// returned vector. \n909/// 10: Bits [95:64] of the source are copied to bits [63:32] of the910/// returned vector. \n911/// 11: Bits [127:96] of the source are copied to bits [63:32] of the912/// returned vector. \n913/// Bits [65:64]: \n914/// 00: Bits [31:0] of the source are copied to bits [95:64] of the915/// returned vector. \n916/// 01: Bits [63:32] of the source are copied to bits [95:64] of the917/// returned vector. \n918/// 10: Bits [95:64] of the source are copied to bits [95:64] of the919/// returned vector. \n920/// 11: Bits [127:96] of the source are copied to bits [95:64] of the921/// returned vector. \n922/// Bits [97:96]: \n923/// 00: Bits [31:0] of the source are copied to bits [127:96] of the924/// returned vector. \n925/// 01: Bits [63:32] of the source are copied to bits [127:96] of the926/// returned vector. \n927/// 10: Bits [95:64] of the source are copied to bits [127:96] of the928/// returned vector. \n929/// 11: Bits [127:96] of the source are copied to bits [127:96] of the930/// returned vector. \n931/// Bits [129:128]: \n932/// 00: Bits [159:128] of the source are copied to bits [159:128] of the933/// returned vector. \n934/// 01: Bits [191:160] of the source are copied to bits [159:128] of the935/// returned vector. \n936/// 10: Bits [223:192] of the source are copied to bits [159:128] of the937/// returned vector. \n938/// 11: Bits [255:224] of the source are copied to bits [159:128] of the939/// returned vector. \n940/// Bits [161:160]: \n941/// 00: Bits [159:128] of the source are copied to bits [191:160] of the942/// returned vector. \n943/// 01: Bits [191:160] of the source are copied to bits [191:160] of the944/// returned vector. \n945/// 10: Bits [223:192] of the source are copied to bits [191:160] of the946/// returned vector. \n947/// 11: Bits [255:224] of the source are copied to bits [191:160] of the948/// returned vector. \n949/// Bits [193:192]: \n950/// 00: Bits [159:128] of the source are copied to bits [223:192] of the951/// returned vector. \n952/// 01: Bits [191:160] of the source are copied to bits [223:192] of the953/// returned vector. \n954/// 10: Bits [223:192] of the source are copied to bits [223:192] of the955/// returned vector. \n956/// 11: Bits [255:224] of the source are copied to bits [223:192] of the957/// returned vector. \n958/// Bits [225:224]: \n959/// 00: Bits [159:128] of the source are copied to bits [255:224] of the960/// returned vector. \n961/// 01: Bits [191:160] of the source are copied to bits [255:224] of the962/// returned vector. \n963/// 10: Bits [223:192] of the source are copied to bits [255:224] of the964/// returned vector. \n965/// 11: Bits [255:224] of the source are copied to bits [255:224] of the966/// returned vector.967/// \returns A 256-bit vector of [8 x float] containing the copied values.968static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR969_mm256_permutevar_ps(__m256 __a, __m256i __c) {970 return (__m256)__builtin_ia32_vpermilvarps256((__v8sf)__a, (__v8si)__c);971}972 973/// Copies the values in a 128-bit vector of [2 x double] as specified974/// by the immediate integer operand.975///976/// \headerfile <x86intrin.h>977///978/// \code979/// __m128d _mm_permute_pd(__m128d A, const int C);980/// \endcode981///982/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction.983///984/// \param A985/// A 128-bit vector of [2 x double].986/// \param C987/// An immediate integer operand specifying how the values are to be988/// copied. \n989/// Bit [0]: \n990/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned991/// vector. \n992/// 1: Bits [127:64] of the source are copied to bits [63:0] of the993/// returned vector. \n994/// Bit [1]: \n995/// 0: Bits [63:0] of the source are copied to bits [127:64] of the996/// returned vector. \n997/// 1: Bits [127:64] of the source are copied to bits [127:64] of the998/// returned vector.999/// \returns A 128-bit vector of [2 x double] containing the copied values.1000#define _mm_permute_pd(A, C) \1001 ((__m128d)__builtin_ia32_vpermilpd((__v2df)(__m128d)(A), (int)(C)))1002 1003/// Copies the values in a 256-bit vector of [4 x double] as specified by1004/// the immediate integer operand.1005///1006/// \headerfile <x86intrin.h>1007///1008/// \code1009/// __m256d _mm256_permute_pd(__m256d A, const int C);1010/// \endcode1011///1012/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction.1013///1014/// \param A1015/// A 256-bit vector of [4 x double].1016/// \param C1017/// An immediate integer operand specifying how the values are to be1018/// copied. \n1019/// Bit [0]: \n1020/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned1021/// vector. \n1022/// 1: Bits [127:64] of the source are copied to bits [63:0] of the1023/// returned vector. \n1024/// Bit [1]: \n1025/// 0: Bits [63:0] of the source are copied to bits [127:64] of the1026/// returned vector. \n1027/// 1: Bits [127:64] of the source are copied to bits [127:64] of the1028/// returned vector. \n1029/// Bit [2]: \n1030/// 0: Bits [191:128] of the source are copied to bits [191:128] of the1031/// returned vector. \n1032/// 1: Bits [255:192] of the source are copied to bits [191:128] of the1033/// returned vector. \n1034/// Bit [3]: \n1035/// 0: Bits [191:128] of the source are copied to bits [255:192] of the1036/// returned vector. \n1037/// 1: Bits [255:192] of the source are copied to bits [255:192] of the1038/// returned vector.1039/// \returns A 256-bit vector of [4 x double] containing the copied values.1040#define _mm256_permute_pd(A, C) \1041 ((__m256d)__builtin_ia32_vpermilpd256((__v4df)(__m256d)(A), (int)(C)))1042 1043/// Copies the values in a 128-bit vector of [4 x float] as specified by1044/// the immediate integer operand.1045///1046/// \headerfile <x86intrin.h>1047///1048/// \code1049/// __m128 _mm_permute_ps(__m128 A, const int C);1050/// \endcode1051///1052/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction.1053///1054/// \param A1055/// A 128-bit vector of [4 x float].1056/// \param C1057/// An immediate integer operand specifying how the values are to be1058/// copied. \n1059/// Bits [1:0]: \n1060/// 00: Bits [31:0] of the source are copied to bits [31:0] of the1061/// returned vector. \n1062/// 01: Bits [63:32] of the source are copied to bits [31:0] of the1063/// returned vector. \n1064/// 10: Bits [95:64] of the source are copied to bits [31:0] of the1065/// returned vector. \n1066/// 11: Bits [127:96] of the source are copied to bits [31:0] of the1067/// returned vector. \n1068/// Bits [3:2]: \n1069/// 00: Bits [31:0] of the source are copied to bits [63:32] of the1070/// returned vector. \n1071/// 01: Bits [63:32] of the source are copied to bits [63:32] of the1072/// returned vector. \n1073/// 10: Bits [95:64] of the source are copied to bits [63:32] of the1074/// returned vector. \n1075/// 11: Bits [127:96] of the source are copied to bits [63:32] of the1076/// returned vector. \n1077/// Bits [5:4]: \n1078/// 00: Bits [31:0] of the source are copied to bits [95:64] of the1079/// returned vector. \n1080/// 01: Bits [63:32] of the source are copied to bits [95:64] of the1081/// returned vector. \n1082/// 10: Bits [95:64] of the source are copied to bits [95:64] of the1083/// returned vector. \n1084/// 11: Bits [127:96] of the source are copied to bits [95:64] of the1085/// returned vector. \n1086/// Bits [7:6]: \n1087/// 00: Bits [31:0] of the source are copied to bits [127:96] of the1088/// returned vector. \n1089/// 01: Bits [63:32] of the source are copied to bits [127:96] of the1090/// returned vector. \n1091/// 10: Bits [95:64] of the source are copied to bits [127:96] of the1092/// returned vector. \n1093/// 11: Bits [127:96] of the source are copied to bits [127:96] of the1094/// returned vector.1095/// \returns A 128-bit vector of [4 x float] containing the copied values.1096#define _mm_permute_ps(A, C) \1097 ((__m128)__builtin_ia32_vpermilps((__v4sf)(__m128)(A), (int)(C)))1098 1099/// Copies the values in a 256-bit vector of [8 x float] as specified by1100/// the immediate integer operand.1101///1102/// \headerfile <x86intrin.h>1103///1104/// \code1105/// __m256 _mm256_permute_ps(__m256 A, const int C);1106/// \endcode1107///1108/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction.1109///1110/// \param A1111/// A 256-bit vector of [8 x float].1112/// \param C1113/// An immediate integer operand specifying how the values are to be1114/// copied. \n1115/// Bits [1:0]: \n1116/// 00: Bits [31:0] of the source are copied to bits [31:0] of the1117/// returned vector. \n1118/// 01: Bits [63:32] of the source are copied to bits [31:0] of the1119/// returned vector. \n1120/// 10: Bits [95:64] of the source are copied to bits [31:0] of the1121/// returned vector. \n1122/// 11: Bits [127:96] of the source are copied to bits [31:0] of the1123/// returned vector. \n1124/// Bits [3:2]: \n1125/// 00: Bits [31:0] of the source are copied to bits [63:32] of the1126/// returned vector. \n1127/// 01: Bits [63:32] of the source are copied to bits [63:32] of the1128/// returned vector. \n1129/// 10: Bits [95:64] of the source are copied to bits [63:32] of the1130/// returned vector. \n1131/// 11: Bits [127:96] of the source are copied to bits [63:32] of the1132/// returned vector. \n1133/// Bits [5:4]: \n1134/// 00: Bits [31:0] of the source are copied to bits [95:64] of the1135/// returned vector. \n1136/// 01: Bits [63:32] of the source are copied to bits [95:64] of the1137/// returned vector. \n1138/// 10: Bits [95:64] of the source are copied to bits [95:64] of the1139/// returned vector. \n1140/// 11: Bits [127:96] of the source are copied to bits [95:64] of the1141/// returned vector. \n1142/// Bits [7:6]: \n1143/// 00: Bits [31:0] of the source are copied to bits [127:96] of the1144/// returned vector. \n1145/// 01: Bits [63:32] of the source are copied to bits [127:96] of the1146/// returned vector. \n1147/// 10: Bits [95:64] of the source are copied to bits [127:96] of the1148/// returned vector. \n1149/// 11: Bits [127:96] of the source are copied to bits [127:96] of the1150/// returned vector. \n1151/// Bits [1:0]: \n1152/// 00: Bits [159:128] of the source are copied to bits [159:128] of the1153/// returned vector. \n1154/// 01: Bits [191:160] of the source are copied to bits [159:128] of the1155/// returned vector. \n1156/// 10: Bits [223:192] of the source are copied to bits [159:128] of the1157/// returned vector. \n1158/// 11: Bits [255:224] of the source are copied to bits [159:128] of the1159/// returned vector. \n1160/// Bits [3:2]: \n1161/// 00: Bits [159:128] of the source are copied to bits [191:160] of the1162/// returned vector. \n1163/// 01: Bits [191:160] of the source are copied to bits [191:160] of the1164/// returned vector. \n1165/// 10: Bits [223:192] of the source are copied to bits [191:160] of the1166/// returned vector. \n1167/// 11: Bits [255:224] of the source are copied to bits [191:160] of the1168/// returned vector. \n1169/// Bits [5:4]: \n1170/// 00: Bits [159:128] of the source are copied to bits [223:192] of the1171/// returned vector. \n1172/// 01: Bits [191:160] of the source are copied to bits [223:192] of the1173/// returned vector. \n1174/// 10: Bits [223:192] of the source are copied to bits [223:192] of the1175/// returned vector. \n1176/// 11: Bits [255:224] of the source are copied to bits [223:192] of the1177/// returned vector. \n1178/// Bits [7:6]: \n1179/// 00: Bits [159:128] of the source are copied to bits [255:224] of the1180/// returned vector. \n1181/// 01: Bits [191:160] of the source are copied to bits [255:224] of the1182/// returned vector. \n1183/// 10: Bits [223:192] of the source are copied to bits [255:224] of the1184/// returned vector. \n1185/// 11: Bits [255:224] of the source are copied to bits [255:224] of the1186/// returned vector.1187/// \returns A 256-bit vector of [8 x float] containing the copied values.1188#define _mm256_permute_ps(A, C) \1189 ((__m256)__builtin_ia32_vpermilps256((__v8sf)(__m256)(A), (int)(C)))1190 1191/// Permutes 128-bit data values stored in two 256-bit vectors of1192/// [4 x double], as specified by the immediate integer operand.1193///1194/// \headerfile <x86intrin.h>1195///1196/// \code1197/// __m256d _mm256_permute2f128_pd(__m256d V1, __m256d V2, const int M);1198/// \endcode1199///1200/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction.1201///1202/// \param V11203/// A 256-bit vector of [4 x double].1204/// \param V21205/// A 256-bit vector of [4 x double.1206/// \param M1207/// An immediate integer operand specifying how the values are to be1208/// permuted. \n1209/// Bits [1:0]: \n1210/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the1211/// destination. \n1212/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the1213/// destination. \n1214/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the1215/// destination. \n1216/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the1217/// destination. \n1218/// Bits [5:4]: \n1219/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the1220/// destination. \n1221/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the1222/// destination. \n1223/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the1224/// destination. \n1225/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the1226/// destination.1227/// \returns A 256-bit vector of [4 x double] containing the copied values.1228#define _mm256_permute2f128_pd(V1, V2, M) \1229 ((__m256d)__builtin_ia32_vperm2f128_pd256((__v4df)(__m256d)(V1), \1230 (__v4df)(__m256d)(V2), (int)(M)))1231 1232/// Permutes 128-bit data values stored in two 256-bit vectors of1233/// [8 x float], as specified by the immediate integer operand.1234///1235/// \headerfile <x86intrin.h>1236///1237/// \code1238/// __m256 _mm256_permute2f128_ps(__m256 V1, __m256 V2, const int M);1239/// \endcode1240///1241/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction.1242///1243/// \param V11244/// A 256-bit vector of [8 x float].1245/// \param V21246/// A 256-bit vector of [8 x float].1247/// \param M1248/// An immediate integer operand specifying how the values are to be1249/// permuted. \n1250/// Bits [1:0]: \n1251/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the1252/// destination. \n1253/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the1254/// destination. \n1255/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the1256/// destination. \n1257/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the1258/// destination. \n1259/// Bits [5:4]: \n1260/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the1261/// destination. \n1262/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the1263/// destination. \n1264/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the1265/// destination. \n1266/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the1267/// destination.1268/// \returns A 256-bit vector of [8 x float] containing the copied values.1269#define _mm256_permute2f128_ps(V1, V2, M) \1270 ((__m256)__builtin_ia32_vperm2f128_ps256((__v8sf)(__m256)(V1), \1271 (__v8sf)(__m256)(V2), (int)(M)))1272 1273/// Permutes 128-bit data values stored in two 256-bit integer vectors,1274/// as specified by the immediate integer operand.1275///1276/// \headerfile <x86intrin.h>1277///1278/// \code1279/// __m256i _mm256_permute2f128_si256(__m256i V1, __m256i V2, const int M);1280/// \endcode1281///1282/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction.1283///1284/// \param V11285/// A 256-bit integer vector.1286/// \param V21287/// A 256-bit integer vector.1288/// \param M1289/// An immediate integer operand specifying how the values are to be copied.1290/// Bits [1:0]: \n1291/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the1292/// destination. \n1293/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the1294/// destination. \n1295/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the1296/// destination. \n1297/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the1298/// destination. \n1299/// Bits [5:4]: \n1300/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the1301/// destination. \n1302/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the1303/// destination. \n1304/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the1305/// destination. \n1306/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the1307/// destination.1308/// \returns A 256-bit integer vector containing the copied values.1309#define _mm256_permute2f128_si256(V1, V2, M) \1310 ((__m256i)__builtin_ia32_vperm2f128_si256((__v8si)(__m256i)(V1), \1311 (__v8si)(__m256i)(V2), (int)(M)))1312 1313/* Vector Blend */1314/// Merges 64-bit double-precision data values stored in either of the1315/// two 256-bit vectors of [4 x double], as specified by the immediate1316/// integer operand.1317///1318/// \headerfile <x86intrin.h>1319///1320/// \code1321/// __m256d _mm256_blend_pd(__m256d V1, __m256d V2, const int M);1322/// \endcode1323///1324/// This intrinsic corresponds to the <c> VBLENDPD </c> instruction.1325///1326/// \param V11327/// A 256-bit vector of [4 x double].1328/// \param V21329/// A 256-bit vector of [4 x double].1330/// \param M1331/// An immediate integer operand, with mask bits [3:0] specifying how the1332/// values are to be copied. The position of the mask bit corresponds to the1333/// index of a copied value. When a mask bit is 0, the corresponding 64-bit1334/// element in operand \a V1 is copied to the same position in the1335/// destination. When a mask bit is 1, the corresponding 64-bit element in1336/// operand \a V2 is copied to the same position in the destination.1337/// \returns A 256-bit vector of [4 x double] containing the copied values.1338#define _mm256_blend_pd(V1, V2, M) \1339 ((__m256d)__builtin_ia32_blendpd256((__v4df)(__m256d)(V1), \1340 (__v4df)(__m256d)(V2), (int)(M)))1341 1342/// Merges 32-bit single-precision data values stored in either of the1343/// two 256-bit vectors of [8 x float], as specified by the immediate1344/// integer operand.1345///1346/// \headerfile <x86intrin.h>1347///1348/// \code1349/// __m256 _mm256_blend_ps(__m256 V1, __m256 V2, const int M);1350/// \endcode1351///1352/// This intrinsic corresponds to the <c> VBLENDPS </c> instruction.1353///1354/// \param V11355/// A 256-bit vector of [8 x float].1356/// \param V21357/// A 256-bit vector of [8 x float].1358/// \param M1359/// An immediate integer operand, with mask bits [7:0] specifying how the1360/// values are to be copied. The position of the mask bit corresponds to the1361/// index of a copied value. When a mask bit is 0, the corresponding 32-bit1362/// element in operand \a V1 is copied to the same position in the1363/// destination. When a mask bit is 1, the corresponding 32-bit element in1364/// operand \a V2 is copied to the same position in the destination.1365/// \returns A 256-bit vector of [8 x float] containing the copied values.1366#define _mm256_blend_ps(V1, V2, M) \1367 ((__m256)__builtin_ia32_blendps256((__v8sf)(__m256)(V1), \1368 (__v8sf)(__m256)(V2), (int)(M)))1369 1370/// Merges 64-bit double-precision data values stored in either of the1371/// two 256-bit vectors of [4 x double], as specified by the 256-bit vector1372/// operand.1373///1374/// \headerfile <x86intrin.h>1375///1376/// This intrinsic corresponds to the <c> VBLENDVPD </c> instruction.1377///1378/// \param __a1379/// A 256-bit vector of [4 x double].1380/// \param __b1381/// A 256-bit vector of [4 x double].1382/// \param __c1383/// A 256-bit vector operand, with mask bits 255, 191, 127, and 63 specifying1384/// how the values are to be copied. The position of the mask bit corresponds1385/// to the most significant bit of a copied value. When a mask bit is 0, the1386/// corresponding 64-bit element in operand \a __a is copied to the same1387/// position in the destination. When a mask bit is 1, the corresponding1388/// 64-bit element in operand \a __b is copied to the same position in the1389/// destination.1390/// \returns A 256-bit vector of [4 x double] containing the copied values.1391static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR1392_mm256_blendv_pd(__m256d __a, __m256d __b, __m256d __c) {1393 return (__m256d)__builtin_ia32_blendvpd256(1394 (__v4df)__a, (__v4df)__b, (__v4df)__c);1395}1396 1397/// Merges 32-bit single-precision data values stored in either of the1398/// two 256-bit vectors of [8 x float], as specified by the 256-bit vector1399/// operand.1400///1401/// \headerfile <x86intrin.h>1402///1403/// This intrinsic corresponds to the <c> VBLENDVPS </c> instruction.1404///1405/// \param __a1406/// A 256-bit vector of [8 x float].1407/// \param __b1408/// A 256-bit vector of [8 x float].1409/// \param __c1410/// A 256-bit vector operand, with mask bits 255, 223, 191, 159, 127, 95, 63,1411/// and 31 specifying how the values are to be copied. The position of the1412/// mask bit corresponds to the most significant bit of a copied value. When1413/// a mask bit is 0, the corresponding 32-bit element in operand \a __a is1414/// copied to the same position in the destination. When a mask bit is 1, the1415/// corresponding 32-bit element in operand \a __b is copied to the same1416/// position in the destination.1417/// \returns A 256-bit vector of [8 x float] containing the copied values.1418static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR1419_mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) {1420 return (__m256)__builtin_ia32_blendvps256(1421 (__v8sf)__a, (__v8sf)__b, (__v8sf)__c);1422}1423 1424/* Vector Dot Product */1425/// Computes two dot products in parallel, using the lower and upper1426/// halves of two [8 x float] vectors as input to the two computations, and1427/// returning the two dot products in the lower and upper halves of the1428/// [8 x float] result.1429///1430/// The immediate integer operand controls which input elements will1431/// contribute to the dot product, and where the final results are returned.1432/// In general, for each dot product, the four corresponding elements of the1433/// input vectors are multiplied; the first two and second two products are1434/// summed, then the two sums are added to form the final result.1435///1436/// \headerfile <x86intrin.h>1437///1438/// \code1439/// __m256 _mm256_dp_ps(__m256 V1, __m256 V2, const int M);1440/// \endcode1441///1442/// This intrinsic corresponds to the <c> VDPPS </c> instruction.1443///1444/// \param V11445/// A vector of [8 x float] values, treated as two [4 x float] vectors.1446/// \param V21447/// A vector of [8 x float] values, treated as two [4 x float] vectors.1448/// \param M1449/// An immediate integer argument. Bits [7:4] determine which elements of1450/// the input vectors are used, with bit [4] corresponding to the lowest1451/// element and bit [7] corresponding to the highest element of each [4 x1452/// float] subvector. If a bit is set, the corresponding elements from the1453/// two input vectors are used as an input for dot product; otherwise that1454/// input is treated as zero. Bits [3:0] determine which elements of the1455/// result will receive a copy of the final dot product, with bit [0]1456/// corresponding to the lowest element and bit [3] corresponding to the1457/// highest element of each [4 x float] subvector. If a bit is set, the dot1458/// product is returned in the corresponding element; otherwise that element1459/// is set to zero. The bitmask is applied in the same way to each of the1460/// two parallel dot product computations.1461/// \returns A 256-bit vector of [8 x float] containing the two dot products.1462#define _mm256_dp_ps(V1, V2, M) \1463 ((__m256)__builtin_ia32_dpps256((__v8sf)(__m256)(V1), \1464 (__v8sf)(__m256)(V2), (M)))1465 1466/* Vector shuffle */1467/// Selects 8 float values from the 256-bit operands of [8 x float], as1468/// specified by the immediate value operand.1469///1470/// The four selected elements in each operand are copied to the destination1471/// according to the bits specified in the immediate operand. The selected1472/// elements from the first 256-bit operand are copied to bits [63:0] and1473/// bits [191:128] of the destination, and the selected elements from the1474/// second 256-bit operand are copied to bits [127:64] and bits [255:192] of1475/// the destination. For example, if bits [7:0] of the immediate operand1476/// contain a value of 0xFF, the 256-bit destination vector would contain the1477/// following values: b[7], b[7], a[7], a[7], b[3], b[3], a[3], a[3].1478///1479/// \headerfile <x86intrin.h>1480///1481/// \code1482/// __m256 _mm256_shuffle_ps(__m256 a, __m256 b, const int mask);1483/// \endcode1484///1485/// This intrinsic corresponds to the <c> VSHUFPS </c> instruction.1486///1487/// \param a1488/// A 256-bit vector of [8 x float]. The four selected elements in this1489/// operand are copied to bits [63:0] and bits [191:128] in the destination,1490/// according to the bits specified in the immediate operand.1491/// \param b1492/// A 256-bit vector of [8 x float]. The four selected elements in this1493/// operand are copied to bits [127:64] and bits [255:192] in the1494/// destination, according to the bits specified in the immediate operand.1495/// \param mask1496/// An immediate value containing an 8-bit value specifying which elements to1497/// copy from \a a and \a b \n.1498/// Bits [3:0] specify the values copied from operand \a a. \n1499/// Bits [7:4] specify the values copied from operand \a b. \n1500/// The destinations within the 256-bit destination are assigned values as1501/// follows, according to the bit value assignments described below: \n1502/// Bits [1:0] are used to assign values to bits [31:0] and [159:128] in the1503/// destination. \n1504/// Bits [3:2] are used to assign values to bits [63:32] and [191:160] in the1505/// destination. \n1506/// Bits [5:4] are used to assign values to bits [95:64] and [223:192] in the1507/// destination. \n1508/// Bits [7:6] are used to assign values to bits [127:96] and [255:224] in1509/// the destination. \n1510/// Bit value assignments: \n1511/// 00: Bits [31:0] and [159:128] are copied from the selected operand. \n1512/// 01: Bits [63:32] and [191:160] are copied from the selected operand. \n1513/// 10: Bits [95:64] and [223:192] are copied from the selected operand. \n1514/// 11: Bits [127:96] and [255:224] are copied from the selected operand. \n1515/// Note: To generate a mask, you can use the \c _MM_SHUFFLE macro.1516/// <c>_MM_SHUFFLE(b6, b4, b2, b0)</c> can create an 8-bit mask of the form1517/// <c>[b6, b4, b2, b0]</c>.1518/// \returns A 256-bit vector of [8 x float] containing the shuffled values.1519#define _mm256_shuffle_ps(a, b, mask) \1520 ((__m256)__builtin_ia32_shufps256((__v8sf)(__m256)(a), \1521 (__v8sf)(__m256)(b), (int)(mask)))1522 1523/// Selects four double-precision values from the 256-bit operands of1524/// [4 x double], as specified by the immediate value operand.1525///1526/// The selected elements from the first 256-bit operand are copied to bits1527/// [63:0] and bits [191:128] in the destination, and the selected elements1528/// from the second 256-bit operand are copied to bits [127:64] and bits1529/// [255:192] in the destination. For example, if bits [3:0] of the immediate1530/// operand contain a value of 0xF, the 256-bit destination vector would1531/// contain the following values: b[3], a[3], b[1], a[1].1532///1533/// \headerfile <x86intrin.h>1534///1535/// \code1536/// __m256d _mm256_shuffle_pd(__m256d a, __m256d b, const int mask);1537/// \endcode1538///1539/// This intrinsic corresponds to the <c> VSHUFPD </c> instruction.1540///1541/// \param a1542/// A 256-bit vector of [4 x double].1543/// \param b1544/// A 256-bit vector of [4 x double].1545/// \param mask1546/// An immediate value containing 8-bit values specifying which elements to1547/// copy from \a a and \a b: \n1548/// Bit [0]=0: Bits [63:0] are copied from \a a to bits [63:0] of the1549/// destination. \n1550/// Bit [0]=1: Bits [127:64] are copied from \a a to bits [63:0] of the1551/// destination. \n1552/// Bit [1]=0: Bits [63:0] are copied from \a b to bits [127:64] of the1553/// destination. \n1554/// Bit [1]=1: Bits [127:64] are copied from \a b to bits [127:64] of the1555/// destination. \n1556/// Bit [2]=0: Bits [191:128] are copied from \a a to bits [191:128] of the1557/// destination. \n1558/// Bit [2]=1: Bits [255:192] are copied from \a a to bits [191:128] of the1559/// destination. \n1560/// Bit [3]=0: Bits [191:128] are copied from \a b to bits [255:192] of the1561/// destination. \n1562/// Bit [3]=1: Bits [255:192] are copied from \a b to bits [255:192] of the1563/// destination.1564/// \returns A 256-bit vector of [4 x double] containing the shuffled values.1565#define _mm256_shuffle_pd(a, b, mask) \1566 ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \1567 (__v4df)(__m256d)(b), (int)(mask)))1568 1569/* Compare */1570#define _CMP_EQ_UQ 0x08 /* Equal (unordered, non-signaling) */1571#define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */1572#define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */1573#define _CMP_FALSE_OQ 0x0b /* False (ordered, non-signaling) */1574#define _CMP_NEQ_OQ 0x0c /* Not-equal (ordered, non-signaling) */1575#define _CMP_GE_OS 0x0d /* Greater-than-or-equal (ordered, signaling) */1576#define _CMP_GT_OS 0x0e /* Greater-than (ordered, signaling) */1577#define _CMP_TRUE_UQ 0x0f /* True (unordered, non-signaling) */1578#define _CMP_EQ_OS 0x10 /* Equal (ordered, signaling) */1579#define _CMP_LT_OQ 0x11 /* Less-than (ordered, non-signaling) */1580#define _CMP_LE_OQ 0x12 /* Less-than-or-equal (ordered, non-signaling) */1581#define _CMP_UNORD_S 0x13 /* Unordered (signaling) */1582#define _CMP_NEQ_US 0x14 /* Not-equal (unordered, signaling) */1583#define _CMP_NLT_UQ 0x15 /* Not-less-than (unordered, non-signaling) */1584#define _CMP_NLE_UQ 0x16 /* Not-less-than-or-equal (unordered, non-signaling) */1585#define _CMP_ORD_S 0x17 /* Ordered (signaling) */1586#define _CMP_EQ_US 0x18 /* Equal (unordered, signaling) */1587#define _CMP_NGE_UQ 0x19 /* Not-greater-than-or-equal (unordered, non-signaling) */1588#define _CMP_NGT_UQ 0x1a /* Not-greater-than (unordered, non-signaling) */1589#define _CMP_FALSE_OS 0x1b /* False (ordered, signaling) */1590#define _CMP_NEQ_OS 0x1c /* Not-equal (ordered, signaling) */1591#define _CMP_GE_OQ 0x1d /* Greater-than-or-equal (ordered, non-signaling) */1592#define _CMP_GT_OQ 0x1e /* Greater-than (ordered, non-signaling) */1593#define _CMP_TRUE_US 0x1f /* True (unordered, signaling) */1594 1595/* Below intrinsic defined in emmintrin.h can be used for AVX */1596/// Compares each of the corresponding double-precision values of two1597/// 128-bit vectors of [2 x double], using the operation specified by the1598/// immediate integer operand.1599///1600/// Each comparison returns 0x0 for false, 0xFFFFFFFFFFFFFFFF for true.1601/// If either value in a comparison is NaN, comparisons that are ordered1602/// return false, and comparisons that are unordered return true.1603///1604/// \headerfile <x86intrin.h>1605///1606/// \code1607/// __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c);1608/// \endcode1609///1610/// This intrinsic corresponds to the <c> VCMPPD </c> instruction.1611///1612/// \param a1613/// A 128-bit vector of [2 x double].1614/// \param b1615/// A 128-bit vector of [2 x double].1616/// \param c1617/// An immediate integer operand, with bits [4:0] specifying which comparison1618/// operation to use: \n1619/// 0x00: Equal (ordered, non-signaling) \n1620/// 0x01: Less-than (ordered, signaling) \n1621/// 0x02: Less-than-or-equal (ordered, signaling) \n1622/// 0x03: Unordered (non-signaling) \n1623/// 0x04: Not-equal (unordered, non-signaling) \n1624/// 0x05: Not-less-than (unordered, signaling) \n1625/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1626/// 0x07: Ordered (non-signaling) \n1627/// 0x08: Equal (unordered, non-signaling) \n1628/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1629/// 0x0A: Not-greater-than (unordered, signaling) \n1630/// 0x0B: False (ordered, non-signaling) \n1631/// 0x0C: Not-equal (ordered, non-signaling) \n1632/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1633/// 0x0E: Greater-than (ordered, signaling) \n1634/// 0x0F: True (unordered, non-signaling) \n1635/// 0x10: Equal (ordered, signaling) \n1636/// 0x11: Less-than (ordered, non-signaling) \n1637/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1638/// 0x13: Unordered (signaling) \n1639/// 0x14: Not-equal (unordered, signaling) \n1640/// 0x15: Not-less-than (unordered, non-signaling) \n1641/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1642/// 0x17: Ordered (signaling) \n1643/// 0x18: Equal (unordered, signaling) \n1644/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1645/// 0x1A: Not-greater-than (unordered, non-signaling) \n1646/// 0x1B: False (ordered, signaling) \n1647/// 0x1C: Not-equal (ordered, signaling) \n1648/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1649/// 0x1E: Greater-than (ordered, non-signaling) \n1650/// 0x1F: True (unordered, signaling)1651/// \returns A 128-bit vector of [2 x double] containing the comparison results.1652/// \fn __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c)1653 1654/* Below intrinsic defined in xmmintrin.h can be used for AVX */1655/// Compares each of the corresponding values of two 128-bit vectors of1656/// [4 x float], using the operation specified by the immediate integer1657/// operand.1658///1659/// Each comparison returns 0x0 for false, 0xFFFFFFFF for true.1660/// If either value in a comparison is NaN, comparisons that are ordered1661/// return false, and comparisons that are unordered return true.1662///1663/// \headerfile <x86intrin.h>1664///1665/// \code1666/// __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c);1667/// \endcode1668///1669/// This intrinsic corresponds to the <c> VCMPPS </c> instruction.1670///1671/// \param a1672/// A 128-bit vector of [4 x float].1673/// \param b1674/// A 128-bit vector of [4 x float].1675/// \param c1676/// An immediate integer operand, with bits [4:0] specifying which comparison1677/// operation to use: \n1678/// 0x00: Equal (ordered, non-signaling) \n1679/// 0x01: Less-than (ordered, signaling) \n1680/// 0x02: Less-than-or-equal (ordered, signaling) \n1681/// 0x03: Unordered (non-signaling) \n1682/// 0x04: Not-equal (unordered, non-signaling) \n1683/// 0x05: Not-less-than (unordered, signaling) \n1684/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1685/// 0x07: Ordered (non-signaling) \n1686/// 0x08: Equal (unordered, non-signaling) \n1687/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1688/// 0x0A: Not-greater-than (unordered, signaling) \n1689/// 0x0B: False (ordered, non-signaling) \n1690/// 0x0C: Not-equal (ordered, non-signaling) \n1691/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1692/// 0x0E: Greater-than (ordered, signaling) \n1693/// 0x0F: True (unordered, non-signaling) \n1694/// 0x10: Equal (ordered, signaling) \n1695/// 0x11: Less-than (ordered, non-signaling) \n1696/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1697/// 0x13: Unordered (signaling) \n1698/// 0x14: Not-equal (unordered, signaling) \n1699/// 0x15: Not-less-than (unordered, non-signaling) \n1700/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1701/// 0x17: Ordered (signaling) \n1702/// 0x18: Equal (unordered, signaling) \n1703/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1704/// 0x1A: Not-greater-than (unordered, non-signaling) \n1705/// 0x1B: False (ordered, signaling) \n1706/// 0x1C: Not-equal (ordered, signaling) \n1707/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1708/// 0x1E: Greater-than (ordered, non-signaling) \n1709/// 0x1F: True (unordered, signaling)1710/// \returns A 128-bit vector of [4 x float] containing the comparison results.1711/// \fn __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c)1712 1713/// Compares each of the corresponding double-precision values of two1714/// 256-bit vectors of [4 x double], using the operation specified by the1715/// immediate integer operand.1716///1717/// Each comparison returns 0x0 for false, 0xFFFFFFFFFFFFFFFF for true.1718/// If either value in a comparison is NaN, comparisons that are ordered1719/// return false, and comparisons that are unordered return true.1720///1721/// \headerfile <x86intrin.h>1722///1723/// \code1724/// __m256d _mm256_cmp_pd(__m256d a, __m256d b, const int c);1725/// \endcode1726///1727/// This intrinsic corresponds to the <c> VCMPPD </c> instruction.1728///1729/// \param a1730/// A 256-bit vector of [4 x double].1731/// \param b1732/// A 256-bit vector of [4 x double].1733/// \param c1734/// An immediate integer operand, with bits [4:0] specifying which comparison1735/// operation to use: \n1736/// 0x00: Equal (ordered, non-signaling) \n1737/// 0x01: Less-than (ordered, signaling) \n1738/// 0x02: Less-than-or-equal (ordered, signaling) \n1739/// 0x03: Unordered (non-signaling) \n1740/// 0x04: Not-equal (unordered, non-signaling) \n1741/// 0x05: Not-less-than (unordered, signaling) \n1742/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1743/// 0x07: Ordered (non-signaling) \n1744/// 0x08: Equal (unordered, non-signaling) \n1745/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1746/// 0x0A: Not-greater-than (unordered, signaling) \n1747/// 0x0B: False (ordered, non-signaling) \n1748/// 0x0C: Not-equal (ordered, non-signaling) \n1749/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1750/// 0x0E: Greater-than (ordered, signaling) \n1751/// 0x0F: True (unordered, non-signaling) \n1752/// 0x10: Equal (ordered, signaling) \n1753/// 0x11: Less-than (ordered, non-signaling) \n1754/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1755/// 0x13: Unordered (signaling) \n1756/// 0x14: Not-equal (unordered, signaling) \n1757/// 0x15: Not-less-than (unordered, non-signaling) \n1758/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1759/// 0x17: Ordered (signaling) \n1760/// 0x18: Equal (unordered, signaling) \n1761/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1762/// 0x1A: Not-greater-than (unordered, non-signaling) \n1763/// 0x1B: False (ordered, signaling) \n1764/// 0x1C: Not-equal (ordered, signaling) \n1765/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1766/// 0x1E: Greater-than (ordered, non-signaling) \n1767/// 0x1F: True (unordered, signaling)1768/// \returns A 256-bit vector of [4 x double] containing the comparison results.1769#define _mm256_cmp_pd(a, b, c) \1770 ((__m256d)__builtin_ia32_cmppd256((__v4df)(__m256d)(a), \1771 (__v4df)(__m256d)(b), (c)))1772 1773/// Compares each of the corresponding values of two 256-bit vectors of1774/// [8 x float], using the operation specified by the immediate integer1775/// operand.1776///1777/// Each comparison returns 0x0 for false, 0xFFFFFFFF for true.1778/// If either value in a comparison is NaN, comparisons that are ordered1779/// return false, and comparisons that are unordered return true.1780///1781/// \headerfile <x86intrin.h>1782///1783/// \code1784/// __m256 _mm256_cmp_ps(__m256 a, __m256 b, const int c);1785/// \endcode1786///1787/// This intrinsic corresponds to the <c> VCMPPS </c> instruction.1788///1789/// \param a1790/// A 256-bit vector of [8 x float].1791/// \param b1792/// A 256-bit vector of [8 x float].1793/// \param c1794/// An immediate integer operand, with bits [4:0] specifying which comparison1795/// operation to use: \n1796/// 0x00: Equal (ordered, non-signaling) \n1797/// 0x01: Less-than (ordered, signaling) \n1798/// 0x02: Less-than-or-equal (ordered, signaling) \n1799/// 0x03: Unordered (non-signaling) \n1800/// 0x04: Not-equal (unordered, non-signaling) \n1801/// 0x05: Not-less-than (unordered, signaling) \n1802/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1803/// 0x07: Ordered (non-signaling) \n1804/// 0x08: Equal (unordered, non-signaling) \n1805/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1806/// 0x0A: Not-greater-than (unordered, signaling) \n1807/// 0x0B: False (ordered, non-signaling) \n1808/// 0x0C: Not-equal (ordered, non-signaling) \n1809/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1810/// 0x0E: Greater-than (ordered, signaling) \n1811/// 0x0F: True (unordered, non-signaling) \n1812/// 0x10: Equal (ordered, signaling) \n1813/// 0x11: Less-than (ordered, non-signaling) \n1814/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1815/// 0x13: Unordered (signaling) \n1816/// 0x14: Not-equal (unordered, signaling) \n1817/// 0x15: Not-less-than (unordered, non-signaling) \n1818/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1819/// 0x17: Ordered (signaling) \n1820/// 0x18: Equal (unordered, signaling) \n1821/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1822/// 0x1A: Not-greater-than (unordered, non-signaling) \n1823/// 0x1B: False (ordered, signaling) \n1824/// 0x1C: Not-equal (ordered, signaling) \n1825/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1826/// 0x1E: Greater-than (ordered, non-signaling) \n1827/// 0x1F: True (unordered, signaling)1828/// \returns A 256-bit vector of [8 x float] containing the comparison results.1829#define _mm256_cmp_ps(a, b, c) \1830 ((__m256)__builtin_ia32_cmpps256((__v8sf)(__m256)(a), \1831 (__v8sf)(__m256)(b), (c)))1832 1833/* Below intrinsic defined in emmintrin.h can be used for AVX */1834/// Compares each of the corresponding scalar double-precision values of1835/// two 128-bit vectors of [2 x double], using the operation specified by the1836/// immediate integer operand.1837///1838/// Each comparison returns 0x0 for false, 0xFFFFFFFFFFFFFFFF for true.1839/// If either value in a comparison is NaN, comparisons that are ordered1840/// return false, and comparisons that are unordered return true.1841///1842/// \headerfile <x86intrin.h>1843///1844/// \code1845/// __m128d _mm_cmp_sd(__m128d a, __m128d b, const int c);1846/// \endcode1847///1848/// This intrinsic corresponds to the <c> VCMPSD </c> instruction.1849///1850/// \param a1851/// A 128-bit vector of [2 x double].1852/// \param b1853/// A 128-bit vector of [2 x double].1854/// \param c1855/// An immediate integer operand, with bits [4:0] specifying which comparison1856/// operation to use: \n1857/// 0x00: Equal (ordered, non-signaling) \n1858/// 0x01: Less-than (ordered, signaling) \n1859/// 0x02: Less-than-or-equal (ordered, signaling) \n1860/// 0x03: Unordered (non-signaling) \n1861/// 0x04: Not-equal (unordered, non-signaling) \n1862/// 0x05: Not-less-than (unordered, signaling) \n1863/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1864/// 0x07: Ordered (non-signaling) \n1865/// 0x08: Equal (unordered, non-signaling) \n1866/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1867/// 0x0A: Not-greater-than (unordered, signaling) \n1868/// 0x0B: False (ordered, non-signaling) \n1869/// 0x0C: Not-equal (ordered, non-signaling) \n1870/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1871/// 0x0E: Greater-than (ordered, signaling) \n1872/// 0x0F: True (unordered, non-signaling) \n1873/// 0x10: Equal (ordered, signaling) \n1874/// 0x11: Less-than (ordered, non-signaling) \n1875/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1876/// 0x13: Unordered (signaling) \n1877/// 0x14: Not-equal (unordered, signaling) \n1878/// 0x15: Not-less-than (unordered, non-signaling) \n1879/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1880/// 0x17: Ordered (signaling) \n1881/// 0x18: Equal (unordered, signaling) \n1882/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1883/// 0x1A: Not-greater-than (unordered, non-signaling) \n1884/// 0x1B: False (ordered, signaling) \n1885/// 0x1C: Not-equal (ordered, signaling) \n1886/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1887/// 0x1E: Greater-than (ordered, non-signaling) \n1888/// 0x1F: True (unordered, signaling)1889/// \returns A 128-bit vector of [2 x double] containing the comparison results.1890/// \fn __m128d _mm_cmp_sd(__m128d a, __m128d b, const int c)1891 1892/* Below intrinsic defined in xmmintrin.h can be used for AVX */1893/// Compares each of the corresponding scalar values of two 128-bit1894/// vectors of [4 x float], using the operation specified by the immediate1895/// integer operand.1896///1897/// Each comparison returns 0x0 for false, 0xFFFFFFFF for true.1898/// If either value in a comparison is NaN, comparisons that are ordered1899/// return false, and comparisons that are unordered return true.1900///1901/// \headerfile <x86intrin.h>1902///1903/// \code1904/// __m128 _mm_cmp_ss(__m128 a, __m128 b, const int c);1905/// \endcode1906///1907/// This intrinsic corresponds to the <c> VCMPSS </c> instruction.1908///1909/// \param a1910/// A 128-bit vector of [4 x float].1911/// \param b1912/// A 128-bit vector of [4 x float].1913/// \param c1914/// An immediate integer operand, with bits [4:0] specifying which comparison1915/// operation to use: \n1916/// 0x00: Equal (ordered, non-signaling) \n1917/// 0x01: Less-than (ordered, signaling) \n1918/// 0x02: Less-than-or-equal (ordered, signaling) \n1919/// 0x03: Unordered (non-signaling) \n1920/// 0x04: Not-equal (unordered, non-signaling) \n1921/// 0x05: Not-less-than (unordered, signaling) \n1922/// 0x06: Not-less-than-or-equal (unordered, signaling) \n1923/// 0x07: Ordered (non-signaling) \n1924/// 0x08: Equal (unordered, non-signaling) \n1925/// 0x09: Not-greater-than-or-equal (unordered, signaling) \n1926/// 0x0A: Not-greater-than (unordered, signaling) \n1927/// 0x0B: False (ordered, non-signaling) \n1928/// 0x0C: Not-equal (ordered, non-signaling) \n1929/// 0x0D: Greater-than-or-equal (ordered, signaling) \n1930/// 0x0E: Greater-than (ordered, signaling) \n1931/// 0x0F: True (unordered, non-signaling) \n1932/// 0x10: Equal (ordered, signaling) \n1933/// 0x11: Less-than (ordered, non-signaling) \n1934/// 0x12: Less-than-or-equal (ordered, non-signaling) \n1935/// 0x13: Unordered (signaling) \n1936/// 0x14: Not-equal (unordered, signaling) \n1937/// 0x15: Not-less-than (unordered, non-signaling) \n1938/// 0x16: Not-less-than-or-equal (unordered, non-signaling) \n1939/// 0x17: Ordered (signaling) \n1940/// 0x18: Equal (unordered, signaling) \n1941/// 0x19: Not-greater-than-or-equal (unordered, non-signaling) \n1942/// 0x1A: Not-greater-than (unordered, non-signaling) \n1943/// 0x1B: False (ordered, signaling) \n1944/// 0x1C: Not-equal (ordered, signaling) \n1945/// 0x1D: Greater-than-or-equal (ordered, non-signaling) \n1946/// 0x1E: Greater-than (ordered, non-signaling) \n1947/// 0x1F: True (unordered, signaling)1948/// \returns A 128-bit vector of [4 x float] containing the comparison results.1949/// \fn __m128 _mm_cmp_ss(__m128 a, __m128 b, const int c)1950 1951/// Takes a [8 x i32] vector and returns the vector element value1952/// indexed by the immediate constant operand.1953///1954/// \headerfile <x86intrin.h>1955///1956/// \code1957/// int _mm256_extract_epi32(__m256i X, const int N);1958/// \endcode1959///1960/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c>1961/// instruction.1962///1963/// \param X1964/// A 256-bit vector of [8 x i32].1965/// \param N1966/// An immediate integer operand with bits [2:0] determining which vector1967/// element is extracted and returned.1968/// \returns A 32-bit integer containing the extracted 32 bits of extended1969/// packed data.1970#define _mm256_extract_epi32(X, N) \1971 ((int)__builtin_ia32_vec_ext_v8si((__v8si)(__m256i)(X), (int)(N)))1972 1973/// Takes a [16 x i16] vector and returns the vector element value1974/// indexed by the immediate constant operand.1975///1976/// \headerfile <x86intrin.h>1977///1978/// \code1979/// int _mm256_extract_epi16(__m256i X, const int N);1980/// \endcode1981///1982/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c>1983/// instruction.1984///1985/// \param X1986/// A 256-bit integer vector of [16 x i16].1987/// \param N1988/// An immediate integer operand with bits [3:0] determining which vector1989/// element is extracted and returned.1990/// \returns A 32-bit integer containing the extracted 16 bits of zero extended1991/// packed data.1992#define _mm256_extract_epi16(X, N) \1993 ((int)(unsigned short)__builtin_ia32_vec_ext_v16hi((__v16hi)(__m256i)(X), \1994 (int)(N)))1995 1996/// Takes a [32 x i8] vector and returns the vector element value1997/// indexed by the immediate constant operand.1998///1999/// \headerfile <x86intrin.h>2000///2001/// \code2002/// int _mm256_extract_epi8(__m256i X, const int N);2003/// \endcode2004///2005/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c>2006/// instruction.2007///2008/// \param X2009/// A 256-bit integer vector of [32 x i8].2010/// \param N2011/// An immediate integer operand with bits [4:0] determining which vector2012/// element is extracted and returned.2013/// \returns A 32-bit integer containing the extracted 8 bits of zero extended2014/// packed data.2015#define _mm256_extract_epi8(X, N) \2016 ((int)(unsigned char)__builtin_ia32_vec_ext_v32qi((__v32qi)(__m256i)(X), \2017 (int)(N)))2018 2019#ifdef __x86_64__2020/// Takes a [4 x i64] vector and returns the vector element value2021/// indexed by the immediate constant operand.2022///2023/// \headerfile <x86intrin.h>2024///2025/// \code2026/// long long _mm256_extract_epi64(__m256i X, const int N);2027/// \endcode2028///2029/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c>2030/// instruction.2031///2032/// \param X2033/// A 256-bit integer vector of [4 x i64].2034/// \param N2035/// An immediate integer operand with bits [1:0] determining which vector2036/// element is extracted and returned.2037/// \returns A 64-bit integer containing the extracted 64 bits of extended2038/// packed data.2039#define _mm256_extract_epi64(X, N) \2040 ((long long)__builtin_ia32_vec_ext_v4di((__v4di)(__m256i)(X), (int)(N)))2041#endif2042 2043/// Takes a [8 x i32] vector and replaces the vector element value2044/// indexed by the immediate constant operand by a new value. Returns the2045/// modified vector.2046///2047/// \headerfile <x86intrin.h>2048///2049/// \code2050/// __m256i _mm256_insert_epi32(__m256i X, int I, const int N);2051/// \endcode2052///2053/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c>2054/// instruction.2055///2056/// \param X2057/// A vector of [8 x i32] to be used by the insert operation.2058/// \param I2059/// An integer value. The replacement value for the insert operation.2060/// \param N2061/// An immediate integer specifying the index of the vector element to be2062/// replaced.2063/// \returns A copy of vector \a X, after replacing its element indexed by2064/// \a N with \a I.2065#define _mm256_insert_epi32(X, I, N) \2066 ((__m256i)__builtin_ia32_vec_set_v8si((__v8si)(__m256i)(X), \2067 (int)(I), (int)(N)))2068 2069 2070/// Takes a [16 x i16] vector and replaces the vector element value2071/// indexed by the immediate constant operand with a new value. Returns the2072/// modified vector.2073///2074/// \headerfile <x86intrin.h>2075///2076/// \code2077/// __m256i _mm256_insert_epi16(__m256i X, int I, const int N);2078/// \endcode2079///2080/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c>2081/// instruction.2082///2083/// \param X2084/// A vector of [16 x i16] to be used by the insert operation.2085/// \param I2086/// An i16 integer value. The replacement value for the insert operation.2087/// \param N2088/// An immediate integer specifying the index of the vector element to be2089/// replaced.2090/// \returns A copy of vector \a X, after replacing its element indexed by2091/// \a N with \a I.2092#define _mm256_insert_epi16(X, I, N) \2093 ((__m256i)__builtin_ia32_vec_set_v16hi((__v16hi)(__m256i)(X), \2094 (int)(I), (int)(N)))2095 2096/// Takes a [32 x i8] vector and replaces the vector element value2097/// indexed by the immediate constant operand with a new value. Returns the2098/// modified vector.2099///2100/// \headerfile <x86intrin.h>2101///2102/// \code2103/// __m256i _mm256_insert_epi8(__m256i X, int I, const int N);2104/// \endcode2105///2106/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c>2107/// instruction.2108///2109/// \param X2110/// A vector of [32 x i8] to be used by the insert operation.2111/// \param I2112/// An i8 integer value. The replacement value for the insert operation.2113/// \param N2114/// An immediate integer specifying the index of the vector element to be2115/// replaced.2116/// \returns A copy of vector \a X, after replacing its element indexed by2117/// \a N with \a I.2118#define _mm256_insert_epi8(X, I, N) \2119 ((__m256i)__builtin_ia32_vec_set_v32qi((__v32qi)(__m256i)(X), \2120 (int)(I), (int)(N)))2121 2122#ifdef __x86_64__2123/// Takes a [4 x i64] vector and replaces the vector element value2124/// indexed by the immediate constant operand with a new value. Returns the2125/// modified vector.2126///2127/// \headerfile <x86intrin.h>2128///2129/// \code2130/// __m256i _mm256_insert_epi64(__m256i X, int I, const int N);2131/// \endcode2132///2133/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c>2134/// instruction.2135///2136/// \param X2137/// A vector of [4 x i64] to be used by the insert operation.2138/// \param I2139/// A 64-bit integer value. The replacement value for the insert operation.2140/// \param N2141/// An immediate integer specifying the index of the vector element to be2142/// replaced.2143/// \returns A copy of vector \a X, after replacing its element indexed by2144/// \a N with \a I.2145#define _mm256_insert_epi64(X, I, N) \2146 ((__m256i)__builtin_ia32_vec_set_v4di((__v4di)(__m256i)(X), \2147 (long long)(I), (int)(N)))2148#endif2149 2150/* Conversion */2151/// Converts a vector of [4 x i32] into a vector of [4 x double].2152///2153/// \headerfile <x86intrin.h>2154///2155/// This intrinsic corresponds to the <c> VCVTDQ2PD </c> instruction.2156///2157/// \param __a2158/// A 128-bit integer vector of [4 x i32].2159/// \returns A 256-bit vector of [4 x double] containing the converted values.2160static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR2161_mm256_cvtepi32_pd(__m128i __a) {2162 return (__m256d)__builtin_convertvector((__v4si)__a, __v4df);2163}2164 2165/// Converts a vector of [8 x i32] into a vector of [8 x float].2166///2167/// \headerfile <x86intrin.h>2168///2169/// This intrinsic corresponds to the <c> VCVTDQ2PS </c> instruction.2170///2171/// \param __a2172/// A 256-bit integer vector.2173/// \returns A 256-bit vector of [8 x float] containing the converted values.2174static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR2175_mm256_cvtepi32_ps(__m256i __a) {2176 return (__m256)__builtin_convertvector((__v8si)__a, __v8sf);2177}2178 2179/// Converts a 256-bit vector of [4 x double] into a 128-bit vector of2180/// [4 x float].2181///2182/// \headerfile <x86intrin.h>2183///2184/// This intrinsic corresponds to the <c> VCVTPD2PS </c> instruction.2185///2186/// \param __a2187/// A 256-bit vector of [4 x double].2188/// \returns A 128-bit vector of [4 x float] containing the converted values.2189static __inline __m128 __DEFAULT_FN_ATTRS2190_mm256_cvtpd_ps(__m256d __a)2191{2192 return (__m128)__builtin_ia32_cvtpd2ps256((__v4df) __a);2193}2194 2195/// Converts a vector of [8 x float] into a vector of [8 x i32].2196///2197/// If a converted value does not fit in a 32-bit integer, raises a2198/// floating-point invalid exception. If the exception is masked, returns2199/// the most negative integer.2200///2201/// \headerfile <x86intrin.h>2202///2203/// This intrinsic corresponds to the <c> VCVTPS2DQ </c> instruction.2204///2205/// \param __a2206/// A 256-bit vector of [8 x float].2207/// \returns A 256-bit integer vector containing the converted values.2208static __inline __m256i __DEFAULT_FN_ATTRS2209_mm256_cvtps_epi32(__m256 __a)2210{2211 return (__m256i)__builtin_ia32_cvtps2dq256((__v8sf) __a);2212}2213 2214/// Converts a 128-bit vector of [4 x float] into a 256-bit vector of [42215/// x double].2216///2217/// \headerfile <x86intrin.h>2218///2219/// This intrinsic corresponds to the <c> VCVTPS2PD </c> instruction.2220///2221/// \param __a2222/// A 128-bit vector of [4 x float].2223/// \returns A 256-bit vector of [4 x double] containing the converted values.2224static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR2225_mm256_cvtps_pd(__m128 __a) {2226 return (__m256d)__builtin_convertvector((__v4sf)__a, __v4df);2227}2228 2229/// Converts a 256-bit vector of [4 x double] into four signed truncated2230/// (rounded toward zero) 32-bit integers returned in a 128-bit vector of2231/// [4 x i32].2232///2233/// If a converted value does not fit in a 32-bit integer, raises a2234/// floating-point invalid exception. If the exception is masked, returns2235/// the most negative integer.2236///2237/// \headerfile <x86intrin.h>2238///2239/// This intrinsic corresponds to the <c> VCVTTPD2DQ </c> instruction.2240///2241/// \param __a2242/// A 256-bit vector of [4 x double].2243/// \returns A 128-bit integer vector containing the converted values.2244static __inline __m128i __DEFAULT_FN_ATTRS2245_mm256_cvttpd_epi32(__m256d __a)2246{2247 return (__m128i)__builtin_ia32_cvttpd2dq256((__v4df) __a);2248}2249 2250/// Converts a 256-bit vector of [4 x double] into a 128-bit vector of2251/// [4 x i32].2252///2253/// If a converted value does not fit in a 32-bit integer, raises a2254/// floating-point invalid exception. If the exception is masked, returns2255/// the most negative integer.2256///2257/// \headerfile <x86intrin.h>2258///2259/// This intrinsic corresponds to the <c> VCVTPD2DQ </c> instruction.2260///2261/// \param __a2262/// A 256-bit vector of [4 x double].2263/// \returns A 128-bit integer vector containing the converted values.2264static __inline __m128i __DEFAULT_FN_ATTRS2265_mm256_cvtpd_epi32(__m256d __a)2266{2267 return (__m128i)__builtin_ia32_cvtpd2dq256((__v4df) __a);2268}2269 2270/// Converts a vector of [8 x float] into eight signed truncated (rounded2271/// toward zero) 32-bit integers returned in a vector of [8 x i32].2272///2273/// If a converted value does not fit in a 32-bit integer, raises a2274/// floating-point invalid exception. If the exception is masked, returns2275/// the most negative integer.2276///2277/// \headerfile <x86intrin.h>2278///2279/// This intrinsic corresponds to the <c> VCVTTPS2DQ </c> instruction.2280///2281/// \param __a2282/// A 256-bit vector of [8 x float].2283/// \returns A 256-bit integer vector containing the converted values.2284static __inline __m256i __DEFAULT_FN_ATTRS2285_mm256_cvttps_epi32(__m256 __a)2286{2287 return (__m256i)__builtin_ia32_cvttps2dq256((__v8sf) __a);2288}2289 2290/// Returns the first element of the input vector of [4 x double].2291///2292/// \headerfile <x86intrin.h>2293///2294/// This intrinsic is a utility function and does not correspond to a specific2295/// instruction.2296///2297/// \param __a2298/// A 256-bit vector of [4 x double].2299/// \returns A 64 bit double containing the first element of the input vector.2300static __inline double __DEFAULT_FN_ATTRS_CONSTEXPR2301_mm256_cvtsd_f64(__m256d __a) {2302 return __a[0];2303}2304 2305/// Returns the first element of the input vector of [8 x i32].2306///2307/// \headerfile <x86intrin.h>2308///2309/// This intrinsic is a utility function and does not correspond to a specific2310/// instruction.2311///2312/// \param __a2313/// A 256-bit vector of [8 x i32].2314/// \returns A 32 bit integer containing the first element of the input vector.2315static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2316_mm256_cvtsi256_si32(__m256i __a) {2317 __v8si __b = (__v8si)__a;2318 return __b[0];2319}2320 2321/// Returns the first element of the input vector of [8 x float].2322///2323/// \headerfile <x86intrin.h>2324///2325/// This intrinsic is a utility function and does not correspond to a specific2326/// instruction.2327///2328/// \param __a2329/// A 256-bit vector of [8 x float].2330/// \returns A 32 bit float containing the first element of the input vector.2331static __inline float __DEFAULT_FN_ATTRS_CONSTEXPR2332_mm256_cvtss_f32(__m256 __a) {2333 return __a[0];2334}2335 2336/* Vector replicate */2337/// Moves and duplicates odd-indexed values from a 256-bit vector of2338/// [8 x float] to float values in a 256-bit vector of [8 x float].2339///2340/// \headerfile <x86intrin.h>2341///2342/// This intrinsic corresponds to the <c> VMOVSHDUP </c> instruction.2343///2344/// \param __a2345/// A 256-bit vector of [8 x float]. \n2346/// Bits [255:224] of \a __a are written to bits [255:224] and [223:192] of2347/// the return value. \n2348/// Bits [191:160] of \a __a are written to bits [191:160] and [159:128] of2349/// the return value. \n2350/// Bits [127:96] of \a __a are written to bits [127:96] and [95:64] of the2351/// return value. \n2352/// Bits [63:32] of \a __a are written to bits [63:32] and [31:0] of the2353/// return value.2354/// \returns A 256-bit vector of [8 x float] containing the moved and duplicated2355/// values.2356static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR2357_mm256_movehdup_ps(__m256 __a)2358{2359 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 1, 1, 3, 3, 5, 5, 7, 7);2360}2361 2362/// Moves and duplicates even-indexed values from a 256-bit vector of2363/// [8 x float] to float values in a 256-bit vector of [8 x float].2364///2365/// \headerfile <x86intrin.h>2366///2367/// This intrinsic corresponds to the <c> VMOVSLDUP </c> instruction.2368///2369/// \param __a2370/// A 256-bit vector of [8 x float]. \n2371/// Bits [223:192] of \a __a are written to bits [255:224] and [223:192] of2372/// the return value. \n2373/// Bits [159:128] of \a __a are written to bits [191:160] and [159:128] of2374/// the return value. \n2375/// Bits [95:64] of \a __a are written to bits [127:96] and [95:64] of the2376/// return value. \n2377/// Bits [31:0] of \a __a are written to bits [63:32] and [31:0] of the2378/// return value.2379/// \returns A 256-bit vector of [8 x float] containing the moved and duplicated2380/// values.2381static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR2382_mm256_moveldup_ps(__m256 __a)2383{2384 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 0, 2, 2, 4, 4, 6, 6);2385}2386 2387/// Moves and duplicates double-precision floating point values from a2388/// 256-bit vector of [4 x double] to double-precision values in a 256-bit2389/// vector of [4 x double].2390///2391/// \headerfile <x86intrin.h>2392///2393/// This intrinsic corresponds to the <c> VMOVDDUP </c> instruction.2394///2395/// \param __a2396/// A 256-bit vector of [4 x double]. \n2397/// Bits [63:0] of \a __a are written to bits [127:64] and [63:0] of the2398/// return value. \n2399/// Bits [191:128] of \a __a are written to bits [255:192] and [191:128] of2400/// the return value.2401/// \returns A 256-bit vector of [4 x double] containing the moved and2402/// duplicated values.2403static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR2404_mm256_movedup_pd(__m256d __a)2405{2406 return __builtin_shufflevector((__v4df)__a, (__v4df)__a, 0, 0, 2, 2);2407}2408 2409/* Unpack and Interleave */2410/// Unpacks the odd-indexed vector elements from two 256-bit vectors of2411/// [4 x double] and interleaves them into a 256-bit vector of [4 x double].2412///2413/// \headerfile <x86intrin.h>2414///2415/// This intrinsic corresponds to the <c> VUNPCKHPD </c> instruction.2416///2417/// \param __a2418/// A 256-bit floating-point vector of [4 x double]. \n2419/// Bits [127:64] are written to bits [63:0] of the return value. \n2420/// Bits [255:192] are written to bits [191:128] of the return value. \n2421/// \param __b2422/// A 256-bit floating-point vector of [4 x double]. \n2423/// Bits [127:64] are written to bits [127:64] of the return value. \n2424/// Bits [255:192] are written to bits [255:192] of the return value. \n2425/// \returns A 256-bit vector of [4 x double] containing the interleaved values.2426static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR2427_mm256_unpackhi_pd(__m256d __a, __m256d __b) {2428 return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 1, 5, 1+2, 5+2);2429}2430 2431/// Unpacks the even-indexed vector elements from two 256-bit vectors of2432/// [4 x double] and interleaves them into a 256-bit vector of [4 x double].2433///2434/// \headerfile <x86intrin.h>2435///2436/// This intrinsic corresponds to the <c> VUNPCKLPD </c> instruction.2437///2438/// \param __a2439/// A 256-bit floating-point vector of [4 x double]. \n2440/// Bits [63:0] are written to bits [63:0] of the return value. \n2441/// Bits [191:128] are written to bits [191:128] of the return value.2442/// \param __b2443/// A 256-bit floating-point vector of [4 x double]. \n2444/// Bits [63:0] are written to bits [127:64] of the return value. \n2445/// Bits [191:128] are written to bits [255:192] of the return value. \n2446/// \returns A 256-bit vector of [4 x double] containing the interleaved values.2447static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR2448_mm256_unpacklo_pd(__m256d __a, __m256d __b) {2449 return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 0, 4, 0+2, 4+2);2450}2451 2452/// Unpacks the 32-bit vector elements 2, 3, 6 and 7 from each of the2453/// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit2454/// vector of [8 x float].2455///2456/// \headerfile <x86intrin.h>2457///2458/// This intrinsic corresponds to the <c> VUNPCKHPS </c> instruction.2459///2460/// \param __a2461/// A 256-bit vector of [8 x float]. \n2462/// Bits [95:64] are written to bits [31:0] of the return value. \n2463/// Bits [127:96] are written to bits [95:64] of the return value. \n2464/// Bits [223:192] are written to bits [159:128] of the return value. \n2465/// Bits [255:224] are written to bits [223:192] of the return value.2466/// \param __b2467/// A 256-bit vector of [8 x float]. \n2468/// Bits [95:64] are written to bits [63:32] of the return value. \n2469/// Bits [127:96] are written to bits [127:96] of the return value. \n2470/// Bits [223:192] are written to bits [191:160] of the return value. \n2471/// Bits [255:224] are written to bits [255:224] of the return value.2472/// \returns A 256-bit vector of [8 x float] containing the interleaved values.2473static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR2474_mm256_unpackhi_ps(__m256 __a, __m256 __b) {2475 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__b, 2, 10, 2+1, 10+1, 6, 14, 6+1, 14+1);2476}2477 2478/// Unpacks the 32-bit vector elements 0, 1, 4 and 5 from each of the2479/// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit2480/// vector of [8 x float].2481///2482/// \headerfile <x86intrin.h>2483///2484/// This intrinsic corresponds to the <c> VUNPCKLPS </c> instruction.2485///2486/// \param __a2487/// A 256-bit vector of [8 x float]. \n2488/// Bits [31:0] are written to bits [31:0] of the return value. \n2489/// Bits [63:32] are written to bits [95:64] of the return value. \n2490/// Bits [159:128] are written to bits [159:128] of the return value. \n2491/// Bits [191:160] are written to bits [223:192] of the return value.2492/// \param __b2493/// A 256-bit vector of [8 x float]. \n2494/// Bits [31:0] are written to bits [63:32] of the return value. \n2495/// Bits [63:32] are written to bits [127:96] of the return value. \n2496/// Bits [159:128] are written to bits [191:160] of the return value. \n2497/// Bits [191:160] are written to bits [255:224] of the return value.2498/// \returns A 256-bit vector of [8 x float] containing the interleaved values.2499static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR2500_mm256_unpacklo_ps(__m256 __a, __m256 __b) {2501 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__b, 0, 8, 0+1, 8+1, 4, 12, 4+1, 12+1);2502}2503 2504/* Bit Test */2505/// Given two 128-bit floating-point vectors of [2 x double], perform an2506/// element-by-element comparison of the double-precision element in the2507/// first source vector and the corresponding element in the second source2508/// vector.2509///2510/// The EFLAGS register is updated as follows: \n2511/// If there is at least one pair of double-precision elements where the2512/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2513/// ZF flag is set to 1. \n2514/// If there is at least one pair of double-precision elements where the2515/// sign-bit of the first element is 0 and the sign-bit of the second element2516/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2517/// This intrinsic returns the value of the ZF flag.2518///2519/// \headerfile <x86intrin.h>2520///2521/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2522///2523/// \param __a2524/// A 128-bit vector of [2 x double].2525/// \param __b2526/// A 128-bit vector of [2 x double].2527/// \returns the ZF flag in the EFLAGS register.2528static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_testz_pd(__m128d __a,2529 __m128d __b) {2530 return __builtin_ia32_vtestzpd((__v2df)__a, (__v2df)__b);2531}2532 2533/// Given two 128-bit floating-point vectors of [2 x double], perform an2534/// element-by-element comparison of the double-precision element in the2535/// first source vector and the corresponding element in the second source2536/// vector.2537///2538/// The EFLAGS register is updated as follows: \n2539/// If there is at least one pair of double-precision elements where the2540/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2541/// ZF flag is set to 1. \n2542/// If there is at least one pair of double-precision elements where the2543/// sign-bit of the first element is 0 and the sign-bit of the second element2544/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2545/// This intrinsic returns the value of the CF flag.2546///2547/// \headerfile <x86intrin.h>2548///2549/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2550///2551/// \param __a2552/// A 128-bit vector of [2 x double].2553/// \param __b2554/// A 128-bit vector of [2 x double].2555/// \returns the CF flag in the EFLAGS register.2556static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_testc_pd(__m128d __a,2557 __m128d __b) {2558 return __builtin_ia32_vtestcpd((__v2df)__a, (__v2df)__b);2559}2560 2561/// Given two 128-bit floating-point vectors of [2 x double], perform an2562/// element-by-element comparison of the double-precision element in the2563/// first source vector and the corresponding element in the second source2564/// vector.2565///2566/// The EFLAGS register is updated as follows: \n2567/// If there is at least one pair of double-precision elements where the2568/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2569/// ZF flag is set to 1. \n2570/// If there is at least one pair of double-precision elements where the2571/// sign-bit of the first element is 0 and the sign-bit of the second element2572/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2573/// This intrinsic returns 1 if both the ZF and CF flags are set to 0,2574/// otherwise it returns 0.2575///2576/// \headerfile <x86intrin.h>2577///2578/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2579///2580/// \param __a2581/// A 128-bit vector of [2 x double].2582/// \param __b2583/// A 128-bit vector of [2 x double].2584/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0.2585static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR2586_mm_testnzc_pd(__m128d __a, __m128d __b) {2587 return __builtin_ia32_vtestnzcpd((__v2df)__a, (__v2df)__b);2588}2589 2590/// Given two 128-bit floating-point vectors of [4 x float], perform an2591/// element-by-element comparison of the single-precision element in the2592/// first source vector and the corresponding element in the second source2593/// vector.2594///2595/// The EFLAGS register is updated as follows: \n2596/// If there is at least one pair of single-precision elements where the2597/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2598/// ZF flag is set to 1. \n2599/// If there is at least one pair of single-precision elements where the2600/// sign-bit of the first element is 0 and the sign-bit of the second element2601/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2602/// This intrinsic returns the value of the ZF flag.2603///2604/// \headerfile <x86intrin.h>2605///2606/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2607///2608/// \param __a2609/// A 128-bit vector of [4 x float].2610/// \param __b2611/// A 128-bit vector of [4 x float].2612/// \returns the ZF flag.2613static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_testz_ps(__m128 __a,2614 __m128 __b) {2615 return __builtin_ia32_vtestzps((__v4sf)__a, (__v4sf)__b);2616}2617 2618/// Given two 128-bit floating-point vectors of [4 x float], perform an2619/// element-by-element comparison of the single-precision element in the2620/// first source vector and the corresponding element in the second source2621/// vector.2622///2623/// The EFLAGS register is updated as follows: \n2624/// If there is at least one pair of single-precision elements where the2625/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2626/// ZF flag is set to 1. \n2627/// If there is at least one pair of single-precision elements where the2628/// sign-bit of the first element is 0 and the sign-bit of the second element2629/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2630/// This intrinsic returns the value of the CF flag.2631///2632/// \headerfile <x86intrin.h>2633///2634/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2635///2636/// \param __a2637/// A 128-bit vector of [4 x float].2638/// \param __b2639/// A 128-bit vector of [4 x float].2640/// \returns the CF flag.2641static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_testc_ps(__m128 __a,2642 __m128 __b) {2643 return __builtin_ia32_vtestcps((__v4sf)__a, (__v4sf)__b);2644}2645 2646/// Given two 128-bit floating-point vectors of [4 x float], perform an2647/// element-by-element comparison of the single-precision element in the2648/// first source vector and the corresponding element in the second source2649/// vector.2650///2651/// The EFLAGS register is updated as follows: \n2652/// If there is at least one pair of single-precision elements where the2653/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2654/// ZF flag is set to 1. \n2655/// If there is at least one pair of single-precision elements where the2656/// sign-bit of the first element is 0 and the sign-bit of the second element2657/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2658/// This intrinsic returns 1 if both the ZF and CF flags are set to 0,2659/// otherwise it returns 0.2660///2661/// \headerfile <x86intrin.h>2662///2663/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2664///2665/// \param __a2666/// A 128-bit vector of [4 x float].2667/// \param __b2668/// A 128-bit vector of [4 x float].2669/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0.2670static __inline int __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_testnzc_ps(__m128 __a,2671 __m128 __b) {2672 return __builtin_ia32_vtestnzcps((__v4sf)__a, (__v4sf)__b);2673}2674 2675/// Given two 256-bit floating-point vectors of [4 x double], perform an2676/// element-by-element comparison of the double-precision elements in the2677/// first source vector and the corresponding elements in the second source2678/// vector.2679///2680/// The EFLAGS register is updated as follows: \n2681/// If there is at least one pair of double-precision elements where the2682/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2683/// ZF flag is set to 1. \n2684/// If there is at least one pair of double-precision elements where the2685/// sign-bit of the first element is 0 and the sign-bit of the second element2686/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2687/// This intrinsic returns the value of the ZF flag.2688///2689/// \headerfile <x86intrin.h>2690///2691/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2692///2693/// \param __a2694/// A 256-bit vector of [4 x double].2695/// \param __b2696/// A 256-bit vector of [4 x double].2697/// \returns the ZF flag.2698static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_testz_pd(__m256d __a,2699 __m256d __b) {2700 return __builtin_ia32_vtestzpd256((__v4df)__a, (__v4df)__b);2701}2702 2703/// Given two 256-bit floating-point vectors of [4 x double], perform an2704/// element-by-element comparison of the double-precision elements in the2705/// first source vector and the corresponding elements in the second source2706/// vector.2707///2708/// The EFLAGS register is updated as follows: \n2709/// If there is at least one pair of double-precision elements where the2710/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2711/// ZF flag is set to 1. \n2712/// If there is at least one pair of double-precision elements where the2713/// sign-bit of the first element is 0 and the sign-bit of the second element2714/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2715/// This intrinsic returns the value of the CF flag.2716///2717/// \headerfile <x86intrin.h>2718///2719/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2720///2721/// \param __a2722/// A 256-bit vector of [4 x double].2723/// \param __b2724/// A 256-bit vector of [4 x double].2725/// \returns the CF flag.2726static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_testc_pd(__m256d __a,2727 __m256d __b) {2728 return __builtin_ia32_vtestcpd256((__v4df)__a, (__v4df)__b);2729}2730 2731/// Given two 256-bit floating-point vectors of [4 x double], perform an2732/// element-by-element comparison of the double-precision elements in the2733/// first source vector and the corresponding elements in the second source2734/// vector.2735///2736/// The EFLAGS register is updated as follows: \n2737/// If there is at least one pair of double-precision elements where the2738/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2739/// ZF flag is set to 1. \n2740/// If there is at least one pair of double-precision elements where the2741/// sign-bit of the first element is 0 and the sign-bit of the second element2742/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2743/// This intrinsic returns 1 if both the ZF and CF flags are set to 0,2744/// otherwise it returns 0.2745///2746/// \headerfile <x86intrin.h>2747///2748/// This intrinsic corresponds to the <c> VTESTPD </c> instruction.2749///2750/// \param __a2751/// A 256-bit vector of [4 x double].2752/// \param __b2753/// A 256-bit vector of [4 x double].2754/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0.2755static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2756_mm256_testnzc_pd(__m256d __a, __m256d __b) {2757 return __builtin_ia32_vtestnzcpd256((__v4df)__a, (__v4df)__b);2758}2759 2760/// Given two 256-bit floating-point vectors of [8 x float], perform an2761/// element-by-element comparison of the single-precision element in the2762/// first source vector and the corresponding element in the second source2763/// vector.2764///2765/// The EFLAGS register is updated as follows: \n2766/// If there is at least one pair of single-precision elements where the2767/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2768/// ZF flag is set to 1. \n2769/// If there is at least one pair of single-precision elements where the2770/// sign-bit of the first element is 0 and the sign-bit of the second element2771/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2772/// This intrinsic returns the value of the ZF flag.2773///2774/// \headerfile <x86intrin.h>2775///2776/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2777///2778/// \param __a2779/// A 256-bit vector of [8 x float].2780/// \param __b2781/// A 256-bit vector of [8 x float].2782/// \returns the ZF flag.2783static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_testz_ps(__m256 __a,2784 __m256 __b) {2785 return __builtin_ia32_vtestzps256((__v8sf)__a, (__v8sf)__b);2786}2787 2788/// Given two 256-bit floating-point vectors of [8 x float], perform an2789/// element-by-element comparison of the single-precision element in the2790/// first source vector and the corresponding element in the second source2791/// vector.2792///2793/// The EFLAGS register is updated as follows: \n2794/// If there is at least one pair of single-precision elements where the2795/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2796/// ZF flag is set to 1. \n2797/// If there is at least one pair of single-precision elements where the2798/// sign-bit of the first element is 0 and the sign-bit of the second element2799/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2800/// This intrinsic returns the value of the CF flag.2801///2802/// \headerfile <x86intrin.h>2803///2804/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2805///2806/// \param __a2807/// A 256-bit vector of [8 x float].2808/// \param __b2809/// A 256-bit vector of [8 x float].2810/// \returns the CF flag.2811static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_testc_ps(__m256 __a,2812 __m256 __b) {2813 return __builtin_ia32_vtestcps256((__v8sf)__a, (__v8sf)__b);2814}2815 2816/// Given two 256-bit floating-point vectors of [8 x float], perform an2817/// element-by-element comparison of the single-precision elements in the2818/// first source vector and the corresponding elements in the second source2819/// vector.2820///2821/// The EFLAGS register is updated as follows: \n2822/// If there is at least one pair of single-precision elements where the2823/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the2824/// ZF flag is set to 1. \n2825/// If there is at least one pair of single-precision elements where the2826/// sign-bit of the first element is 0 and the sign-bit of the second element2827/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n2828/// This intrinsic returns 1 if both the ZF and CF flags are set to 0,2829/// otherwise it returns 0.2830///2831/// \headerfile <x86intrin.h>2832///2833/// This intrinsic corresponds to the <c> VTESTPS </c> instruction.2834///2835/// \param __a2836/// A 256-bit vector of [8 x float].2837/// \param __b2838/// A 256-bit vector of [8 x float].2839/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0.2840static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_testnzc_ps(__m256 __a,2841 __m256 __b) {2842 return __builtin_ia32_vtestnzcps256((__v8sf)__a, (__v8sf)__b);2843}2844 2845/// Given two 256-bit integer vectors, perform a bit-by-bit comparison2846/// of the two source vectors.2847///2848/// The EFLAGS register is updated as follows: \n2849/// If there is at least one pair of bits where both bits are 1, the ZF flag2850/// is set to 0. Otherwise the ZF flag is set to 1. \n2851/// If there is at least one pair of bits where the bit from the first source2852/// vector is 0 and the bit from the second source vector is 1, the CF flag2853/// is set to 0. Otherwise the CF flag is set to 1. \n2854/// This intrinsic returns the value of the ZF flag.2855///2856/// \headerfile <x86intrin.h>2857///2858/// This intrinsic corresponds to the <c> VPTEST </c> instruction.2859///2860/// \param __a2861/// A 256-bit integer vector.2862/// \param __b2863/// A 256-bit integer vector.2864/// \returns the ZF flag.2865static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2866_mm256_testz_si256(__m256i __a, __m256i __b) {2867 return __builtin_ia32_ptestz256((__v4di)__a, (__v4di)__b);2868}2869 2870/// Given two 256-bit integer vectors, perform a bit-by-bit comparison2871/// of the two source vectors.2872///2873/// The EFLAGS register is updated as follows: \n2874/// If there is at least one pair of bits where both bits are 1, the ZF flag2875/// is set to 0. Otherwise the ZF flag is set to 1. \n2876/// If there is at least one pair of bits where the bit from the first source2877/// vector is 0 and the bit from the second source vector is 1, the CF flag2878/// is set to 0. Otherwise the CF flag is set to 1. \n2879/// This intrinsic returns the value of the CF flag.2880///2881/// \headerfile <x86intrin.h>2882///2883/// This intrinsic corresponds to the <c> VPTEST </c> instruction.2884///2885/// \param __a2886/// A 256-bit integer vector.2887/// \param __b2888/// A 256-bit integer vector.2889/// \returns the CF flag.2890static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2891_mm256_testc_si256(__m256i __a, __m256i __b) {2892 return __builtin_ia32_ptestc256((__v4di)__a, (__v4di)__b);2893}2894 2895/// Given two 256-bit integer vectors, perform a bit-by-bit comparison2896/// of the two source vectors.2897///2898/// The EFLAGS register is updated as follows: \n2899/// If there is at least one pair of bits where both bits are 1, the ZF flag2900/// is set to 0. Otherwise the ZF flag is set to 1. \n2901/// If there is at least one pair of bits where the bit from the first source2902/// vector is 0 and the bit from the second source vector is 1, the CF flag2903/// is set to 0. Otherwise the CF flag is set to 1. \n2904/// This intrinsic returns 1 if both the ZF and CF flags are set to 0,2905/// otherwise it returns 0.2906///2907/// \headerfile <x86intrin.h>2908///2909/// This intrinsic corresponds to the <c> VPTEST </c> instruction.2910///2911/// \param __a2912/// A 256-bit integer vector.2913/// \param __b2914/// A 256-bit integer vector.2915/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0.2916static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2917_mm256_testnzc_si256(__m256i __a, __m256i __b) {2918 return __builtin_ia32_ptestnzc256((__v4di)__a, (__v4di)__b);2919}2920 2921/* Vector extract sign mask */2922/// Extracts the sign bits of double-precision floating point elements2923/// in a 256-bit vector of [4 x double] and writes them to the lower order2924/// bits of the return value.2925///2926/// \headerfile <x86intrin.h>2927///2928/// This intrinsic corresponds to the <c> VMOVMSKPD </c> instruction.2929///2930/// \param __a2931/// A 256-bit vector of [4 x double] containing the double-precision2932/// floating point values with sign bits to be extracted.2933/// \returns The sign bits from the operand, written to bits [3:0].2934static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2935_mm256_movemask_pd(__m256d __a) {2936 return __builtin_ia32_movmskpd256((__v4df)__a);2937}2938 2939/// Extracts the sign bits of single-precision floating point elements2940/// in a 256-bit vector of [8 x float] and writes them to the lower order2941/// bits of the return value.2942///2943/// \headerfile <x86intrin.h>2944///2945/// This intrinsic corresponds to the <c> VMOVMSKPS </c> instruction.2946///2947/// \param __a2948/// A 256-bit vector of [8 x float] containing the single-precision floating2949/// point values with sign bits to be extracted.2950/// \returns The sign bits from the operand, written to bits [7:0].2951static __inline int __DEFAULT_FN_ATTRS_CONSTEXPR2952_mm256_movemask_ps(__m256 __a) {2953 return __builtin_ia32_movmskps256((__v8sf)__a);2954}2955 2956/* Vector __zero */2957/// Zeroes the contents of all XMM or YMM registers.2958///2959/// \headerfile <x86intrin.h>2960///2961/// This intrinsic corresponds to the <c> VZEROALL </c> instruction.2962static __inline void __attribute__((__always_inline__, __nodebug__, __target__("avx")))2963_mm256_zeroall(void)2964{2965 __builtin_ia32_vzeroall();2966}2967 2968/// Zeroes the upper 128 bits (bits 255:128) of all YMM registers.2969///2970/// \headerfile <x86intrin.h>2971///2972/// This intrinsic corresponds to the <c> VZEROUPPER </c> instruction.2973static __inline void __attribute__((__always_inline__, __nodebug__, __target__("avx")))2974_mm256_zeroupper(void)2975{2976 __builtin_ia32_vzeroupper();2977}2978 2979/* Vector load with broadcast */2980/// Loads a scalar single-precision floating point value from the2981/// specified address pointed to by \a __a and broadcasts it to the elements2982/// of a [4 x float] vector.2983///2984/// \headerfile <x86intrin.h>2985///2986/// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction.2987///2988/// \param __a2989/// The single-precision floating point value to be broadcast.2990/// \returns A 128-bit vector of [4 x float] whose 32-bit elements are set2991/// equal to the broadcast value.2992static __inline __m128 __DEFAULT_FN_ATTRS1282993_mm_broadcast_ss(float const *__a)2994{2995 struct __mm_broadcast_ss_struct {2996 float __f;2997 } __attribute__((__packed__, __may_alias__));2998 float __f = ((const struct __mm_broadcast_ss_struct*)__a)->__f;2999 return __extension__ (__m128){ __f, __f, __f, __f };3000}3001 3002/// Loads a scalar double-precision floating point value from the3003/// specified address pointed to by \a __a and broadcasts it to the elements3004/// of a [4 x double] vector.3005///3006/// \headerfile <x86intrin.h>3007///3008/// This intrinsic corresponds to the <c> VBROADCASTSD </c> instruction.3009///3010/// \param __a3011/// The double-precision floating point value to be broadcast.3012/// \returns A 256-bit vector of [4 x double] whose 64-bit elements are set3013/// equal to the broadcast value.3014static __inline __m256d __DEFAULT_FN_ATTRS3015_mm256_broadcast_sd(double const *__a)3016{3017 struct __mm256_broadcast_sd_struct {3018 double __d;3019 } __attribute__((__packed__, __may_alias__));3020 double __d = ((const struct __mm256_broadcast_sd_struct*)__a)->__d;3021 return __extension__ (__m256d)(__v4df){ __d, __d, __d, __d };3022}3023 3024/// Loads a scalar single-precision floating point value from the3025/// specified address pointed to by \a __a and broadcasts it to the elements3026/// of a [8 x float] vector.3027///3028/// \headerfile <x86intrin.h>3029///3030/// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction.3031///3032/// \param __a3033/// The single-precision floating point value to be broadcast.3034/// \returns A 256-bit vector of [8 x float] whose 32-bit elements are set3035/// equal to the broadcast value.3036static __inline __m256 __DEFAULT_FN_ATTRS3037_mm256_broadcast_ss(float const *__a)3038{3039 struct __mm256_broadcast_ss_struct {3040 float __f;3041 } __attribute__((__packed__, __may_alias__));3042 float __f = ((const struct __mm256_broadcast_ss_struct*)__a)->__f;3043 return __extension__ (__m256)(__v8sf){ __f, __f, __f, __f, __f, __f, __f, __f };3044}3045 3046/// Loads the data from a 128-bit vector of [2 x double] from the3047/// specified address pointed to by \a __a and broadcasts it to 128-bit3048/// elements in a 256-bit vector of [4 x double].3049///3050/// \headerfile <x86intrin.h>3051///3052/// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction.3053///3054/// \param __a3055/// The 128-bit vector of [2 x double] to be broadcast.3056/// \returns A 256-bit vector of [4 x double] whose 128-bit elements are set3057/// equal to the broadcast value.3058static __inline __m256d __DEFAULT_FN_ATTRS3059_mm256_broadcast_pd(__m128d const *__a)3060{3061 __m128d __b = _mm_loadu_pd((const double *)__a);3062 return (__m256d)__builtin_shufflevector((__v2df)__b, (__v2df)__b,3063 0, 1, 0, 1);3064}3065 3066/// Loads the data from a 128-bit vector of [4 x float] from the3067/// specified address pointed to by \a __a and broadcasts it to 128-bit3068/// elements in a 256-bit vector of [8 x float].3069///3070/// \headerfile <x86intrin.h>3071///3072/// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction.3073///3074/// \param __a3075/// The 128-bit vector of [4 x float] to be broadcast.3076/// \returns A 256-bit vector of [8 x float] whose 128-bit elements are set3077/// equal to the broadcast value.3078static __inline __m256 __DEFAULT_FN_ATTRS3079_mm256_broadcast_ps(__m128 const *__a)3080{3081 __m128 __b = _mm_loadu_ps((const float *)__a);3082 return (__m256)__builtin_shufflevector((__v4sf)__b, (__v4sf)__b,3083 0, 1, 2, 3, 0, 1, 2, 3);3084}3085 3086/* SIMD load ops */3087/// Loads 4 double-precision floating point values from a 32-byte aligned3088/// memory location pointed to by \a __p into a vector of [4 x double].3089///3090/// \headerfile <x86intrin.h>3091///3092/// This intrinsic corresponds to the <c> VMOVAPD </c> instruction.3093///3094/// \param __p3095/// A 32-byte aligned pointer to a memory location containing3096/// double-precision floating point values.3097/// \returns A 256-bit vector of [4 x double] containing the moved values.3098static __inline __m256d __DEFAULT_FN_ATTRS3099_mm256_load_pd(double const *__p)3100{3101 return *(const __m256d *)__p;3102}3103 3104/// Loads 8 single-precision floating point values from a 32-byte aligned3105/// memory location pointed to by \a __p into a vector of [8 x float].3106///3107/// \headerfile <x86intrin.h>3108///3109/// This intrinsic corresponds to the <c> VMOVAPS </c> instruction.3110///3111/// \param __p3112/// A 32-byte aligned pointer to a memory location containing float values.3113/// \returns A 256-bit vector of [8 x float] containing the moved values.3114static __inline __m256 __DEFAULT_FN_ATTRS3115_mm256_load_ps(float const *__p)3116{3117 return *(const __m256 *)__p;3118}3119 3120/// Loads 4 double-precision floating point values from an unaligned3121/// memory location pointed to by \a __p into a vector of [4 x double].3122///3123/// \headerfile <x86intrin.h>3124///3125/// This intrinsic corresponds to the <c> VMOVUPD </c> instruction.3126///3127/// \param __p3128/// A pointer to a memory location containing double-precision floating3129/// point values.3130/// \returns A 256-bit vector of [4 x double] containing the moved values.3131static __inline __m256d __DEFAULT_FN_ATTRS3132_mm256_loadu_pd(double const *__p)3133{3134 struct __loadu_pd {3135 __m256d_u __v;3136 } __attribute__((__packed__, __may_alias__));3137 return ((const struct __loadu_pd*)__p)->__v;3138}3139 3140/// Loads 8 single-precision floating point values from an unaligned3141/// memory location pointed to by \a __p into a vector of [8 x float].3142///3143/// \headerfile <x86intrin.h>3144///3145/// This intrinsic corresponds to the <c> VMOVUPS </c> instruction.3146///3147/// \param __p3148/// A pointer to a memory location containing single-precision floating3149/// point values.3150/// \returns A 256-bit vector of [8 x float] containing the moved values.3151static __inline __m256 __DEFAULT_FN_ATTRS3152_mm256_loadu_ps(float const *__p)3153{3154 struct __loadu_ps {3155 __m256_u __v;3156 } __attribute__((__packed__, __may_alias__));3157 return ((const struct __loadu_ps*)__p)->__v;3158}3159 3160/// Loads 256 bits of integer data from a 32-byte aligned memory3161/// location pointed to by \a __p into elements of a 256-bit integer vector.3162///3163/// \headerfile <x86intrin.h>3164///3165/// This intrinsic corresponds to the <c> VMOVDQA </c> instruction.3166///3167/// \param __p3168/// A 32-byte aligned pointer to a 256-bit integer vector containing integer3169/// values.3170/// \returns A 256-bit integer vector containing the moved values.3171static __inline __m256i __DEFAULT_FN_ATTRS3172_mm256_load_si256(__m256i const *__p)3173{3174 return *__p;3175}3176 3177/// Loads 256 bits of integer data from an unaligned memory location3178/// pointed to by \a __p into a 256-bit integer vector.3179///3180/// \headerfile <x86intrin.h>3181///3182/// This intrinsic corresponds to the <c> VMOVDQU </c> instruction.3183///3184/// \param __p3185/// A pointer to a 256-bit integer vector containing integer values.3186/// \returns A 256-bit integer vector containing the moved values.3187static __inline __m256i __DEFAULT_FN_ATTRS3188_mm256_loadu_si256(__m256i_u const *__p)3189{3190 struct __loadu_si256 {3191 __m256i_u __v;3192 } __attribute__((__packed__, __may_alias__));3193 return ((const struct __loadu_si256*)__p)->__v;3194}3195 3196/// Loads 256 bits of integer data from an unaligned memory location3197/// pointed to by \a __p into a 256-bit integer vector. This intrinsic may3198/// perform better than \c _mm256_loadu_si256 when the data crosses a cache3199/// line boundary.3200///3201/// \headerfile <x86intrin.h>3202///3203/// This intrinsic corresponds to the <c> VLDDQU </c> instruction.3204///3205/// \param __p3206/// A pointer to a 256-bit integer vector containing integer values.3207/// \returns A 256-bit integer vector containing the moved values.3208static __inline __m256i __DEFAULT_FN_ATTRS3209_mm256_lddqu_si256(__m256i_u const *__p)3210{3211 return (__m256i)__builtin_ia32_lddqu256((char const *)__p);3212}3213 3214/* SIMD store ops */3215/// Stores double-precision floating point values from a 256-bit vector3216/// of [4 x double] to a 32-byte aligned memory location pointed to by3217/// \a __p.3218///3219/// \headerfile <x86intrin.h>3220///3221/// This intrinsic corresponds to the <c> VMOVAPD </c> instruction.3222///3223/// \param __p3224/// A 32-byte aligned pointer to a memory location that will receive the3225/// double-precision floaing point values.3226/// \param __a3227/// A 256-bit vector of [4 x double] containing the values to be moved.3228static __inline void __DEFAULT_FN_ATTRS3229_mm256_store_pd(double *__p, __m256d __a)3230{3231 *(__m256d *)__p = __a;3232}3233 3234/// Stores single-precision floating point values from a 256-bit vector3235/// of [8 x float] to a 32-byte aligned memory location pointed to by \a __p.3236///3237/// \headerfile <x86intrin.h>3238///3239/// This intrinsic corresponds to the <c> VMOVAPS </c> instruction.3240///3241/// \param __p3242/// A 32-byte aligned pointer to a memory location that will receive the3243/// float values.3244/// \param __a3245/// A 256-bit vector of [8 x float] containing the values to be moved.3246static __inline void __DEFAULT_FN_ATTRS3247_mm256_store_ps(float *__p, __m256 __a)3248{3249 *(__m256 *)__p = __a;3250}3251 3252/// Stores double-precision floating point values from a 256-bit vector3253/// of [4 x double] to an unaligned memory location pointed to by \a __p.3254///3255/// \headerfile <x86intrin.h>3256///3257/// This intrinsic corresponds to the <c> VMOVUPD </c> instruction.3258///3259/// \param __p3260/// A pointer to a memory location that will receive the double-precision3261/// floating point values.3262/// \param __a3263/// A 256-bit vector of [4 x double] containing the values to be moved.3264static __inline void __DEFAULT_FN_ATTRS3265_mm256_storeu_pd(double *__p, __m256d __a)3266{3267 struct __storeu_pd {3268 __m256d_u __v;3269 } __attribute__((__packed__, __may_alias__));3270 ((struct __storeu_pd*)__p)->__v = __a;3271}3272 3273/// Stores single-precision floating point values from a 256-bit vector3274/// of [8 x float] to an unaligned memory location pointed to by \a __p.3275///3276/// \headerfile <x86intrin.h>3277///3278/// This intrinsic corresponds to the <c> VMOVUPS </c> instruction.3279///3280/// \param __p3281/// A pointer to a memory location that will receive the float values.3282/// \param __a3283/// A 256-bit vector of [8 x float] containing the values to be moved.3284static __inline void __DEFAULT_FN_ATTRS3285_mm256_storeu_ps(float *__p, __m256 __a)3286{3287 struct __storeu_ps {3288 __m256_u __v;3289 } __attribute__((__packed__, __may_alias__));3290 ((struct __storeu_ps*)__p)->__v = __a;3291}3292 3293/// Stores integer values from a 256-bit integer vector to a 32-byte3294/// aligned memory location pointed to by \a __p.3295///3296/// \headerfile <x86intrin.h>3297///3298/// This intrinsic corresponds to the <c> VMOVDQA </c> instruction.3299///3300/// \param __p3301/// A 32-byte aligned pointer to a memory location that will receive the3302/// integer values.3303/// \param __a3304/// A 256-bit integer vector containing the values to be moved.3305static __inline void __DEFAULT_FN_ATTRS3306_mm256_store_si256(__m256i *__p, __m256i __a)3307{3308 *__p = __a;3309}3310 3311/// Stores integer values from a 256-bit integer vector to an unaligned3312/// memory location pointed to by \a __p.3313///3314/// \headerfile <x86intrin.h>3315///3316/// This intrinsic corresponds to the <c> VMOVDQU </c> instruction.3317///3318/// \param __p3319/// A pointer to a memory location that will receive the integer values.3320/// \param __a3321/// A 256-bit integer vector containing the values to be moved.3322static __inline void __DEFAULT_FN_ATTRS3323_mm256_storeu_si256(__m256i_u *__p, __m256i __a)3324{3325 struct __storeu_si256 {3326 __m256i_u __v;3327 } __attribute__((__packed__, __may_alias__));3328 ((struct __storeu_si256*)__p)->__v = __a;3329}3330 3331/* Conditional load ops */3332/// Conditionally loads double-precision floating point elements from a3333/// memory location pointed to by \a __p into a 128-bit vector of3334/// [2 x double], depending on the mask bits associated with each data3335/// element.3336///3337/// \headerfile <x86intrin.h>3338///3339/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction.3340///3341/// \param __p3342/// A pointer to a memory location that contains the double-precision3343/// floating point values.3344/// \param __m3345/// A 128-bit integer vector containing the mask. The most significant bit of3346/// each data element represents the mask bits. If a mask bit is zero, the3347/// corresponding value in the memory location is not loaded and the3348/// corresponding field in the return value is set to zero.3349/// \returns A 128-bit vector of [2 x double] containing the loaded values.3350static __inline __m128d __DEFAULT_FN_ATTRS1283351_mm_maskload_pd(double const *__p, __m128i __m)3352{3353 return (__m128d)__builtin_ia32_maskloadpd((const __v2df *)__p, (__v2di)__m);3354}3355 3356/// Conditionally loads double-precision floating point elements from a3357/// memory location pointed to by \a __p into a 256-bit vector of3358/// [4 x double], depending on the mask bits associated with each data3359/// element.3360///3361/// \headerfile <x86intrin.h>3362///3363/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction.3364///3365/// \param __p3366/// A pointer to a memory location that contains the double-precision3367/// floating point values.3368/// \param __m3369/// A 256-bit integer vector of [4 x quadword] containing the mask. The most3370/// significant bit of each quadword element represents the mask bits. If a3371/// mask bit is zero, the corresponding value in the memory location is not3372/// loaded and the corresponding field in the return value is set to zero.3373/// \returns A 256-bit vector of [4 x double] containing the loaded values.3374static __inline __m256d __DEFAULT_FN_ATTRS3375_mm256_maskload_pd(double const *__p, __m256i __m)3376{3377 return (__m256d)__builtin_ia32_maskloadpd256((const __v4df *)__p,3378 (__v4di)__m);3379}3380 3381/// Conditionally loads single-precision floating point elements from a3382/// memory location pointed to by \a __p into a 128-bit vector of3383/// [4 x float], depending on the mask bits associated with each data3384/// element.3385///3386/// \headerfile <x86intrin.h>3387///3388/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction.3389///3390/// \param __p3391/// A pointer to a memory location that contains the single-precision3392/// floating point values.3393/// \param __m3394/// A 128-bit integer vector containing the mask. The most significant bit of3395/// each data element represents the mask bits. If a mask bit is zero, the3396/// corresponding value in the memory location is not loaded and the3397/// corresponding field in the return value is set to zero.3398/// \returns A 128-bit vector of [4 x float] containing the loaded values.3399static __inline __m128 __DEFAULT_FN_ATTRS1283400_mm_maskload_ps(float const *__p, __m128i __m)3401{3402 return (__m128)__builtin_ia32_maskloadps((const __v4sf *)__p, (__v4si)__m);3403}3404 3405/// Conditionally loads single-precision floating point elements from a3406/// memory location pointed to by \a __p into a 256-bit vector of3407/// [8 x float], depending on the mask bits associated with each data3408/// element.3409///3410/// \headerfile <x86intrin.h>3411///3412/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction.3413///3414/// \param __p3415/// A pointer to a memory location that contains the single-precision3416/// floating point values.3417/// \param __m3418/// A 256-bit integer vector of [8 x dword] containing the mask. The most3419/// significant bit of each dword element represents the mask bits. If a mask3420/// bit is zero, the corresponding value in the memory location is not loaded3421/// and the corresponding field in the return value is set to zero.3422/// \returns A 256-bit vector of [8 x float] containing the loaded values.3423static __inline __m256 __DEFAULT_FN_ATTRS3424_mm256_maskload_ps(float const *__p, __m256i __m)3425{3426 return (__m256)__builtin_ia32_maskloadps256((const __v8sf *)__p, (__v8si)__m);3427}3428 3429/* Conditional store ops */3430/// Moves single-precision floating point values from a 256-bit vector3431/// of [8 x float] to a memory location pointed to by \a __p, according to3432/// the specified mask.3433///3434/// \headerfile <x86intrin.h>3435///3436/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction.3437///3438/// \param __p3439/// A pointer to a memory location that will receive the float values.3440/// \param __m3441/// A 256-bit integer vector of [8 x dword] containing the mask. The most3442/// significant bit of each dword element in the mask vector represents the3443/// mask bits. If a mask bit is zero, the corresponding value from vector3444/// \a __a is not stored and the corresponding field in the memory location3445/// pointed to by \a __p is not changed.3446/// \param __a3447/// A 256-bit vector of [8 x float] containing the values to be stored.3448static __inline void __DEFAULT_FN_ATTRS3449_mm256_maskstore_ps(float *__p, __m256i __m, __m256 __a)3450{3451 __builtin_ia32_maskstoreps256((__v8sf *)__p, (__v8si)__m, (__v8sf)__a);3452}3453 3454/// Moves double-precision values from a 128-bit vector of [2 x double]3455/// to a memory location pointed to by \a __p, according to the specified3456/// mask.3457///3458/// \headerfile <x86intrin.h>3459///3460/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction.3461///3462/// \param __p3463/// A pointer to a memory location that will receive the float values.3464/// \param __m3465/// A 128-bit integer vector containing the mask. The most significant bit of3466/// each field in the mask vector represents the mask bits. If a mask bit is3467/// zero, the corresponding value from vector \a __a is not stored and the3468/// corresponding field in the memory location pointed to by \a __p is not3469/// changed.3470/// \param __a3471/// A 128-bit vector of [2 x double] containing the values to be stored.3472static __inline void __DEFAULT_FN_ATTRS1283473_mm_maskstore_pd(double *__p, __m128i __m, __m128d __a)3474{3475 __builtin_ia32_maskstorepd((__v2df *)__p, (__v2di)__m, (__v2df)__a);3476}3477 3478/// Moves double-precision values from a 256-bit vector of [4 x double]3479/// to a memory location pointed to by \a __p, according to the specified3480/// mask.3481///3482/// \headerfile <x86intrin.h>3483///3484/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction.3485///3486/// \param __p3487/// A pointer to a memory location that will receive the float values.3488/// \param __m3489/// A 256-bit integer vector of [4 x quadword] containing the mask. The most3490/// significant bit of each quadword element in the mask vector represents3491/// the mask bits. If a mask bit is zero, the corresponding value from vector3492/// __a is not stored and the corresponding field in the memory location3493/// pointed to by \a __p is not changed.3494/// \param __a3495/// A 256-bit vector of [4 x double] containing the values to be stored.3496static __inline void __DEFAULT_FN_ATTRS3497_mm256_maskstore_pd(double *__p, __m256i __m, __m256d __a)3498{3499 __builtin_ia32_maskstorepd256((__v4df *)__p, (__v4di)__m, (__v4df)__a);3500}3501 3502/// Moves single-precision floating point values from a 128-bit vector3503/// of [4 x float] to a memory location pointed to by \a __p, according to3504/// the specified mask.3505///3506/// \headerfile <x86intrin.h>3507///3508/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction.3509///3510/// \param __p3511/// A pointer to a memory location that will receive the float values.3512/// \param __m3513/// A 128-bit integer vector containing the mask. The most significant bit of3514/// each field in the mask vector represents the mask bits. If a mask bit is3515/// zero, the corresponding value from vector __a is not stored and the3516/// corresponding field in the memory location pointed to by \a __p is not3517/// changed.3518/// \param __a3519/// A 128-bit vector of [4 x float] containing the values to be stored.3520static __inline void __DEFAULT_FN_ATTRS1283521_mm_maskstore_ps(float *__p, __m128i __m, __m128 __a)3522{3523 __builtin_ia32_maskstoreps((__v4sf *)__p, (__v4si)__m, (__v4sf)__a);3524}3525 3526/* Cacheability support ops */3527/// Moves integer data from a 256-bit integer vector to a 32-byte3528/// aligned memory location. To minimize caching, the data is flagged as3529/// non-temporal (unlikely to be used again soon).3530///3531/// \headerfile <x86intrin.h>3532///3533/// This intrinsic corresponds to the <c> VMOVNTDQ </c> instruction.3534///3535/// \param __a3536/// A pointer to a 32-byte aligned memory location that will receive the3537/// integer values.3538/// \param __b3539/// A 256-bit integer vector containing the values to be moved.3540static __inline void __DEFAULT_FN_ATTRS3541_mm256_stream_si256(void *__a, __m256i __b)3542{3543 typedef __v4di __v4di_aligned __attribute__((aligned(32)));3544 __builtin_nontemporal_store((__v4di_aligned)__b, (__v4di_aligned*)__a);3545}3546 3547/// Moves double-precision values from a 256-bit vector of [4 x double]3548/// to a 32-byte aligned memory location. To minimize caching, the data is3549/// flagged as non-temporal (unlikely to be used again soon).3550///3551/// \headerfile <x86intrin.h>3552///3553/// This intrinsic corresponds to the <c> VMOVNTPD </c> instruction.3554///3555/// \param __a3556/// A pointer to a 32-byte aligned memory location that will receive the3557/// double-precision floating-point values.3558/// \param __b3559/// A 256-bit vector of [4 x double] containing the values to be moved.3560static __inline void __DEFAULT_FN_ATTRS3561_mm256_stream_pd(void *__a, __m256d __b)3562{3563 typedef __v4df __v4df_aligned __attribute__((aligned(32)));3564 __builtin_nontemporal_store((__v4df_aligned)__b, (__v4df_aligned*)__a);3565}3566 3567/// Moves single-precision floating point values from a 256-bit vector3568/// of [8 x float] to a 32-byte aligned memory location. To minimize3569/// caching, the data is flagged as non-temporal (unlikely to be used again3570/// soon).3571///3572/// \headerfile <x86intrin.h>3573///3574/// This intrinsic corresponds to the <c> VMOVNTPS </c> instruction.3575///3576/// \param __p3577/// A pointer to a 32-byte aligned memory location that will receive the3578/// single-precision floating point values.3579/// \param __a3580/// A 256-bit vector of [8 x float] containing the values to be moved.3581static __inline void __DEFAULT_FN_ATTRS3582_mm256_stream_ps(void *__p, __m256 __a)3583{3584 typedef __v8sf __v8sf_aligned __attribute__((aligned(32)));3585 __builtin_nontemporal_store((__v8sf_aligned)__a, (__v8sf_aligned*)__p);3586}3587 3588/* Create vectors */3589/// Create a 256-bit vector of [4 x double] with undefined values.3590///3591/// \headerfile <x86intrin.h>3592///3593/// This intrinsic has no corresponding instruction.3594///3595/// \returns A 256-bit vector of [4 x double] containing undefined values.3596static __inline__ __m256d __DEFAULT_FN_ATTRS3597_mm256_undefined_pd(void)3598{3599 return (__m256d)__builtin_ia32_undef256();3600}3601 3602/// Create a 256-bit vector of [8 x float] with undefined values.3603///3604/// \headerfile <x86intrin.h>3605///3606/// This intrinsic has no corresponding instruction.3607///3608/// \returns A 256-bit vector of [8 x float] containing undefined values.3609static __inline__ __m256 __DEFAULT_FN_ATTRS3610_mm256_undefined_ps(void)3611{3612 return (__m256)__builtin_ia32_undef256();3613}3614 3615/// Create a 256-bit integer vector with undefined values.3616///3617/// \headerfile <x86intrin.h>3618///3619/// This intrinsic has no corresponding instruction.3620///3621/// \returns A 256-bit integer vector containing undefined values.3622static __inline__ __m256i __DEFAULT_FN_ATTRS3623_mm256_undefined_si256(void)3624{3625 return (__m256i)__builtin_ia32_undef256();3626}3627 3628/// Constructs a 256-bit floating-point vector of [4 x double]3629/// initialized with the specified double-precision floating-point values.3630///3631/// \headerfile <x86intrin.h>3632///3633/// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c>3634/// instruction.3635///3636/// \param __a3637/// A double-precision floating-point value used to initialize bits [255:192]3638/// of the result.3639/// \param __b3640/// A double-precision floating-point value used to initialize bits [191:128]3641/// of the result.3642/// \param __c3643/// A double-precision floating-point value used to initialize bits [127:64]3644/// of the result.3645/// \param __d3646/// A double-precision floating-point value used to initialize bits [63:0]3647/// of the result.3648/// \returns An initialized 256-bit floating-point vector of [4 x double].3649static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR3650_mm256_set_pd(double __a, double __b, double __c, double __d)3651{3652 return __extension__ (__m256d){ __d, __c, __b, __a };3653}3654 3655/// Constructs a 256-bit floating-point vector of [8 x float] initialized3656/// with the specified single-precision floating-point values.3657///3658/// \headerfile <x86intrin.h>3659///3660/// This intrinsic is a utility function and does not correspond to a specific3661/// instruction.3662///3663/// \param __a3664/// A single-precision floating-point value used to initialize bits [255:224]3665/// of the result.3666/// \param __b3667/// A single-precision floating-point value used to initialize bits [223:192]3668/// of the result.3669/// \param __c3670/// A single-precision floating-point value used to initialize bits [191:160]3671/// of the result.3672/// \param __d3673/// A single-precision floating-point value used to initialize bits [159:128]3674/// of the result.3675/// \param __e3676/// A single-precision floating-point value used to initialize bits [127:96]3677/// of the result.3678/// \param __f3679/// A single-precision floating-point value used to initialize bits [95:64]3680/// of the result.3681/// \param __g3682/// A single-precision floating-point value used to initialize bits [63:32]3683/// of the result.3684/// \param __h3685/// A single-precision floating-point value used to initialize bits [31:0]3686/// of the result.3687/// \returns An initialized 256-bit floating-point vector of [8 x float].3688static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR3689_mm256_set_ps(float __a, float __b, float __c, float __d,3690 float __e, float __f, float __g, float __h)3691{3692 return __extension__ (__m256){ __h, __g, __f, __e, __d, __c, __b, __a };3693}3694 3695/// Constructs a 256-bit integer vector initialized with the specified3696/// 32-bit integral values.3697///3698/// \headerfile <x86intrin.h>3699///3700/// This intrinsic is a utility function and does not correspond to a specific3701/// instruction.3702///3703/// \param __i03704/// A 32-bit integral value used to initialize bits [255:224] of the result.3705/// \param __i13706/// A 32-bit integral value used to initialize bits [223:192] of the result.3707/// \param __i23708/// A 32-bit integral value used to initialize bits [191:160] of the result.3709/// \param __i33710/// A 32-bit integral value used to initialize bits [159:128] of the result.3711/// \param __i43712/// A 32-bit integral value used to initialize bits [127:96] of the result.3713/// \param __i53714/// A 32-bit integral value used to initialize bits [95:64] of the result.3715/// \param __i63716/// A 32-bit integral value used to initialize bits [63:32] of the result.3717/// \param __i73718/// A 32-bit integral value used to initialize bits [31:0] of the result.3719/// \returns An initialized 256-bit integer vector.3720static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR3721_mm256_set_epi32(int __i0, int __i1, int __i2, int __i3,3722 int __i4, int __i5, int __i6, int __i7)3723{3724 return __extension__ (__m256i)(__v8si){ __i7, __i6, __i5, __i4, __i3, __i2, __i1, __i0 };3725}3726 3727/// Constructs a 256-bit integer vector initialized with the specified3728/// 16-bit integral values.3729///3730/// \headerfile <x86intrin.h>3731///3732/// This intrinsic is a utility function and does not correspond to a specific3733/// instruction.3734///3735/// \param __w153736/// A 16-bit integral value used to initialize bits [255:240] of the result.3737/// \param __w143738/// A 16-bit integral value used to initialize bits [239:224] of the result.3739/// \param __w133740/// A 16-bit integral value used to initialize bits [223:208] of the result.3741/// \param __w123742/// A 16-bit integral value used to initialize bits [207:192] of the result.3743/// \param __w113744/// A 16-bit integral value used to initialize bits [191:176] of the result.3745/// \param __w103746/// A 16-bit integral value used to initialize bits [175:160] of the result.3747/// \param __w093748/// A 16-bit integral value used to initialize bits [159:144] of the result.3749/// \param __w083750/// A 16-bit integral value used to initialize bits [143:128] of the result.3751/// \param __w073752/// A 16-bit integral value used to initialize bits [127:112] of the result.3753/// \param __w063754/// A 16-bit integral value used to initialize bits [111:96] of the result.3755/// \param __w053756/// A 16-bit integral value used to initialize bits [95:80] of the result.3757/// \param __w043758/// A 16-bit integral value used to initialize bits [79:64] of the result.3759/// \param __w033760/// A 16-bit integral value used to initialize bits [63:48] of the result.3761/// \param __w023762/// A 16-bit integral value used to initialize bits [47:32] of the result.3763/// \param __w013764/// A 16-bit integral value used to initialize bits [31:16] of the result.3765/// \param __w003766/// A 16-bit integral value used to initialize bits [15:0] of the result.3767/// \returns An initialized 256-bit integer vector.3768static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR3769_mm256_set_epi16(short __w15, short __w14, short __w13, short __w12,3770 short __w11, short __w10, short __w09, short __w08,3771 short __w07, short __w06, short __w05, short __w04,3772 short __w03, short __w02, short __w01, short __w00)3773{3774 return __extension__ (__m256i)(__v16hi){ __w00, __w01, __w02, __w03, __w04, __w05, __w06,3775 __w07, __w08, __w09, __w10, __w11, __w12, __w13, __w14, __w15 };3776}3777 3778/// Constructs a 256-bit integer vector initialized with the specified3779/// 8-bit integral values.3780///3781/// \headerfile <x86intrin.h>3782///3783/// This intrinsic is a utility function and does not correspond to a specific3784/// instruction.3785///3786/// \param __b313787/// An 8-bit integral value used to initialize bits [255:248] of the result.3788/// \param __b303789/// An 8-bit integral value used to initialize bits [247:240] of the result.3790/// \param __b293791/// An 8-bit integral value used to initialize bits [239:232] of the result.3792/// \param __b283793/// An 8-bit integral value used to initialize bits [231:224] of the result.3794/// \param __b273795/// An 8-bit integral value used to initialize bits [223:216] of the result.3796/// \param __b263797/// An 8-bit integral value used to initialize bits [215:208] of the result.3798/// \param __b253799/// An 8-bit integral value used to initialize bits [207:200] of the result.3800/// \param __b243801/// An 8-bit integral value used to initialize bits [199:192] of the result.3802/// \param __b233803/// An 8-bit integral value used to initialize bits [191:184] of the result.3804/// \param __b223805/// An 8-bit integral value used to initialize bits [183:176] of the result.3806/// \param __b213807/// An 8-bit integral value used to initialize bits [175:168] of the result.3808/// \param __b203809/// An 8-bit integral value used to initialize bits [167:160] of the result.3810/// \param __b193811/// An 8-bit integral value used to initialize bits [159:152] of the result.3812/// \param __b183813/// An 8-bit integral value used to initialize bits [151:144] of the result.3814/// \param __b173815/// An 8-bit integral value used to initialize bits [143:136] of the result.3816/// \param __b163817/// An 8-bit integral value used to initialize bits [135:128] of the result.3818/// \param __b153819/// An 8-bit integral value used to initialize bits [127:120] of the result.3820/// \param __b143821/// An 8-bit integral value used to initialize bits [119:112] of the result.3822/// \param __b133823/// An 8-bit integral value used to initialize bits [111:104] of the result.3824/// \param __b123825/// An 8-bit integral value used to initialize bits [103:96] of the result.3826/// \param __b113827/// An 8-bit integral value used to initialize bits [95:88] of the result.3828/// \param __b103829/// An 8-bit integral value used to initialize bits [87:80] of the result.3830/// \param __b093831/// An 8-bit integral value used to initialize bits [79:72] of the result.3832/// \param __b083833/// An 8-bit integral value used to initialize bits [71:64] of the result.3834/// \param __b073835/// An 8-bit integral value used to initialize bits [63:56] of the result.3836/// \param __b063837/// An 8-bit integral value used to initialize bits [55:48] of the result.3838/// \param __b053839/// An 8-bit integral value used to initialize bits [47:40] of the result.3840/// \param __b043841/// An 8-bit integral value used to initialize bits [39:32] of the result.3842/// \param __b033843/// An 8-bit integral value used to initialize bits [31:24] of the result.3844/// \param __b023845/// An 8-bit integral value used to initialize bits [23:16] of the result.3846/// \param __b013847/// An 8-bit integral value used to initialize bits [15:8] of the result.3848/// \param __b003849/// An 8-bit integral value used to initialize bits [7:0] of the result.3850/// \returns An initialized 256-bit integer vector.3851static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR3852_mm256_set_epi8(char __b31, char __b30, char __b29, char __b28,3853 char __b27, char __b26, char __b25, char __b24,3854 char __b23, char __b22, char __b21, char __b20,3855 char __b19, char __b18, char __b17, char __b16,3856 char __b15, char __b14, char __b13, char __b12,3857 char __b11, char __b10, char __b09, char __b08,3858 char __b07, char __b06, char __b05, char __b04,3859 char __b03, char __b02, char __b01, char __b00)3860{3861 return __extension__ (__m256i)(__v32qi){3862 __b00, __b01, __b02, __b03, __b04, __b05, __b06, __b07,3863 __b08, __b09, __b10, __b11, __b12, __b13, __b14, __b15,3864 __b16, __b17, __b18, __b19, __b20, __b21, __b22, __b23,3865 __b24, __b25, __b26, __b27, __b28, __b29, __b30, __b313866 };3867}3868 3869/// Constructs a 256-bit integer vector initialized with the specified3870/// 64-bit integral values.3871///3872/// \headerfile <x86intrin.h>3873///3874/// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c>3875/// instruction.3876///3877/// \param __a3878/// A 64-bit integral value used to initialize bits [255:192] of the result.3879/// \param __b3880/// A 64-bit integral value used to initialize bits [191:128] of the result.3881/// \param __c3882/// A 64-bit integral value used to initialize bits [127:64] of the result.3883/// \param __d3884/// A 64-bit integral value used to initialize bits [63:0] of the result.3885/// \returns An initialized 256-bit integer vector.3886static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR3887_mm256_set_epi64x(long long __a, long long __b, long long __c, long long __d)3888{3889 return __extension__ (__m256i)(__v4di){ __d, __c, __b, __a };3890}3891 3892/* Create vectors with elements in reverse order */3893/// Constructs a 256-bit floating-point vector of [4 x double],3894/// initialized in reverse order with the specified double-precision3895/// floating-point values.3896///3897/// \headerfile <x86intrin.h>3898///3899/// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c>3900/// instruction.3901///3902/// \param __a3903/// A double-precision floating-point value used to initialize bits [63:0]3904/// of the result.3905/// \param __b3906/// A double-precision floating-point value used to initialize bits [127:64]3907/// of the result.3908/// \param __c3909/// A double-precision floating-point value used to initialize bits [191:128]3910/// of the result.3911/// \param __d3912/// A double-precision floating-point value used to initialize bits [255:192]3913/// of the result.3914/// \returns An initialized 256-bit floating-point vector of [4 x double].3915static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR3916_mm256_setr_pd(double __a, double __b, double __c, double __d)3917{3918 return _mm256_set_pd(__d, __c, __b, __a);3919}3920 3921/// Constructs a 256-bit floating-point vector of [8 x float],3922/// initialized in reverse order with the specified single-precision3923/// float-point values.3924///3925/// \headerfile <x86intrin.h>3926///3927/// This intrinsic is a utility function and does not correspond to a specific3928/// instruction.3929///3930/// \param __a3931/// A single-precision floating-point value used to initialize bits [31:0]3932/// of the result.3933/// \param __b3934/// A single-precision floating-point value used to initialize bits [63:32]3935/// of the result.3936/// \param __c3937/// A single-precision floating-point value used to initialize bits [95:64]3938/// of the result.3939/// \param __d3940/// A single-precision floating-point value used to initialize bits [127:96]3941/// of the result.3942/// \param __e3943/// A single-precision floating-point value used to initialize bits [159:128]3944/// of the result.3945/// \param __f3946/// A single-precision floating-point value used to initialize bits [191:160]3947/// of the result.3948/// \param __g3949/// A single-precision floating-point value used to initialize bits [223:192]3950/// of the result.3951/// \param __h3952/// A single-precision floating-point value used to initialize bits [255:224]3953/// of the result.3954/// \returns An initialized 256-bit floating-point vector of [8 x float].3955static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR3956_mm256_setr_ps(float __a, float __b, float __c, float __d,3957 float __e, float __f, float __g, float __h)3958{3959 return _mm256_set_ps(__h, __g, __f, __e, __d, __c, __b, __a);3960}3961 3962/// Constructs a 256-bit integer vector, initialized in reverse order3963/// with the specified 32-bit integral values.3964///3965/// \headerfile <x86intrin.h>3966///3967/// This intrinsic is a utility function and does not correspond to a specific3968/// instruction.3969///3970/// \param __i03971/// A 32-bit integral value used to initialize bits [31:0] of the result.3972/// \param __i13973/// A 32-bit integral value used to initialize bits [63:32] of the result.3974/// \param __i23975/// A 32-bit integral value used to initialize bits [95:64] of the result.3976/// \param __i33977/// A 32-bit integral value used to initialize bits [127:96] of the result.3978/// \param __i43979/// A 32-bit integral value used to initialize bits [159:128] of the result.3980/// \param __i53981/// A 32-bit integral value used to initialize bits [191:160] of the result.3982/// \param __i63983/// A 32-bit integral value used to initialize bits [223:192] of the result.3984/// \param __i73985/// A 32-bit integral value used to initialize bits [255:224] of the result.3986/// \returns An initialized 256-bit integer vector.3987static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR3988_mm256_setr_epi32(int __i0, int __i1, int __i2, int __i3,3989 int __i4, int __i5, int __i6, int __i7)3990{3991 return _mm256_set_epi32(__i7, __i6, __i5, __i4, __i3, __i2, __i1, __i0);3992}3993 3994/// Constructs a 256-bit integer vector, initialized in reverse order3995/// with the specified 16-bit integral values.3996///3997/// \headerfile <x86intrin.h>3998///3999/// This intrinsic is a utility function and does not correspond to a specific4000/// instruction.4001///4002/// \param __w154003/// A 16-bit integral value used to initialize bits [15:0] of the result.4004/// \param __w144005/// A 16-bit integral value used to initialize bits [31:16] of the result.4006/// \param __w134007/// A 16-bit integral value used to initialize bits [47:32] of the result.4008/// \param __w124009/// A 16-bit integral value used to initialize bits [63:48] of the result.4010/// \param __w114011/// A 16-bit integral value used to initialize bits [79:64] of the result.4012/// \param __w104013/// A 16-bit integral value used to initialize bits [95:80] of the result.4014/// \param __w094015/// A 16-bit integral value used to initialize bits [111:96] of the result.4016/// \param __w084017/// A 16-bit integral value used to initialize bits [127:112] of the result.4018/// \param __w074019/// A 16-bit integral value used to initialize bits [143:128] of the result.4020/// \param __w064021/// A 16-bit integral value used to initialize bits [159:144] of the result.4022/// \param __w054023/// A 16-bit integral value used to initialize bits [175:160] of the result.4024/// \param __w044025/// A 16-bit integral value used to initialize bits [191:176] of the result.4026/// \param __w034027/// A 16-bit integral value used to initialize bits [207:192] of the result.4028/// \param __w024029/// A 16-bit integral value used to initialize bits [223:208] of the result.4030/// \param __w014031/// A 16-bit integral value used to initialize bits [239:224] of the result.4032/// \param __w004033/// A 16-bit integral value used to initialize bits [255:240] of the result.4034/// \returns An initialized 256-bit integer vector.4035static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4036_mm256_setr_epi16(short __w15, short __w14, short __w13, short __w12,4037 short __w11, short __w10, short __w09, short __w08,4038 short __w07, short __w06, short __w05, short __w04,4039 short __w03, short __w02, short __w01, short __w00)4040{4041 return _mm256_set_epi16(__w00, __w01, __w02, __w03,4042 __w04, __w05, __w06, __w07,4043 __w08, __w09, __w10, __w11,4044 __w12, __w13, __w14, __w15);4045}4046 4047/// Constructs a 256-bit integer vector, initialized in reverse order4048/// with the specified 8-bit integral values.4049///4050/// \headerfile <x86intrin.h>4051///4052/// This intrinsic is a utility function and does not correspond to a specific4053/// instruction.4054///4055/// \param __b314056/// An 8-bit integral value used to initialize bits [7:0] of the result.4057/// \param __b304058/// An 8-bit integral value used to initialize bits [15:8] of the result.4059/// \param __b294060/// An 8-bit integral value used to initialize bits [23:16] of the result.4061/// \param __b284062/// An 8-bit integral value used to initialize bits [31:24] of the result.4063/// \param __b274064/// An 8-bit integral value used to initialize bits [39:32] of the result.4065/// \param __b264066/// An 8-bit integral value used to initialize bits [47:40] of the result.4067/// \param __b254068/// An 8-bit integral value used to initialize bits [55:48] of the result.4069/// \param __b244070/// An 8-bit integral value used to initialize bits [63:56] of the result.4071/// \param __b234072/// An 8-bit integral value used to initialize bits [71:64] of the result.4073/// \param __b224074/// An 8-bit integral value used to initialize bits [79:72] of the result.4075/// \param __b214076/// An 8-bit integral value used to initialize bits [87:80] of the result.4077/// \param __b204078/// An 8-bit integral value used to initialize bits [95:88] of the result.4079/// \param __b194080/// An 8-bit integral value used to initialize bits [103:96] of the result.4081/// \param __b184082/// An 8-bit integral value used to initialize bits [111:104] of the result.4083/// \param __b174084/// An 8-bit integral value used to initialize bits [119:112] of the result.4085/// \param __b164086/// An 8-bit integral value used to initialize bits [127:120] of the result.4087/// \param __b154088/// An 8-bit integral value used to initialize bits [135:128] of the result.4089/// \param __b144090/// An 8-bit integral value used to initialize bits [143:136] of the result.4091/// \param __b134092/// An 8-bit integral value used to initialize bits [151:144] of the result.4093/// \param __b124094/// An 8-bit integral value used to initialize bits [159:152] of the result.4095/// \param __b114096/// An 8-bit integral value used to initialize bits [167:160] of the result.4097/// \param __b104098/// An 8-bit integral value used to initialize bits [175:168] of the result.4099/// \param __b094100/// An 8-bit integral value used to initialize bits [183:176] of the result.4101/// \param __b084102/// An 8-bit integral value used to initialize bits [191:184] of the result.4103/// \param __b074104/// An 8-bit integral value used to initialize bits [199:192] of the result.4105/// \param __b064106/// An 8-bit integral value used to initialize bits [207:200] of the result.4107/// \param __b054108/// An 8-bit integral value used to initialize bits [215:208] of the result.4109/// \param __b044110/// An 8-bit integral value used to initialize bits [223:216] of the result.4111/// \param __b034112/// An 8-bit integral value used to initialize bits [231:224] of the result.4113/// \param __b024114/// An 8-bit integral value used to initialize bits [239:232] of the result.4115/// \param __b014116/// An 8-bit integral value used to initialize bits [247:240] of the result.4117/// \param __b004118/// An 8-bit integral value used to initialize bits [255:248] of the result.4119/// \returns An initialized 256-bit integer vector.4120static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4121_mm256_setr_epi8(char __b31, char __b30, char __b29, char __b28,4122 char __b27, char __b26, char __b25, char __b24,4123 char __b23, char __b22, char __b21, char __b20,4124 char __b19, char __b18, char __b17, char __b16,4125 char __b15, char __b14, char __b13, char __b12,4126 char __b11, char __b10, char __b09, char __b08,4127 char __b07, char __b06, char __b05, char __b04,4128 char __b03, char __b02, char __b01, char __b00)4129{4130 return _mm256_set_epi8(__b00, __b01, __b02, __b03, __b04, __b05, __b06, __b07,4131 __b08, __b09, __b10, __b11, __b12, __b13, __b14, __b15,4132 __b16, __b17, __b18, __b19, __b20, __b21, __b22, __b23,4133 __b24, __b25, __b26, __b27, __b28, __b29, __b30, __b31);4134}4135 4136/// Constructs a 256-bit integer vector, initialized in reverse order4137/// with the specified 64-bit integral values.4138///4139/// \headerfile <x86intrin.h>4140///4141/// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c>4142/// instruction.4143///4144/// \param __a4145/// A 64-bit integral value used to initialize bits [63:0] of the result.4146/// \param __b4147/// A 64-bit integral value used to initialize bits [127:64] of the result.4148/// \param __c4149/// A 64-bit integral value used to initialize bits [191:128] of the result.4150/// \param __d4151/// A 64-bit integral value used to initialize bits [255:192] of the result.4152/// \returns An initialized 256-bit integer vector.4153static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4154_mm256_setr_epi64x(long long __a, long long __b, long long __c, long long __d)4155{4156 return _mm256_set_epi64x(__d, __c, __b, __a);4157}4158 4159/* Create vectors with repeated elements */4160/// Constructs a 256-bit floating-point vector of [4 x double], with each4161/// of the four double-precision floating-point vector elements set to the4162/// specified double-precision floating-point value.4163///4164/// \headerfile <x86intrin.h>4165///4166/// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction.4167///4168/// \param __w4169/// A double-precision floating-point value used to initialize each vector4170/// element of the result.4171/// \returns An initialized 256-bit floating-point vector of [4 x double].4172static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4173_mm256_set1_pd(double __w)4174{4175 return _mm256_set_pd(__w, __w, __w, __w);4176}4177 4178/// Constructs a 256-bit floating-point vector of [8 x float], with each4179/// of the eight single-precision floating-point vector elements set to the4180/// specified single-precision floating-point value.4181///4182/// \headerfile <x86intrin.h>4183///4184/// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c>4185/// instruction.4186///4187/// \param __w4188/// A single-precision floating-point value used to initialize each vector4189/// element of the result.4190/// \returns An initialized 256-bit floating-point vector of [8 x float].4191static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4192_mm256_set1_ps(float __w)4193{4194 return _mm256_set_ps(__w, __w, __w, __w, __w, __w, __w, __w);4195}4196 4197/// Constructs a 256-bit integer vector of [8 x i32], with each of the4198/// 32-bit integral vector elements set to the specified 32-bit integral4199/// value.4200///4201/// \headerfile <x86intrin.h>4202///4203/// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c>4204/// instruction.4205///4206/// \param __i4207/// A 32-bit integral value used to initialize each vector element of the4208/// result.4209/// \returns An initialized 256-bit integer vector of [8 x i32].4210static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4211_mm256_set1_epi32(int __i)4212{4213 return _mm256_set_epi32(__i, __i, __i, __i, __i, __i, __i, __i);4214}4215 4216/// Constructs a 256-bit integer vector of [16 x i16], with each of the4217/// 16-bit integral vector elements set to the specified 16-bit integral4218/// value.4219///4220/// \headerfile <x86intrin.h>4221///4222/// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction.4223///4224/// \param __w4225/// A 16-bit integral value used to initialize each vector element of the4226/// result.4227/// \returns An initialized 256-bit integer vector of [16 x i16].4228static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4229_mm256_set1_epi16(short __w)4230{4231 return _mm256_set_epi16(__w, __w, __w, __w, __w, __w, __w, __w,4232 __w, __w, __w, __w, __w, __w, __w, __w);4233}4234 4235/// Constructs a 256-bit integer vector of [32 x i8], with each of the4236/// 8-bit integral vector elements set to the specified 8-bit integral value.4237///4238/// \headerfile <x86intrin.h>4239///4240/// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction.4241///4242/// \param __b4243/// An 8-bit integral value used to initialize each vector element of the4244/// result.4245/// \returns An initialized 256-bit integer vector of [32 x i8].4246static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4247_mm256_set1_epi8(char __b)4248{4249 return _mm256_set_epi8(__b, __b, __b, __b, __b, __b, __b, __b,4250 __b, __b, __b, __b, __b, __b, __b, __b,4251 __b, __b, __b, __b, __b, __b, __b, __b,4252 __b, __b, __b, __b, __b, __b, __b, __b);4253}4254 4255/// Constructs a 256-bit integer vector of [4 x i64], with each of the4256/// 64-bit integral vector elements set to the specified 64-bit integral4257/// value.4258///4259/// \headerfile <x86intrin.h>4260///4261/// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction.4262///4263/// \param __q4264/// A 64-bit integral value used to initialize each vector element of the4265/// result.4266/// \returns An initialized 256-bit integer vector of [4 x i64].4267static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4268_mm256_set1_epi64x(long long __q)4269{4270 return _mm256_set_epi64x(__q, __q, __q, __q);4271}4272 4273/* Create __zeroed vectors */4274/// Constructs a 256-bit floating-point vector of [4 x double] with all4275/// vector elements initialized to zero.4276///4277/// \headerfile <x86intrin.h>4278///4279/// This intrinsic corresponds to the <c> VXORPS </c> instruction.4280///4281/// \returns A 256-bit vector of [4 x double] with all elements set to zero.4282static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_setzero_pd(void) {4283 return __extension__(__m256d){0.0, 0.0, 0.0, 0.0};4284}4285 4286/// Constructs a 256-bit floating-point vector of [8 x float] with all4287/// vector elements initialized to zero.4288///4289/// \headerfile <x86intrin.h>4290///4291/// This intrinsic corresponds to the <c> VXORPS </c> instruction.4292///4293/// \returns A 256-bit vector of [8 x float] with all elements set to zero.4294static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR _mm256_setzero_ps(void) {4295 return __extension__ (__m256){ 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f };4296}4297 4298/// Constructs a 256-bit integer vector initialized to zero.4299///4300/// \headerfile <x86intrin.h>4301///4302/// This intrinsic corresponds to the <c> VXORPS </c> instruction.4303///4304/// \returns A 256-bit integer vector initialized to zero.4305static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4306_mm256_setzero_si256(void) {4307 return __extension__ (__m256i)(__v4di){ 0, 0, 0, 0 };4308}4309 4310/* Cast between vector types */4311/// Casts a 256-bit floating-point vector of [4 x double] into a 256-bit4312/// floating-point vector of [8 x float].4313///4314/// \headerfile <x86intrin.h>4315///4316/// This intrinsic has no corresponding instruction.4317///4318/// \param __a4319/// A 256-bit floating-point vector of [4 x double].4320/// \returns A 256-bit floating-point vector of [8 x float] containing the same4321/// bitwise pattern as the parameter.4322static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4323_mm256_castpd_ps(__m256d __a)4324{4325 return (__m256)__a;4326}4327 4328/// Casts a 256-bit floating-point vector of [4 x double] into a 256-bit4329/// integer vector.4330///4331/// \headerfile <x86intrin.h>4332///4333/// This intrinsic has no corresponding instruction.4334///4335/// \param __a4336/// A 256-bit floating-point vector of [4 x double].4337/// \returns A 256-bit integer vector containing the same bitwise pattern as the4338/// parameter.4339static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4340_mm256_castpd_si256(__m256d __a)4341{4342 return (__m256i)__a;4343}4344 4345/// Casts a 256-bit floating-point vector of [8 x float] into a 256-bit4346/// floating-point vector of [4 x double].4347///4348/// \headerfile <x86intrin.h>4349///4350/// This intrinsic has no corresponding instruction.4351///4352/// \param __a4353/// A 256-bit floating-point vector of [8 x float].4354/// \returns A 256-bit floating-point vector of [4 x double] containing the same4355/// bitwise pattern as the parameter.4356static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4357_mm256_castps_pd(__m256 __a)4358{4359 return (__m256d)__a;4360}4361 4362/// Casts a 256-bit floating-point vector of [8 x float] into a 256-bit4363/// integer vector.4364///4365/// \headerfile <x86intrin.h>4366///4367/// This intrinsic has no corresponding instruction.4368///4369/// \param __a4370/// A 256-bit floating-point vector of [8 x float].4371/// \returns A 256-bit integer vector containing the same bitwise pattern as the4372/// parameter.4373static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4374_mm256_castps_si256(__m256 __a)4375{4376 return (__m256i)__a;4377}4378 4379/// Casts a 256-bit integer vector into a 256-bit floating-point vector4380/// of [8 x float].4381///4382/// \headerfile <x86intrin.h>4383///4384/// This intrinsic has no corresponding instruction.4385///4386/// \param __a4387/// A 256-bit integer vector.4388/// \returns A 256-bit floating-point vector of [8 x float] containing the same4389/// bitwise pattern as the parameter.4390static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4391_mm256_castsi256_ps(__m256i __a)4392{4393 return (__m256)__a;4394}4395 4396/// Casts a 256-bit integer vector into a 256-bit floating-point vector4397/// of [4 x double].4398///4399/// \headerfile <x86intrin.h>4400///4401/// This intrinsic has no corresponding instruction.4402///4403/// \param __a4404/// A 256-bit integer vector.4405/// \returns A 256-bit floating-point vector of [4 x double] containing the same4406/// bitwise pattern as the parameter.4407static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4408_mm256_castsi256_pd(__m256i __a)4409{4410 return (__m256d)__a;4411}4412 4413/// Returns the lower 128 bits of a 256-bit floating-point vector of4414/// [4 x double] as a 128-bit floating-point vector of [2 x double].4415///4416/// \headerfile <x86intrin.h>4417///4418/// This intrinsic has no corresponding instruction.4419///4420/// \param __a4421/// A 256-bit floating-point vector of [4 x double].4422/// \returns A 128-bit floating-point vector of [2 x double] containing the4423/// lower 128 bits of the parameter.4424static __inline __m128d __DEFAULT_FN_ATTRS_CONSTEXPR4425_mm256_castpd256_pd128(__m256d __a)4426{4427 return __builtin_shufflevector((__v4df)__a, (__v4df)__a, 0, 1);4428}4429 4430/// Returns the lower 128 bits of a 256-bit floating-point vector of4431/// [8 x float] as a 128-bit floating-point vector of [4 x float].4432///4433/// \headerfile <x86intrin.h>4434///4435/// This intrinsic has no corresponding instruction.4436///4437/// \param __a4438/// A 256-bit floating-point vector of [8 x float].4439/// \returns A 128-bit floating-point vector of [4 x float] containing the4440/// lower 128 bits of the parameter.4441static __inline __m128 __DEFAULT_FN_ATTRS_CONSTEXPR4442_mm256_castps256_ps128(__m256 __a)4443{4444 return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 1, 2, 3);4445}4446 4447/// Truncates a 256-bit integer vector into a 128-bit integer vector.4448///4449/// \headerfile <x86intrin.h>4450///4451/// This intrinsic has no corresponding instruction.4452///4453/// \param __a4454/// A 256-bit integer vector.4455/// \returns A 128-bit integer vector containing the lower 128 bits of the4456/// parameter.4457static __inline __m128i __DEFAULT_FN_ATTRS_CONSTEXPR4458_mm256_castsi256_si128(__m256i __a)4459{4460 return __builtin_shufflevector((__v4di)__a, (__v4di)__a, 0, 1);4461}4462 4463/// Constructs a 256-bit floating-point vector of [4 x double] from a4464/// 128-bit floating-point vector of [2 x double].4465///4466/// The lower 128 bits contain the value of the source vector. The contents4467/// of the upper 128 bits are undefined.4468///4469/// \headerfile <x86intrin.h>4470///4471/// This intrinsic has no corresponding instruction.4472///4473/// \param __a4474/// A 128-bit vector of [2 x double].4475/// \returns A 256-bit floating-point vector of [4 x double]. The lower 128 bits4476/// contain the value of the parameter. The contents of the upper 128 bits4477/// are undefined.4478static __inline __m256d __DEFAULT_FN_ATTRS4479_mm256_castpd128_pd256(__m128d __a)4480{4481 return __builtin_shufflevector(4482 (__v2df)__a, (__v2df)__builtin_nondeterministic_value(__a), 0, 1, 2, 3);4483}4484 4485/// Constructs a 256-bit floating-point vector of [8 x float] from a4486/// 128-bit floating-point vector of [4 x float].4487///4488/// The lower 128 bits contain the value of the source vector. The contents4489/// of the upper 128 bits are undefined.4490///4491/// \headerfile <x86intrin.h>4492///4493/// This intrinsic has no corresponding instruction.4494///4495/// \param __a4496/// A 128-bit vector of [4 x float].4497/// \returns A 256-bit floating-point vector of [8 x float]. The lower 128 bits4498/// contain the value of the parameter. The contents of the upper 128 bits4499/// are undefined.4500static __inline __m256 __DEFAULT_FN_ATTRS4501_mm256_castps128_ps256(__m128 __a)4502{4503 return __builtin_shufflevector((__v4sf)__a,4504 (__v4sf)__builtin_nondeterministic_value(__a),4505 0, 1, 2, 3, 4, 5, 6, 7);4506}4507 4508/// Constructs a 256-bit integer vector from a 128-bit integer vector.4509///4510/// The lower 128 bits contain the value of the source vector. The contents4511/// of the upper 128 bits are undefined.4512///4513/// \headerfile <x86intrin.h>4514///4515/// This intrinsic has no corresponding instruction.4516///4517/// \param __a4518/// A 128-bit integer vector.4519/// \returns A 256-bit integer vector. The lower 128 bits contain the value of4520/// the parameter. The contents of the upper 128 bits are undefined.4521static __inline __m256i __DEFAULT_FN_ATTRS4522_mm256_castsi128_si256(__m128i __a)4523{4524 return __builtin_shufflevector(4525 (__v2di)__a, (__v2di)__builtin_nondeterministic_value(__a), 0, 1, 2, 3);4526}4527 4528/// Constructs a 256-bit floating-point vector of [4 x double] from a4529/// 128-bit floating-point vector of [2 x double]. The lower 128 bits4530/// contain the value of the source vector. The upper 128 bits are set4531/// to zero.4532///4533/// \headerfile <x86intrin.h>4534///4535/// This intrinsic has no corresponding instruction.4536///4537/// \param __a4538/// A 128-bit vector of [2 x double].4539/// \returns A 256-bit floating-point vector of [4 x double]. The lower 128 bits4540/// contain the value of the parameter. The upper 128 bits are set to zero.4541static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4542_mm256_zextpd128_pd256(__m128d __a) {4543 return __builtin_shufflevector((__v2df)__a, (__v2df)_mm_setzero_pd(), 0, 1, 2, 3);4544}4545 4546/// Constructs a 256-bit floating-point vector of [8 x float] from a4547/// 128-bit floating-point vector of [4 x float]. The lower 128 bits contain4548/// the value of the source vector. The upper 128 bits are set to zero.4549///4550/// \headerfile <x86intrin.h>4551///4552/// This intrinsic has no corresponding instruction.4553///4554/// \param __a4555/// A 128-bit vector of [4 x float].4556/// \returns A 256-bit floating-point vector of [8 x float]. The lower 128 bits4557/// contain the value of the parameter. The upper 128 bits are set to zero.4558static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4559_mm256_zextps128_ps256(__m128 __a) {4560 return __builtin_shufflevector((__v4sf)__a, (__v4sf)_mm_setzero_ps(), 0, 1, 2, 3, 4, 5, 6, 7);4561}4562 4563/// Constructs a 256-bit integer vector from a 128-bit integer vector.4564/// The lower 128 bits contain the value of the source vector. The upper4565/// 128 bits are set to zero.4566///4567/// \headerfile <x86intrin.h>4568///4569/// This intrinsic has no corresponding instruction.4570///4571/// \param __a4572/// A 128-bit integer vector.4573/// \returns A 256-bit integer vector. The lower 128 bits contain the value of4574/// the parameter. The upper 128 bits are set to zero.4575static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4576_mm256_zextsi128_si256(__m128i __a) {4577 return __builtin_shufflevector((__v2di)__a, (__v2di)_mm_setzero_si128(), 0, 1, 2, 3);4578}4579 4580/*4581 Vector insert.4582 We use macros rather than inlines because we only want to accept4583 invocations where the immediate M is a constant expression.4584*/4585/// Constructs a new 256-bit vector of [8 x float] by first duplicating4586/// a 256-bit vector of [8 x float] given in the first parameter, and then4587/// replacing either the upper or the lower 128 bits with the contents of a4588/// 128-bit vector of [4 x float] in the second parameter.4589///4590/// The immediate integer parameter determines between the upper or the lower4591/// 128 bits.4592///4593/// \headerfile <x86intrin.h>4594///4595/// \code4596/// __m256 _mm256_insertf128_ps(__m256 V1, __m128 V2, const int M);4597/// \endcode4598///4599/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4600///4601/// \param V14602/// A 256-bit vector of [8 x float]. This vector is copied to the result4603/// first, and then either the upper or the lower 128 bits of the result will4604/// be replaced by the contents of \a V2.4605/// \param V24606/// A 128-bit vector of [4 x float]. The contents of this parameter are4607/// written to either the upper or the lower 128 bits of the result depending4608/// on the value of parameter \a M.4609/// \param M4610/// An immediate integer. The least significant bit determines how the values4611/// from the two parameters are interleaved: \n4612/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result,4613/// and bits [255:128] of \a V1 are copied to bits [255:128] of the4614/// result. \n4615/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the4616/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the4617/// result.4618/// \returns A 256-bit vector of [8 x float] containing the interleaved values.4619#define _mm256_insertf128_ps(V1, V2, M) \4620 ((__m256)__builtin_ia32_vinsertf128_ps256((__v8sf)(__m256)(V1), \4621 (__v4sf)(__m128)(V2), (int)(M)))4622 4623/// Constructs a new 256-bit vector of [4 x double] by first duplicating4624/// a 256-bit vector of [4 x double] given in the first parameter, and then4625/// replacing either the upper or the lower 128 bits with the contents of a4626/// 128-bit vector of [2 x double] in the second parameter.4627///4628/// The immediate integer parameter determines between the upper or the lower4629/// 128 bits.4630///4631/// \headerfile <x86intrin.h>4632///4633/// \code4634/// __m256d _mm256_insertf128_pd(__m256d V1, __m128d V2, const int M);4635/// \endcode4636///4637/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4638///4639/// \param V14640/// A 256-bit vector of [4 x double]. This vector is copied to the result4641/// first, and then either the upper or the lower 128 bits of the result will4642/// be replaced by the contents of \a V2.4643/// \param V24644/// A 128-bit vector of [2 x double]. The contents of this parameter are4645/// written to either the upper or the lower 128 bits of the result depending4646/// on the value of parameter \a M.4647/// \param M4648/// An immediate integer. The least significant bit determines how the values4649/// from the two parameters are interleaved: \n4650/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result,4651/// and bits [255:128] of \a V1 are copied to bits [255:128] of the4652/// result. \n4653/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the4654/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the4655/// result.4656/// \returns A 256-bit vector of [4 x double] containing the interleaved values.4657#define _mm256_insertf128_pd(V1, V2, M) \4658 ((__m256d)__builtin_ia32_vinsertf128_pd256((__v4df)(__m256d)(V1), \4659 (__v2df)(__m128d)(V2), (int)(M)))4660 4661/// Constructs a new 256-bit integer vector by first duplicating a4662/// 256-bit integer vector given in the first parameter, and then replacing4663/// either the upper or the lower 128 bits with the contents of a 128-bit4664/// integer vector in the second parameter.4665///4666/// The immediate integer parameter determines between the upper or the lower4667/// 128 bits.4668///4669/// \headerfile <x86intrin.h>4670///4671/// \code4672/// __m256i _mm256_insertf128_si256(__m256i V1, __m128i V2, const int M);4673/// \endcode4674///4675/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4676///4677/// \param V14678/// A 256-bit integer vector. This vector is copied to the result first, and4679/// then either the upper or the lower 128 bits of the result will be4680/// replaced by the contents of \a V2.4681/// \param V24682/// A 128-bit integer vector. The contents of this parameter are written to4683/// either the upper or the lower 128 bits of the result depending on the4684/// value of parameter \a M.4685/// \param M4686/// An immediate integer. The least significant bit determines how the values4687/// from the two parameters are interleaved: \n4688/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result,4689/// and bits [255:128] of \a V1 are copied to bits [255:128] of the4690/// result. \n4691/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the4692/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the4693/// result.4694/// \returns A 256-bit integer vector containing the interleaved values.4695#define _mm256_insertf128_si256(V1, V2, M) \4696 ((__m256i)__builtin_ia32_vinsertf128_si256((__v8si)(__m256i)(V1), \4697 (__v4si)(__m128i)(V2), (int)(M)))4698 4699/*4700 Vector extract.4701 We use macros rather than inlines because we only want to accept4702 invocations where the immediate M is a constant expression.4703*/4704/// Extracts either the upper or the lower 128 bits from a 256-bit vector4705/// of [8 x float], as determined by the immediate integer parameter, and4706/// returns the extracted bits as a 128-bit vector of [4 x float].4707///4708/// \headerfile <x86intrin.h>4709///4710/// \code4711/// __m128 _mm256_extractf128_ps(__m256 V, const int M);4712/// \endcode4713///4714/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction.4715///4716/// \param V4717/// A 256-bit vector of [8 x float].4718/// \param M4719/// An immediate integer. The least significant bit determines which bits are4720/// extracted from the first parameter: \n4721/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the4722/// result. \n4723/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result.4724/// \returns A 128-bit vector of [4 x float] containing the extracted bits.4725#define _mm256_extractf128_ps(V, M) \4726 ((__m128)__builtin_ia32_vextractf128_ps256((__v8sf)(__m256)(V), (int)(M)))4727 4728/// Extracts either the upper or the lower 128 bits from a 256-bit vector4729/// of [4 x double], as determined by the immediate integer parameter, and4730/// returns the extracted bits as a 128-bit vector of [2 x double].4731///4732/// \headerfile <x86intrin.h>4733///4734/// \code4735/// __m128d _mm256_extractf128_pd(__m256d V, const int M);4736/// \endcode4737///4738/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction.4739///4740/// \param V4741/// A 256-bit vector of [4 x double].4742/// \param M4743/// An immediate integer. The least significant bit determines which bits are4744/// extracted from the first parameter: \n4745/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the4746/// result. \n4747/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result.4748/// \returns A 128-bit vector of [2 x double] containing the extracted bits.4749#define _mm256_extractf128_pd(V, M) \4750 ((__m128d)__builtin_ia32_vextractf128_pd256((__v4df)(__m256d)(V), (int)(M)))4751 4752/// Extracts either the upper or the lower 128 bits from a 256-bit4753/// integer vector, as determined by the immediate integer parameter, and4754/// returns the extracted bits as a 128-bit integer vector.4755///4756/// \headerfile <x86intrin.h>4757///4758/// \code4759/// __m128i _mm256_extractf128_si256(__m256i V, const int M);4760/// \endcode4761///4762/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction.4763///4764/// \param V4765/// A 256-bit integer vector.4766/// \param M4767/// An immediate integer. The least significant bit determines which bits are4768/// extracted from the first parameter: \n4769/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the4770/// result. \n4771/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result.4772/// \returns A 128-bit integer vector containing the extracted bits.4773#define _mm256_extractf128_si256(V, M) \4774 ((__m128i)__builtin_ia32_vextractf128_si256((__v8si)(__m256i)(V), (int)(M)))4775 4776/// Constructs a 256-bit floating-point vector of [8 x float] by4777/// concatenating two 128-bit floating-point vectors of [4 x float].4778///4779/// \headerfile <x86intrin.h>4780///4781/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4782///4783/// \param __hi4784/// A 128-bit floating-point vector of [4 x float] to be copied to the upper4785/// 128 bits of the result.4786/// \param __lo4787/// A 128-bit floating-point vector of [4 x float] to be copied to the lower4788/// 128 bits of the result.4789/// \returns A 256-bit floating-point vector of [8 x float] containing the4790/// concatenated result.4791static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4792_mm256_set_m128(__m128 __hi, __m128 __lo) {4793 return (__m256) __builtin_shufflevector((__v4sf)__lo, (__v4sf)__hi, 0, 1, 2, 3, 4, 5, 6, 7);4794}4795 4796/// Constructs a 256-bit floating-point vector of [4 x double] by4797/// concatenating two 128-bit floating-point vectors of [2 x double].4798///4799/// \headerfile <x86intrin.h>4800///4801/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4802///4803/// \param __hi4804/// A 128-bit floating-point vector of [2 x double] to be copied to the upper4805/// 128 bits of the result.4806/// \param __lo4807/// A 128-bit floating-point vector of [2 x double] to be copied to the lower4808/// 128 bits of the result.4809/// \returns A 256-bit floating-point vector of [4 x double] containing the4810/// concatenated result.4811static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4812_mm256_set_m128d(__m128d __hi, __m128d __lo) {4813 return (__m256d) __builtin_shufflevector((__v2df)__lo, (__v2df)__hi, 0, 1, 2, 3);4814}4815 4816/// Constructs a 256-bit integer vector by concatenating two 128-bit4817/// integer vectors.4818///4819/// \headerfile <x86intrin.h>4820///4821/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4822///4823/// \param __hi4824/// A 128-bit integer vector to be copied to the upper 128 bits of the4825/// result.4826/// \param __lo4827/// A 128-bit integer vector to be copied to the lower 128 bits of the4828/// result.4829/// \returns A 256-bit integer vector containing the concatenated result.4830static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4831_mm256_set_m128i(__m128i __hi, __m128i __lo) {4832 return (__m256i) __builtin_shufflevector((__v2di)__lo, (__v2di)__hi, 0, 1, 2, 3);4833}4834 4835/// Constructs a 256-bit floating-point vector of [8 x float] by4836/// concatenating two 128-bit floating-point vectors of [4 x float]. This is4837/// similar to _mm256_set_m128, but the order of the input parameters is4838/// swapped.4839///4840/// \headerfile <x86intrin.h>4841///4842/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4843///4844/// \param __lo4845/// A 128-bit floating-point vector of [4 x float] to be copied to the lower4846/// 128 bits of the result.4847/// \param __hi4848/// A 128-bit floating-point vector of [4 x float] to be copied to the upper4849/// 128 bits of the result.4850/// \returns A 256-bit floating-point vector of [8 x float] containing the4851/// concatenated result.4852static __inline __m256 __DEFAULT_FN_ATTRS_CONSTEXPR4853_mm256_setr_m128(__m128 __lo, __m128 __hi) {4854 return _mm256_set_m128(__hi, __lo);4855}4856 4857/// Constructs a 256-bit floating-point vector of [4 x double] by4858/// concatenating two 128-bit floating-point vectors of [2 x double]. This is4859/// similar to _mm256_set_m128d, but the order of the input parameters is4860/// swapped.4861///4862/// \headerfile <x86intrin.h>4863///4864/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4865///4866/// \param __lo4867/// A 128-bit floating-point vector of [2 x double] to be copied to the lower4868/// 128 bits of the result.4869/// \param __hi4870/// A 128-bit floating-point vector of [2 x double] to be copied to the upper4871/// 128 bits of the result.4872/// \returns A 256-bit floating-point vector of [4 x double] containing the4873/// concatenated result.4874static __inline __m256d __DEFAULT_FN_ATTRS_CONSTEXPR4875_mm256_setr_m128d(__m128d __lo, __m128d __hi) {4876 return (__m256d)_mm256_set_m128d(__hi, __lo);4877}4878 4879/// Constructs a 256-bit integer vector by concatenating two 128-bit4880/// integer vectors. This is similar to _mm256_set_m128i, but the order of4881/// the input parameters is swapped.4882///4883/// \headerfile <x86intrin.h>4884///4885/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction.4886///4887/// \param __lo4888/// A 128-bit integer vector to be copied to the lower 128 bits of the4889/// result.4890/// \param __hi4891/// A 128-bit integer vector to be copied to the upper 128 bits of the4892/// result.4893/// \returns A 256-bit integer vector containing the concatenated result.4894static __inline __m256i __DEFAULT_FN_ATTRS_CONSTEXPR4895_mm256_setr_m128i(__m128i __lo, __m128i __hi) {4896 return (__m256i)_mm256_set_m128i(__hi, __lo);4897}4898 4899/* SIMD load ops (unaligned) */4900/// Loads two 128-bit floating-point vectors of [4 x float] from4901/// unaligned memory locations and constructs a 256-bit floating-point vector4902/// of [8 x float] by concatenating the two 128-bit vectors.4903///4904/// \headerfile <x86intrin.h>4905///4906/// This intrinsic corresponds to load instructions followed by the4907/// <c> VINSERTF128 </c> instruction.4908///4909/// \param __addr_hi4910/// A pointer to a 128-bit memory location containing 4 consecutive4911/// single-precision floating-point values. These values are to be copied to4912/// bits[255:128] of the result. The address of the memory location does not4913/// have to be aligned.4914/// \param __addr_lo4915/// A pointer to a 128-bit memory location containing 4 consecutive4916/// single-precision floating-point values. These values are to be copied to4917/// bits[127:0] of the result. The address of the memory location does not4918/// have to be aligned.4919/// \returns A 256-bit floating-point vector of [8 x float] containing the4920/// concatenated result.4921static __inline __m256 __DEFAULT_FN_ATTRS4922_mm256_loadu2_m128(float const *__addr_hi, float const *__addr_lo)4923{4924 return _mm256_set_m128(_mm_loadu_ps(__addr_hi), _mm_loadu_ps(__addr_lo));4925}4926 4927/// Loads two 128-bit floating-point vectors of [2 x double] from4928/// unaligned memory locations and constructs a 256-bit floating-point vector4929/// of [4 x double] by concatenating the two 128-bit vectors.4930///4931/// \headerfile <x86intrin.h>4932///4933/// This intrinsic corresponds to load instructions followed by the4934/// <c> VINSERTF128 </c> instruction.4935///4936/// \param __addr_hi4937/// A pointer to a 128-bit memory location containing two consecutive4938/// double-precision floating-point values. These values are to be copied to4939/// bits[255:128] of the result. The address of the memory location does not4940/// have to be aligned.4941/// \param __addr_lo4942/// A pointer to a 128-bit memory location containing two consecutive4943/// double-precision floating-point values. These values are to be copied to4944/// bits[127:0] of the result. The address of the memory location does not4945/// have to be aligned.4946/// \returns A 256-bit floating-point vector of [4 x double] containing the4947/// concatenated result.4948static __inline __m256d __DEFAULT_FN_ATTRS4949_mm256_loadu2_m128d(double const *__addr_hi, double const *__addr_lo)4950{4951 return _mm256_set_m128d(_mm_loadu_pd(__addr_hi), _mm_loadu_pd(__addr_lo));4952}4953 4954/// Loads two 128-bit integer vectors from unaligned memory locations and4955/// constructs a 256-bit integer vector by concatenating the two 128-bit4956/// vectors.4957///4958/// \headerfile <x86intrin.h>4959///4960/// This intrinsic corresponds to load instructions followed by the4961/// <c> VINSERTF128 </c> instruction.4962///4963/// \param __addr_hi4964/// A pointer to a 128-bit memory location containing a 128-bit integer4965/// vector. This vector is to be copied to bits[255:128] of the result. The4966/// address of the memory location does not have to be aligned.4967/// \param __addr_lo4968/// A pointer to a 128-bit memory location containing a 128-bit integer4969/// vector. This vector is to be copied to bits[127:0] of the result. The4970/// address of the memory location does not have to be aligned.4971/// \returns A 256-bit integer vector containing the concatenated result.4972static __inline __m256i __DEFAULT_FN_ATTRS4973_mm256_loadu2_m128i(__m128i_u const *__addr_hi, __m128i_u const *__addr_lo)4974{4975 return _mm256_set_m128i(_mm_loadu_si128(__addr_hi), _mm_loadu_si128(__addr_lo));4976}4977 4978/* SIMD store ops (unaligned) */4979/// Stores the upper and lower 128 bits of a 256-bit floating-point4980/// vector of [8 x float] into two different unaligned memory locations.4981///4982/// \headerfile <x86intrin.h>4983///4984/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the4985/// store instructions.4986///4987/// \param __addr_hi4988/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be4989/// copied to this memory location. The address of this memory location does4990/// not have to be aligned.4991/// \param __addr_lo4992/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be4993/// copied to this memory location. The address of this memory location does4994/// not have to be aligned.4995/// \param __a4996/// A 256-bit floating-point vector of [8 x float].4997static __inline void __DEFAULT_FN_ATTRS4998_mm256_storeu2_m128(float *__addr_hi, float *__addr_lo, __m256 __a)4999{5000 __m128 __v128;5001 5002 __v128 = _mm256_castps256_ps128(__a);5003 _mm_storeu_ps(__addr_lo, __v128);5004 __v128 = _mm256_extractf128_ps(__a, 1);5005 _mm_storeu_ps(__addr_hi, __v128);5006}5007 5008/// Stores the upper and lower 128 bits of a 256-bit floating-point5009/// vector of [4 x double] into two different unaligned memory locations.5010///5011/// \headerfile <x86intrin.h>5012///5013/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the5014/// store instructions.5015///5016/// \param __addr_hi5017/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be5018/// copied to this memory location. The address of this memory location does5019/// not have to be aligned.5020/// \param __addr_lo5021/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be5022/// copied to this memory location. The address of this memory location does5023/// not have to be aligned.5024/// \param __a5025/// A 256-bit floating-point vector of [4 x double].5026static __inline void __DEFAULT_FN_ATTRS5027_mm256_storeu2_m128d(double *__addr_hi, double *__addr_lo, __m256d __a)5028{5029 __m128d __v128;5030 5031 __v128 = _mm256_castpd256_pd128(__a);5032 _mm_storeu_pd(__addr_lo, __v128);5033 __v128 = _mm256_extractf128_pd(__a, 1);5034 _mm_storeu_pd(__addr_hi, __v128);5035}5036 5037/// Stores the upper and lower 128 bits of a 256-bit integer vector into5038/// two different unaligned memory locations.5039///5040/// \headerfile <x86intrin.h>5041///5042/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the5043/// store instructions.5044///5045/// \param __addr_hi5046/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be5047/// copied to this memory location. The address of this memory location does5048/// not have to be aligned.5049/// \param __addr_lo5050/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be5051/// copied to this memory location. The address of this memory location does5052/// not have to be aligned.5053/// \param __a5054/// A 256-bit integer vector.5055static __inline void __DEFAULT_FN_ATTRS5056_mm256_storeu2_m128i(__m128i_u *__addr_hi, __m128i_u *__addr_lo, __m256i __a)5057{5058 __m128i __v128;5059 5060 __v128 = _mm256_castsi256_si128(__a);5061 _mm_storeu_si128(__addr_lo, __v128);5062 __v128 = _mm256_extractf128_si256(__a, 1);5063 _mm_storeu_si128(__addr_hi, __v128);5064}5065 5066#undef __DEFAULT_FN_ATTRS5067#undef __DEFAULT_FN_ATTRS_CONSTEXPR5068#undef __DEFAULT_FN_ATTRS1285069#undef __DEFAULT_FN_ATTRS128_CONSTEXPR5070 5071#endif /* __AVXINTRIN_H */5072