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1/*===---- f16cintrin.h - F16C intrinsics -----------------------------------===2 *3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4 * See https://llvm.org/LICENSE.txt for license information.5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6 *7 *===-----------------------------------------------------------------------===8 */9 10#if !defined __IMMINTRIN_H11#error "Never use <f16cintrin.h> directly; include <immintrin.h> instead."12#endif13 14#ifndef __F16CINTRIN_H15#define __F16CINTRIN_H16 17/* Define the default attributes for the functions in this file. */18#if defined(__cplusplus) && (__cplusplus >= 201103L)19#define __DEFAULT_FN_ATTRS128 \20 __attribute__((__always_inline__, __nodebug__, __target__("f16c"), \21 __min_vector_width__(128))) constexpr22#define __DEFAULT_FN_ATTRS256 \23 __attribute__((__always_inline__, __nodebug__, __target__("f16c"), \24 __min_vector_width__(256))) constexpr25#else26#define __DEFAULT_FN_ATTRS128 \27 __attribute__((__always_inline__, __nodebug__, __target__("f16c"), \28 __min_vector_width__(128)))29#define __DEFAULT_FN_ATTRS256 \30 __attribute__((__always_inline__, __nodebug__, __target__("f16c"), \31 __min_vector_width__(256)))32#endif33 34/* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,35 * but that's because icc can emulate these without f16c using a library call.36 * Since we don't do that let's leave these in f16cintrin.h.37 */38 39/// Converts a 16-bit half-precision float value into a 32-bit float40/// value.41///42/// \headerfile <x86intrin.h>43///44/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.45///46/// \param __a47/// A 16-bit half-precision float value.48/// \returns The converted 32-bit float value.49static __inline float __DEFAULT_FN_ATTRS12850_cvtsh_ss(unsigned short __a)51{52 return (float)__builtin_bit_cast(__fp16, __a);53}54 55/// Converts a 32-bit single-precision float value to a 16-bit56/// half-precision float value.57///58/// \headerfile <x86intrin.h>59///60/// \code61/// unsigned short _cvtss_sh(float a, const int imm);62/// \endcode63///64/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.65///66/// \param a67/// A 32-bit single-precision float value to be converted to a 16-bit68/// half-precision float value.69/// \param imm70/// An immediate value controlling rounding using bits [2:0]: \n71/// 000: Nearest \n72/// 001: Down \n73/// 010: Up \n74/// 011: Truncate \n75/// 1XX: Use MXCSR.RC for rounding76/// \returns The converted 16-bit half-precision float value.77#define _cvtss_sh(a, imm) __extension__ ({ \78 (unsigned short)(((__v8hi)__builtin_ia32_vcvtps2ph((__v4sf){a, 0, 0, 0}, \79 (imm)))[0]); })80 81/// Converts a 128-bit vector containing 32-bit float values into a82/// 128-bit vector containing 16-bit half-precision float values.83///84/// \headerfile <x86intrin.h>85///86/// \code87/// __m128i _mm_cvtps_ph(__m128 a, const int imm);88/// \endcode89///90/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.91///92/// \param a93/// A 128-bit vector containing 32-bit float values.94/// \param imm95/// An immediate value controlling rounding using bits [2:0]: \n96/// 000: Nearest \n97/// 001: Down \n98/// 010: Up \n99/// 011: Truncate \n100/// 1XX: Use MXCSR.RC for rounding101/// \returns A 128-bit vector containing converted 16-bit half-precision float102/// values. The lower 64 bits are used to store the converted 16-bit103/// half-precision floating-point values.104#define _mm_cvtps_ph(a, imm) \105 ((__m128i)__builtin_ia32_vcvtps2ph((__v4sf)(__m128)(a), (imm)))106 107/// Converts a 128-bit vector containing 16-bit half-precision float108/// values into a 128-bit vector containing 32-bit float values.109///110/// \headerfile <x86intrin.h>111///112/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.113///114/// \param __a115/// A 128-bit vector containing 16-bit half-precision float values. The lower116/// 64 bits are used in the conversion.117/// \returns A 128-bit vector of [4 x float] containing converted float values.118static __inline __m128 __DEFAULT_FN_ATTRS128119_mm_cvtph_ps(__m128i __a)120{121 typedef __fp16 __v4fp16 __attribute__((__vector_size__(8)));122 123 __v4hi __v = __builtin_shufflevector((__v8hi)__a, (__v8hi)__a, 0, 1, 2, 3);124 return (__m128) __builtin_convertvector((__v4fp16)__v, __v4sf);125}126 127/// Converts a 256-bit vector of [8 x float] into a 128-bit vector128/// containing 16-bit half-precision float values.129///130/// \headerfile <x86intrin.h>131///132/// \code133/// __m128i _mm256_cvtps_ph(__m256 a, const int imm);134/// \endcode135///136/// This intrinsic corresponds to the <c> VCVTPS2PH </c> instruction.137///138/// \param a139/// A 256-bit vector containing 32-bit single-precision float values to be140/// converted to 16-bit half-precision float values.141/// \param imm142/// An immediate value controlling rounding using bits [2:0]: \n143/// 000: Nearest \n144/// 001: Down \n145/// 010: Up \n146/// 011: Truncate \n147/// 1XX: Use MXCSR.RC for rounding148/// \returns A 128-bit vector containing the converted 16-bit half-precision149/// float values.150#define _mm256_cvtps_ph(a, imm) \151 ((__m128i)__builtin_ia32_vcvtps2ph256((__v8sf)(__m256)(a), (imm)))152 153/// Converts a 128-bit vector containing 16-bit half-precision float154/// values into a 256-bit vector of [8 x float].155///156/// \headerfile <x86intrin.h>157///158/// This intrinsic corresponds to the <c> VCVTPH2PS </c> instruction.159///160/// \param __a161/// A 128-bit vector containing 16-bit half-precision float values to be162/// converted to 32-bit single-precision float values.163/// \returns A vector of [8 x float] containing the converted 32-bit164/// single-precision float values.165static __inline __m256 __DEFAULT_FN_ATTRS256166_mm256_cvtph_ps(__m128i __a)167{168 typedef __fp16 __v8fp16 __attribute__((__vector_size__(16), __aligned__(16)));169 170 return (__m256) __builtin_convertvector((__v8fp16)__a, __v8sf);171}172 173#undef __DEFAULT_FN_ATTRS128174#undef __DEFAULT_FN_ATTRS256175 176#endif /* __F16CINTRIN_H */177