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1/*===----------------- gfniintrin.h - GFNI intrinsics ----------------------===2 *3 *4 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.5 * See https://llvm.org/LICENSE.txt for license information.6 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception7 *8 *===-----------------------------------------------------------------------===9 */10#ifndef __IMMINTRIN_H11#error "Never use <gfniintrin.h> directly; include <immintrin.h> instead."12#endif13 14#ifndef __GFNIINTRIN_H15#define __GFNIINTRIN_H16 17/* Default attributes for simple form (no masking). */18#define __DEFAULT_FN_ATTRS \19 __attribute__((__always_inline__, __nodebug__, __target__("gfni"), \20 __min_vector_width__(128)))21 22/* Default attributes for YMM unmasked form. */23#define __DEFAULT_FN_ATTRS_Y \24 __attribute__((__always_inline__, __nodebug__, __target__("avx,gfni"), \25 __min_vector_width__(256)))26 27/* Default attributes for VLX masked forms. */28#define __DEFAULT_FN_ATTRS_VL128 \29 __attribute__((__always_inline__, __nodebug__, \30 __target__("avx512bw,avx512vl,gfni"), \31 __min_vector_width__(128)))32#define __DEFAULT_FN_ATTRS_VL256 \33 __attribute__((__always_inline__, __nodebug__, \34 __target__("avx512bw,avx512vl,gfni"), \35 __min_vector_width__(256)))36 37/* Default attributes for ZMM unmasked forms. */38#define __DEFAULT_FN_ATTRS_Z \39 __attribute__((__always_inline__, __nodebug__, __target__("avx512f,gfni"), \40 __min_vector_width__(512)))41/* Default attributes for ZMM masked forms. */42#define __DEFAULT_FN_ATTRS_Z_MASK \43 __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,gfni"), \44 __min_vector_width__(512)))45 46#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) \47 ((__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \48 (__v16qi)(__m128i)(B), \49 (char)(I)))50 51#define _mm_gf2p8affine_epi64_epi8(A, B, I) \52 ((__m128i)__builtin_ia32_vgf2p8affineqb_v16qi((__v16qi)(__m128i)(A), \53 (__v16qi)(__m128i)(B), \54 (char)(I)))55 56static __inline__ __m128i __DEFAULT_FN_ATTRS57_mm_gf2p8mul_epi8(__m128i __A, __m128i __B)58{59 return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi((__v16qi) __A,60 (__v16qi) __B);61}62 63#ifdef __AVXINTRIN_H64#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) \65 ((__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \66 (__v32qi)(__m256i)(B), \67 (char)(I)))68 69#define _mm256_gf2p8affine_epi64_epi8(A, B, I) \70 ((__m256i)__builtin_ia32_vgf2p8affineqb_v32qi((__v32qi)(__m256i)(A), \71 (__v32qi)(__m256i)(B), \72 (char)(I)))73 74static __inline__ __m256i __DEFAULT_FN_ATTRS_Y75_mm256_gf2p8mul_epi8(__m256i __A, __m256i __B)76{77 return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi((__v32qi) __A,78 (__v32qi) __B);79}80#endif /* __AVXINTRIN_H */81 82#ifdef __AVX512BWINTRIN_H83#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) \84 ((__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A), \85 (__v64qi)(__m512i)(B), \86 (char)(I)))87 88#define _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \89 ((__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \90 (__v64qi)_mm512_gf2p8affineinv_epi64_epi8(A, B, I), \91 (__v64qi)(__m512i)(S)))92 93#define _mm512_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \94 _mm512_mask_gf2p8affineinv_epi64_epi8((__m512i)_mm512_setzero_si512(), \95 U, A, B, I)96 97#define _mm512_gf2p8affine_epi64_epi8(A, B, I) \98 ((__m512i)__builtin_ia32_vgf2p8affineqb_v64qi((__v64qi)(__m512i)(A), \99 (__v64qi)(__m512i)(B), \100 (char)(I)))101 102#define _mm512_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \103 ((__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \104 (__v64qi)_mm512_gf2p8affine_epi64_epi8((A), (B), (I)), \105 (__v64qi)(__m512i)(S)))106 107#define _mm512_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \108 _mm512_mask_gf2p8affine_epi64_epi8((__m512i)_mm512_setzero_si512(), \109 U, A, B, I)110 111static __inline__ __m512i __DEFAULT_FN_ATTRS_Z112_mm512_gf2p8mul_epi8(__m512i __A, __m512i __B)113{114 return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi((__v64qi) __A,115 (__v64qi) __B);116}117 118static __inline__ __m512i __DEFAULT_FN_ATTRS_Z_MASK119_mm512_mask_gf2p8mul_epi8(__m512i __S, __mmask64 __U, __m512i __A, __m512i __B)120{121 return (__m512i) __builtin_ia32_selectb_512(__U,122 (__v64qi) _mm512_gf2p8mul_epi8(__A, __B),123 (__v64qi) __S);124}125 126static __inline__ __m512i __DEFAULT_FN_ATTRS_Z_MASK127_mm512_maskz_gf2p8mul_epi8(__mmask64 __U, __m512i __A, __m512i __B)128{129 return _mm512_mask_gf2p8mul_epi8((__m512i)_mm512_setzero_si512(),130 __U, __A, __B);131}132#endif /* __AVX512BWINTRIN_H */133 134#ifdef __AVX512VLBWINTRIN_H135#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \136 ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \137 (__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I), \138 (__v16qi)(__m128i)(S)))139 140#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \141 _mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(), \142 U, A, B, I)143 144#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) \145 ((__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \146 (__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I), \147 (__v32qi)(__m256i)(S)))148 149#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) \150 _mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \151 U, A, B, I)152 153#define _mm_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \154 ((__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \155 (__v16qi)_mm_gf2p8affine_epi64_epi8(A, B, I), \156 (__v16qi)(__m128i)(S)))157 158#define _mm_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \159 _mm_mask_gf2p8affine_epi64_epi8((__m128i)_mm_setzero_si128(), U, A, B, I)160 161#define _mm256_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) \162 ((__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \163 (__v32qi)_mm256_gf2p8affine_epi64_epi8(A, B, I), \164 (__v32qi)(__m256i)(S)))165 166#define _mm256_maskz_gf2p8affine_epi64_epi8(U, A, B, I) \167 _mm256_mask_gf2p8affine_epi64_epi8((__m256i)_mm256_setzero_si256(), \168 U, A, B, I)169 170static __inline__ __m128i __DEFAULT_FN_ATTRS_VL128171_mm_mask_gf2p8mul_epi8(__m128i __S, __mmask16 __U, __m128i __A, __m128i __B)172{173 return (__m128i) __builtin_ia32_selectb_128(__U,174 (__v16qi) _mm_gf2p8mul_epi8(__A, __B),175 (__v16qi) __S);176}177 178static __inline__ __m128i __DEFAULT_FN_ATTRS_VL128179_mm_maskz_gf2p8mul_epi8(__mmask16 __U, __m128i __A, __m128i __B)180{181 return _mm_mask_gf2p8mul_epi8((__m128i)_mm_setzero_si128(),182 __U, __A, __B);183}184 185static __inline__ __m256i __DEFAULT_FN_ATTRS_VL256186_mm256_mask_gf2p8mul_epi8(__m256i __S, __mmask32 __U, __m256i __A, __m256i __B)187{188 return (__m256i) __builtin_ia32_selectb_256(__U,189 (__v32qi) _mm256_gf2p8mul_epi8(__A, __B),190 (__v32qi) __S);191}192 193static __inline__ __m256i __DEFAULT_FN_ATTRS_VL256194_mm256_maskz_gf2p8mul_epi8(__mmask32 __U, __m256i __A, __m256i __B)195{196 return _mm256_mask_gf2p8mul_epi8((__m256i)_mm256_setzero_si256(),197 __U, __A, __B);198}199#endif /* __AVX512VLBWINTRIN_H */200 201#undef __DEFAULT_FN_ATTRS202#undef __DEFAULT_FN_ATTRS_Y203#undef __DEFAULT_FN_ATTRS_Z204#undef __DEFAULT_FN_ATTRS_VL128205#undef __DEFAULT_FN_ATTRS_VL256206 207#endif /* __GFNIINTRIN_H */208 209