6004 lines · c
1//===----------------------------------------------------------------------===//2//3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.4// See https://llvm.org/LICENSE.txt for license information.5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception6//7//===----------------------------------------------------------------------===//8// Automatically generated file, do not edit!9//===----------------------------------------------------------------------===//10 11 12#ifndef _HVX_HEXAGON_PROTOS_H_13#define _HVX_HEXAGON_PROTOS_H_ 114 15#ifdef __HVX__16#if __HVX_LENGTH__ == 12817#define __BUILTIN_VECTOR_WRAP(a) a ## _128B18#else19#define __BUILTIN_VECTOR_WRAP(a) a20#endif21 22#if __HVX_ARCH__ >= 6023/* ==========================================================================24 Assembly Syntax: Rd32=vextract(Vu32,Rs32)25 C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)26 Instruction Type: LD27 Execution Slots: SLOT028 ========================================================================== */29 30#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)31#endif /* __HEXAGON_ARCH___ >= 60 */32 33#if __HVX_ARCH__ >= 6034/* ==========================================================================35 Assembly Syntax: Vd32=hi(Vss32)36 C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)37 Instruction Type: CVI_VA38 Execution Slots: SLOT012339 ========================================================================== */40 41#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)42#endif /* __HEXAGON_ARCH___ >= 60 */43 44#if __HVX_ARCH__ >= 6045/* ==========================================================================46 Assembly Syntax: Vd32=lo(Vss32)47 C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)48 Instruction Type: CVI_VA49 Execution Slots: SLOT012350 ========================================================================== */51 52#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)53#endif /* __HEXAGON_ARCH___ >= 60 */54 55#if __HVX_ARCH__ >= 6056/* ==========================================================================57 Assembly Syntax: Vd32=vsplat(Rt32)58 C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)59 Instruction Type: CVI_VX_LATE60 Execution Slots: SLOT2361 ========================================================================== */62 63#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)64#endif /* __HEXAGON_ARCH___ >= 60 */65 66#if __HVX_ARCH__ >= 6067/* ==========================================================================68 Assembly Syntax: Qd4=and(Qs4,Qt4)69 C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)70 Instruction Type: CVI_VA_DV71 Execution Slots: SLOT012372 ========================================================================== */73 74#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)75#endif /* __HEXAGON_ARCH___ >= 60 */76 77#if __HVX_ARCH__ >= 6078/* ==========================================================================79 Assembly Syntax: Qd4=and(Qs4,!Qt4)80 C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)81 Instruction Type: CVI_VA_DV82 Execution Slots: SLOT012383 ========================================================================== */84 85#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)86#endif /* __HEXAGON_ARCH___ >= 60 */87 88#if __HVX_ARCH__ >= 6089/* ==========================================================================90 Assembly Syntax: Qd4=not(Qs4)91 C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)92 Instruction Type: CVI_VA93 Execution Slots: SLOT012394 ========================================================================== */95 96#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)97#endif /* __HEXAGON_ARCH___ >= 60 */98 99#if __HVX_ARCH__ >= 60100/* ==========================================================================101 Assembly Syntax: Qd4=or(Qs4,Qt4)102 C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)103 Instruction Type: CVI_VA_DV104 Execution Slots: SLOT0123105 ========================================================================== */106 107#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)108#endif /* __HEXAGON_ARCH___ >= 60 */109 110#if __HVX_ARCH__ >= 60111/* ==========================================================================112 Assembly Syntax: Qd4=or(Qs4,!Qt4)113 C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)114 Instruction Type: CVI_VA_DV115 Execution Slots: SLOT0123116 ========================================================================== */117 118#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)119#endif /* __HEXAGON_ARCH___ >= 60 */120 121#if __HVX_ARCH__ >= 60122/* ==========================================================================123 Assembly Syntax: Qd4=vsetq(Rt32)124 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)125 Instruction Type: CVI_VP126 Execution Slots: SLOT0123127 ========================================================================== */128 129#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)130#endif /* __HEXAGON_ARCH___ >= 60 */131 132#if __HVX_ARCH__ >= 60133/* ==========================================================================134 Assembly Syntax: Qd4=xor(Qs4,Qt4)135 C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)136 Instruction Type: CVI_VA_DV137 Execution Slots: SLOT0123138 ========================================================================== */139 140#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)141#endif /* __HEXAGON_ARCH___ >= 60 */142 143#if __HVX_ARCH__ >= 60144/* ==========================================================================145 Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32146 C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)147 Instruction Type: CVI_VM_ST148 Execution Slots: SLOT0149 ========================================================================== */150 151#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)152#endif /* __HEXAGON_ARCH___ >= 60 */153 154#if __HVX_ARCH__ >= 60155/* ==========================================================================156 Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32157 C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)158 Instruction Type: CVI_VM_ST159 Execution Slots: SLOT0160 ========================================================================== */161 162#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)163#endif /* __HEXAGON_ARCH___ >= 60 */164 165#if __HVX_ARCH__ >= 60166/* ==========================================================================167 Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32168 C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)169 Instruction Type: CVI_VM_ST170 Execution Slots: SLOT0171 ========================================================================== */172 173#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)174#endif /* __HEXAGON_ARCH___ >= 60 */175 176#if __HVX_ARCH__ >= 60177/* ==========================================================================178 Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32179 C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)180 Instruction Type: CVI_VM_ST181 Execution Slots: SLOT0182 ========================================================================== */183 184#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)185#endif /* __HEXAGON_ARCH___ >= 60 */186 187#if __HVX_ARCH__ >= 60188/* ==========================================================================189 Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h)190 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)191 Instruction Type: CVI_VX192 Execution Slots: SLOT23193 ========================================================================== */194 195#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)196#endif /* __HEXAGON_ARCH___ >= 60 */197 198#if __HVX_ARCH__ >= 60199/* ==========================================================================200 Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)201 C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)202 Instruction Type: CVI_VX203 Execution Slots: SLOT23204 ========================================================================== */205 206#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)207#endif /* __HEXAGON_ARCH___ >= 60 */208 209#if __HVX_ARCH__ >= 60210/* ==========================================================================211 Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)212 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)213 Instruction Type: CVI_VX214 Execution Slots: SLOT23215 ========================================================================== */216 217#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)218#endif /* __HEXAGON_ARCH___ >= 60 */219 220#if __HVX_ARCH__ >= 60221/* ==========================================================================222 Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w)223 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)224 Instruction Type: CVI_VX225 Execution Slots: SLOT23226 ========================================================================== */227 228#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)229#endif /* __HEXAGON_ARCH___ >= 60 */230 231#if __HVX_ARCH__ >= 60232/* ==========================================================================233 Assembly Syntax: Vd32.h=vabs(Vu32.h)234 C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)235 Instruction Type: CVI_VA236 Execution Slots: SLOT0123237 ========================================================================== */238 239#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)240#endif /* __HEXAGON_ARCH___ >= 60 */241 242#if __HVX_ARCH__ >= 60243/* ==========================================================================244 Assembly Syntax: Vd32.h=vabs(Vu32.h):sat245 C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)246 Instruction Type: CVI_VA247 Execution Slots: SLOT0123248 ========================================================================== */249 250#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)251#endif /* __HEXAGON_ARCH___ >= 60 */252 253#if __HVX_ARCH__ >= 60254/* ==========================================================================255 Assembly Syntax: Vd32.w=vabs(Vu32.w)256 C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)257 Instruction Type: CVI_VA258 Execution Slots: SLOT0123259 ========================================================================== */260 261#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)262#endif /* __HEXAGON_ARCH___ >= 60 */263 264#if __HVX_ARCH__ >= 60265/* ==========================================================================266 Assembly Syntax: Vd32.w=vabs(Vu32.w):sat267 C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)268 Instruction Type: CVI_VA269 Execution Slots: SLOT0123270 ========================================================================== */271 272#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)273#endif /* __HEXAGON_ARCH___ >= 60 */274 275#if __HVX_ARCH__ >= 60276/* ==========================================================================277 Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b)278 C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)279 Instruction Type: CVI_VA280 Execution Slots: SLOT0123281 ========================================================================== */282 283#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)284#endif /* __HEXAGON_ARCH___ >= 60 */285 286#if __HVX_ARCH__ >= 60287/* ==========================================================================288 Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b)289 C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)290 Instruction Type: CVI_VA_DV291 Execution Slots: SLOT0123292 ========================================================================== */293 294#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)295#endif /* __HEXAGON_ARCH___ >= 60 */296 297#if __HVX_ARCH__ >= 60298/* ==========================================================================299 Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b300 C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)301 Instruction Type: CVI_VA302 Execution Slots: SLOT0123303 ========================================================================== */304 305#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)306#endif /* __HEXAGON_ARCH___ >= 60 */307 308#if __HVX_ARCH__ >= 60309/* ==========================================================================310 Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b311 C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)312 Instruction Type: CVI_VA313 Execution Slots: SLOT0123314 ========================================================================== */315 316#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)317#endif /* __HEXAGON_ARCH___ >= 60 */318 319#if __HVX_ARCH__ >= 60320/* ==========================================================================321 Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h)322 C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)323 Instruction Type: CVI_VA324 Execution Slots: SLOT0123325 ========================================================================== */326 327#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)328#endif /* __HEXAGON_ARCH___ >= 60 */329 330#if __HVX_ARCH__ >= 60331/* ==========================================================================332 Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h)333 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)334 Instruction Type: CVI_VA_DV335 Execution Slots: SLOT0123336 ========================================================================== */337 338#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)339#endif /* __HEXAGON_ARCH___ >= 60 */340 341#if __HVX_ARCH__ >= 60342/* ==========================================================================343 Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h344 C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)345 Instruction Type: CVI_VA346 Execution Slots: SLOT0123347 ========================================================================== */348 349#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)350#endif /* __HEXAGON_ARCH___ >= 60 */351 352#if __HVX_ARCH__ >= 60353/* ==========================================================================354 Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h355 C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)356 Instruction Type: CVI_VA357 Execution Slots: SLOT0123358 ========================================================================== */359 360#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)361#endif /* __HEXAGON_ARCH___ >= 60 */362 363#if __HVX_ARCH__ >= 60364/* ==========================================================================365 Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat366 C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)367 Instruction Type: CVI_VA368 Execution Slots: SLOT0123369 ========================================================================== */370 371#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)372#endif /* __HEXAGON_ARCH___ >= 60 */373 374#if __HVX_ARCH__ >= 60375/* ==========================================================================376 Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat377 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)378 Instruction Type: CVI_VA_DV379 Execution Slots: SLOT0123380 ========================================================================== */381 382#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)383#endif /* __HEXAGON_ARCH___ >= 60 */384 385#if __HVX_ARCH__ >= 60386/* ==========================================================================387 Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h)388 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)389 Instruction Type: CVI_VX_DV390 Execution Slots: SLOT23391 ========================================================================== */392 393#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)394#endif /* __HEXAGON_ARCH___ >= 60 */395 396#if __HVX_ARCH__ >= 60397/* ==========================================================================398 Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub)399 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)400 Instruction Type: CVI_VX_DV401 Execution Slots: SLOT23402 ========================================================================== */403 404#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)405#endif /* __HEXAGON_ARCH___ >= 60 */406 407#if __HVX_ARCH__ >= 60408/* ==========================================================================409 Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat410 C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)411 Instruction Type: CVI_VA412 Execution Slots: SLOT0123413 ========================================================================== */414 415#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv)416#endif /* __HEXAGON_ARCH___ >= 60 */417 418#if __HVX_ARCH__ >= 60419/* ==========================================================================420 Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat421 C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)422 Instruction Type: CVI_VA_DV423 Execution Slots: SLOT0123424 ========================================================================== */425 426#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv)427#endif /* __HEXAGON_ARCH___ >= 60 */428 429#if __HVX_ARCH__ >= 60430/* ==========================================================================431 Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat432 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)433 Instruction Type: CVI_VA434 Execution Slots: SLOT0123435 ========================================================================== */436 437#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv)438#endif /* __HEXAGON_ARCH___ >= 60 */439 440#if __HVX_ARCH__ >= 60441/* ==========================================================================442 Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat443 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)444 Instruction Type: CVI_VA_DV445 Execution Slots: SLOT0123446 ========================================================================== */447 448#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv)449#endif /* __HEXAGON_ARCH___ >= 60 */450 451#if __HVX_ARCH__ >= 60452/* ==========================================================================453 Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh)454 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)455 Instruction Type: CVI_VX_DV456 Execution Slots: SLOT23457 ========================================================================== */458 459#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv)460#endif /* __HEXAGON_ARCH___ >= 60 */461 462#if __HVX_ARCH__ >= 60463/* ==========================================================================464 Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w)465 C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv)466 Instruction Type: CVI_VA467 Execution Slots: SLOT0123468 ========================================================================== */469 470#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv)471#endif /* __HEXAGON_ARCH___ >= 60 */472 473#if __HVX_ARCH__ >= 60474/* ==========================================================================475 Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w)476 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)477 Instruction Type: CVI_VA_DV478 Execution Slots: SLOT0123479 ========================================================================== */480 481#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv)482#endif /* __HEXAGON_ARCH___ >= 60 */483 484#if __HVX_ARCH__ >= 60485/* ==========================================================================486 Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w487 C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)488 Instruction Type: CVI_VA489 Execution Slots: SLOT0123490 ========================================================================== */491 492#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)493#endif /* __HEXAGON_ARCH___ >= 60 */494 495#if __HVX_ARCH__ >= 60496/* ==========================================================================497 Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w498 C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)499 Instruction Type: CVI_VA500 Execution Slots: SLOT0123501 ========================================================================== */502 503#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)504#endif /* __HEXAGON_ARCH___ >= 60 */505 506#if __HVX_ARCH__ >= 60507/* ==========================================================================508 Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat509 C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)510 Instruction Type: CVI_VA511 Execution Slots: SLOT0123512 ========================================================================== */513 514#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv)515#endif /* __HEXAGON_ARCH___ >= 60 */516 517#if __HVX_ARCH__ >= 60518/* ==========================================================================519 Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat520 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)521 Instruction Type: CVI_VA_DV522 Execution Slots: SLOT0123523 ========================================================================== */524 525#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv)526#endif /* __HEXAGON_ARCH___ >= 60 */527 528#if __HVX_ARCH__ >= 60529/* ==========================================================================530 Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8)531 C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)532 Instruction Type: CVI_VP533 Execution Slots: SLOT0123534 ========================================================================== */535 536#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt)537#endif /* __HEXAGON_ARCH___ >= 60 */538 539#if __HVX_ARCH__ >= 60540/* ==========================================================================541 Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3)542 C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)543 Instruction Type: CVI_VP544 Execution Slots: SLOT0123545 ========================================================================== */546 547#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3)548#endif /* __HEXAGON_ARCH___ >= 60 */549 550#if __HVX_ARCH__ >= 60551/* ==========================================================================552 Assembly Syntax: Vd32=vand(Vu32,Vv32)553 C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv)554 Instruction Type: CVI_VA555 Execution Slots: SLOT0123556 ========================================================================== */557 558#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv)559#endif /* __HEXAGON_ARCH___ >= 60 */560 561#if __HVX_ARCH__ >= 60562/* ==========================================================================563 Assembly Syntax: Vd32=vand(Qu4,Rt32)564 C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt)565 Instruction Type: CVI_VX_LATE566 Execution Slots: SLOT23567 ========================================================================== */568 569#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)570#endif /* __HEXAGON_ARCH___ >= 60 */571 572#if __HVX_ARCH__ >= 60573/* ==========================================================================574 Assembly Syntax: Vx32|=vand(Qu4,Rt32)575 C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)576 Instruction Type: CVI_VX_LATE577 Execution Slots: SLOT23578 ========================================================================== */579 580#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)581#endif /* __HEXAGON_ARCH___ >= 60 */582 583#if __HVX_ARCH__ >= 60584/* ==========================================================================585 Assembly Syntax: Qd4=vand(Vu32,Rt32)586 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt)587 Instruction Type: CVI_VX_LATE588 Execution Slots: SLOT23589 ========================================================================== */590 591#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1)592#endif /* __HEXAGON_ARCH___ >= 60 */593 594#if __HVX_ARCH__ >= 60595/* ==========================================================================596 Assembly Syntax: Qx4|=vand(Vu32,Rt32)597 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt)598 Instruction Type: CVI_VX_LATE599 Execution Slots: SLOT23600 ========================================================================== */601 602#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1)603#endif /* __HEXAGON_ARCH___ >= 60 */604 605#if __HVX_ARCH__ >= 60606/* ==========================================================================607 Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32)608 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt)609 Instruction Type: CVI_VS610 Execution Slots: SLOT0123611 ========================================================================== */612 613#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt)614#endif /* __HEXAGON_ARCH___ >= 60 */615 616#if __HVX_ARCH__ >= 60617/* ==========================================================================618 Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h)619 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv)620 Instruction Type: CVI_VS621 Execution Slots: SLOT0123622 ========================================================================== */623 624#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv)625#endif /* __HEXAGON_ARCH___ >= 60 */626 627#if __HVX_ARCH__ >= 60628/* ==========================================================================629 Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32)630 C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt)631 Instruction Type: CVI_VS632 Execution Slots: SLOT0123633 ========================================================================== */634 635#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt)636#endif /* __HEXAGON_ARCH___ >= 60 */637 638#if __HVX_ARCH__ >= 60639/* ==========================================================================640 Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32)641 C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)642 Instruction Type: CVI_VS643 Execution Slots: SLOT0123644 ========================================================================== */645 646#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt)647#endif /* __HEXAGON_ARCH___ >= 60 */648 649#if __HVX_ARCH__ >= 60650/* ==========================================================================651 Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w)652 C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv)653 Instruction Type: CVI_VS654 Execution Slots: SLOT0123655 ========================================================================== */656 657#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv)658#endif /* __HEXAGON_ARCH___ >= 60 */659 660#if __HVX_ARCH__ >= 60661/* ==========================================================================662 Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32)663 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt)664 Instruction Type: CVI_VS665 Execution Slots: SLOT0123666 ========================================================================== */667 668#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt)669#endif /* __HEXAGON_ARCH___ >= 60 */670 671#if __HVX_ARCH__ >= 60672/* ==========================================================================673 Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat674 C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)675 Instruction Type: CVI_VS676 Execution Slots: SLOT0123677 ========================================================================== */678 679#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt)680#endif /* __HEXAGON_ARCH___ >= 60 */681 682#if __HVX_ARCH__ >= 60683/* ==========================================================================684 Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat685 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)686 Instruction Type: CVI_VS687 Execution Slots: SLOT0123688 ========================================================================== */689 690#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt)691#endif /* __HEXAGON_ARCH___ >= 60 */692 693#if __HVX_ARCH__ >= 60694/* ==========================================================================695 Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat696 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)697 Instruction Type: CVI_VS698 Execution Slots: SLOT0123699 ========================================================================== */700 701#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt)702#endif /* __HEXAGON_ARCH___ >= 60 */703 704#if __HVX_ARCH__ >= 60705/* ==========================================================================706 Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h)707 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv)708 Instruction Type: CVI_VS709 Execution Slots: SLOT0123710 ========================================================================== */711 712#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv)713#endif /* __HEXAGON_ARCH___ >= 60 */714 715#if __HVX_ARCH__ >= 60716/* ==========================================================================717 Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32)718 C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt)719 Instruction Type: CVI_VS720 Execution Slots: SLOT0123721 ========================================================================== */722 723#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt)724#endif /* __HEXAGON_ARCH___ >= 60 */725 726#if __HVX_ARCH__ >= 60727/* ==========================================================================728 Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32)729 C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)730 Instruction Type: CVI_VS731 Execution Slots: SLOT0123732 ========================================================================== */733 734#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt)735#endif /* __HEXAGON_ARCH___ >= 60 */736 737#if __HVX_ARCH__ >= 60738/* ==========================================================================739 Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)740 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)741 Instruction Type: CVI_VS742 Execution Slots: SLOT0123743 ========================================================================== */744 745#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt)746#endif /* __HEXAGON_ARCH___ >= 60 */747 748#if __HVX_ARCH__ >= 60749/* ==========================================================================750 Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat751 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)752 Instruction Type: CVI_VS753 Execution Slots: SLOT0123754 ========================================================================== */755 756#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt)757#endif /* __HEXAGON_ARCH___ >= 60 */758 759#if __HVX_ARCH__ >= 60760/* ==========================================================================761 Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat762 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)763 Instruction Type: CVI_VS764 Execution Slots: SLOT0123765 ========================================================================== */766 767#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt)768#endif /* __HEXAGON_ARCH___ >= 60 */769 770#if __HVX_ARCH__ >= 60771/* ==========================================================================772 Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat773 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)774 Instruction Type: CVI_VS775 Execution Slots: SLOT0123776 ========================================================================== */777 778#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt)779#endif /* __HEXAGON_ARCH___ >= 60 */780 781#if __HVX_ARCH__ >= 60782/* ==========================================================================783 Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w)784 C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv)785 Instruction Type: CVI_VS786 Execution Slots: SLOT0123787 ========================================================================== */788 789#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv)790#endif /* __HEXAGON_ARCH___ >= 60 */791 792#if __HVX_ARCH__ >= 60793/* ==========================================================================794 Assembly Syntax: Vd32=Vu32795 C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu)796 Instruction Type: CVI_VA797 Execution Slots: SLOT0123798 ========================================================================== */799 800#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu)801#endif /* __HEXAGON_ARCH___ >= 60 */802 803#if __HVX_ARCH__ >= 60804/* ==========================================================================805 Assembly Syntax: Vdd32=Vuu32806 C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu)807 Instruction Type: CVI_VA_DV808 Execution Slots: SLOT0123809 ========================================================================== */810 811#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu)812#endif /* __HEXAGON_ARCH___ >= 60 */813 814#if __HVX_ARCH__ >= 60815/* ==========================================================================816 Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h)817 C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)818 Instruction Type: CVI_VA819 Execution Slots: SLOT0123820 ========================================================================== */821 822#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv)823#endif /* __HEXAGON_ARCH___ >= 60 */824 825#if __HVX_ARCH__ >= 60826/* ==========================================================================827 Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd828 C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv)829 Instruction Type: CVI_VA830 Execution Slots: SLOT0123831 ========================================================================== */832 833#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv)834#endif /* __HEXAGON_ARCH___ >= 60 */835 836#if __HVX_ARCH__ >= 60837/* ==========================================================================838 Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub)839 C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)840 Instruction Type: CVI_VA841 Execution Slots: SLOT0123842 ========================================================================== */843 844#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv)845#endif /* __HEXAGON_ARCH___ >= 60 */846 847#if __HVX_ARCH__ >= 60848/* ==========================================================================849 Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd850 C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv)851 Instruction Type: CVI_VA852 Execution Slots: SLOT0123853 ========================================================================== */854 855#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv)856#endif /* __HEXAGON_ARCH___ >= 60 */857 858#if __HVX_ARCH__ >= 60859/* ==========================================================================860 Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh)861 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)862 Instruction Type: CVI_VA863 Execution Slots: SLOT0123864 ========================================================================== */865 866#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv)867#endif /* __HEXAGON_ARCH___ >= 60 */868 869#if __HVX_ARCH__ >= 60870/* ==========================================================================871 Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd872 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv)873 Instruction Type: CVI_VA874 Execution Slots: SLOT0123875 ========================================================================== */876 877#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv)878#endif /* __HEXAGON_ARCH___ >= 60 */879 880#if __HVX_ARCH__ >= 60881/* ==========================================================================882 Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w)883 C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)884 Instruction Type: CVI_VA885 Execution Slots: SLOT0123886 ========================================================================== */887 888#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv)889#endif /* __HEXAGON_ARCH___ >= 60 */890 891#if __HVX_ARCH__ >= 60892/* ==========================================================================893 Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd894 C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv)895 Instruction Type: CVI_VA896 Execution Slots: SLOT0123897 ========================================================================== */898 899#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv)900#endif /* __HEXAGON_ARCH___ >= 60 */901 902#if __HVX_ARCH__ >= 60903/* ==========================================================================904 Assembly Syntax: Vd32.uh=vcl0(Vu32.uh)905 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu)906 Instruction Type: CVI_VS907 Execution Slots: SLOT0123908 ========================================================================== */909 910#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu)911#endif /* __HEXAGON_ARCH___ >= 60 */912 913#if __HVX_ARCH__ >= 60914/* ==========================================================================915 Assembly Syntax: Vd32.uw=vcl0(Vu32.uw)916 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu)917 Instruction Type: CVI_VS918 Execution Slots: SLOT0123919 ========================================================================== */920 921#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu)922#endif /* __HEXAGON_ARCH___ >= 60 */923 924#if __HVX_ARCH__ >= 60925/* ==========================================================================926 Assembly Syntax: Vdd32=vcombine(Vu32,Vv32)927 C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv)928 Instruction Type: CVI_VA_DV929 Execution Slots: SLOT0123930 ========================================================================== */931 932#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv)933#endif /* __HEXAGON_ARCH___ >= 60 */934 935#if __HVX_ARCH__ >= 60936/* ==========================================================================937 Assembly Syntax: Vd32=#0938 C Intrinsic Prototype: HVX_Vector Q6_V_vzero()939 Instruction Type: CVI_VA940 Execution Slots: SLOT0123941 ========================================================================== */942 943#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)()944#endif /* __HEXAGON_ARCH___ >= 60 */945 946#if __HVX_ARCH__ >= 60947/* ==========================================================================948 Assembly Syntax: Vd32.b=vdeal(Vu32.b)949 C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu)950 Instruction Type: CVI_VP951 Execution Slots: SLOT0123952 ========================================================================== */953 954#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu)955#endif /* __HEXAGON_ARCH___ >= 60 */956 957#if __HVX_ARCH__ >= 60958/* ==========================================================================959 Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b)960 C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv)961 Instruction Type: CVI_VP962 Execution Slots: SLOT0123963 ========================================================================== */964 965#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv)966#endif /* __HEXAGON_ARCH___ >= 60 */967 968#if __HVX_ARCH__ >= 60969/* ==========================================================================970 Assembly Syntax: Vd32.h=vdeal(Vu32.h)971 C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu)972 Instruction Type: CVI_VP973 Execution Slots: SLOT0123974 ========================================================================== */975 976#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu)977#endif /* __HEXAGON_ARCH___ >= 60 */978 979#if __HVX_ARCH__ >= 60980/* ==========================================================================981 Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8)982 C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)983 Instruction Type: CVI_VP_VS984 Execution Slots: SLOT0123985 ========================================================================== */986 987#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt)988#endif /* __HEXAGON_ARCH___ >= 60 */989 990#if __HVX_ARCH__ >= 60991/* ==========================================================================992 Assembly Syntax: Vd32=vdelta(Vu32,Vv32)993 C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv)994 Instruction Type: CVI_VP995 Execution Slots: SLOT0123996 ========================================================================== */997 998#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv)999#endif /* __HEXAGON_ARCH___ >= 60 */1000 1001#if __HVX_ARCH__ >= 601002/* ==========================================================================1003 Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b)1004 C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt)1005 Instruction Type: CVI_VX1006 Execution Slots: SLOT231007 ========================================================================== */1008 1009#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt)1010#endif /* __HEXAGON_ARCH___ >= 60 */1011 1012#if __HVX_ARCH__ >= 601013/* ==========================================================================1014 Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b)1015 C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)1016 Instruction Type: CVI_VX1017 Execution Slots: SLOT231018 ========================================================================== */1019 1020#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt)1021#endif /* __HEXAGON_ARCH___ >= 60 */1022 1023#if __HVX_ARCH__ >= 601024/* ==========================================================================1025 Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)1026 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)1027 Instruction Type: CVI_VX_DV1028 Execution Slots: SLOT231029 ========================================================================== */1030 1031#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt)1032#endif /* __HEXAGON_ARCH___ >= 60 */1033 1034#if __HVX_ARCH__ >= 601035/* ==========================================================================1036 Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)1037 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)1038 Instruction Type: CVI_VX_DV1039 Execution Slots: SLOT231040 ========================================================================== */1041 1042#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt)1043#endif /* __HEXAGON_ARCH___ >= 60 */1044 1045#if __HVX_ARCH__ >= 601046/* ==========================================================================1047 Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b)1048 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt)1049 Instruction Type: CVI_VX1050 Execution Slots: SLOT231051 ========================================================================== */1052 1053#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt)1054#endif /* __HEXAGON_ARCH___ >= 60 */1055 1056#if __HVX_ARCH__ >= 601057/* ==========================================================================1058 Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b)1059 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)1060 Instruction Type: CVI_VX1061 Execution Slots: SLOT231062 ========================================================================== */1063 1064#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt)1065#endif /* __HEXAGON_ARCH___ >= 60 */1066 1067#if __HVX_ARCH__ >= 601068/* ==========================================================================1069 Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b)1070 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)1071 Instruction Type: CVI_VX_DV1072 Execution Slots: SLOT231073 ========================================================================== */1074 1075#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt)1076#endif /* __HEXAGON_ARCH___ >= 60 */1077 1078#if __HVX_ARCH__ >= 601079/* ==========================================================================1080 Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)1081 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)1082 Instruction Type: CVI_VX_DV1083 Execution Slots: SLOT231084 ========================================================================== */1085 1086#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt)1087#endif /* __HEXAGON_ARCH___ >= 60 */1088 1089#if __HVX_ARCH__ >= 601090/* ==========================================================================1091 Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat1092 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt)1093 Instruction Type: CVI_VX_DV1094 Execution Slots: SLOT231095 ========================================================================== */1096 1097#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt)1098#endif /* __HEXAGON_ARCH___ >= 60 */1099 1100#if __HVX_ARCH__ >= 601101/* ==========================================================================1102 Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat1103 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)1104 Instruction Type: CVI_VX_DV1105 Execution Slots: SLOT231106 ========================================================================== */1107 1108#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt)1109#endif /* __HEXAGON_ARCH___ >= 60 */1110 1111#if __HVX_ARCH__ >= 601112/* ==========================================================================1113 Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat1114 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt)1115 Instruction Type: CVI_VX1116 Execution Slots: SLOT231117 ========================================================================== */1118 1119#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt)1120#endif /* __HEXAGON_ARCH___ >= 60 */1121 1122#if __HVX_ARCH__ >= 601123/* ==========================================================================1124 Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat1125 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)1126 Instruction Type: CVI_VX1127 Execution Slots: SLOT231128 ========================================================================== */1129 1130#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt)1131#endif /* __HEXAGON_ARCH___ >= 60 */1132 1133#if __HVX_ARCH__ >= 601134/* ==========================================================================1135 Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat1136 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt)1137 Instruction Type: CVI_VX_DV1138 Execution Slots: SLOT231139 ========================================================================== */1140 1141#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt)1142#endif /* __HEXAGON_ARCH___ >= 60 */1143 1144#if __HVX_ARCH__ >= 601145/* ==========================================================================1146 Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat1147 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)1148 Instruction Type: CVI_VX_DV1149 Execution Slots: SLOT231150 ========================================================================== */1151 1152#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt)1153#endif /* __HEXAGON_ARCH___ >= 60 */1154 1155#if __HVX_ARCH__ >= 601156/* ==========================================================================1157 Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat1158 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt)1159 Instruction Type: CVI_VX1160 Execution Slots: SLOT231161 ========================================================================== */1162 1163#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt)1164#endif /* __HEXAGON_ARCH___ >= 60 */1165 1166#if __HVX_ARCH__ >= 601167/* ==========================================================================1168 Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat1169 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)1170 Instruction Type: CVI_VX1171 Execution Slots: SLOT231172 ========================================================================== */1173 1174#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt)1175#endif /* __HEXAGON_ARCH___ >= 60 */1176 1177#if __HVX_ARCH__ >= 601178/* ==========================================================================1179 Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat1180 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)1181 Instruction Type: CVI_VX1182 Execution Slots: SLOT231183 ========================================================================== */1184 1185#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv)1186#endif /* __HEXAGON_ARCH___ >= 60 */1187 1188#if __HVX_ARCH__ >= 601189/* ==========================================================================1190 Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat1191 C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)1192 Instruction Type: CVI_VX_DV1193 Execution Slots: SLOT231194 ========================================================================== */1195 1196#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv)1197#endif /* __HEXAGON_ARCH___ >= 60 */1198 1199#if __HVX_ARCH__ >= 601200/* ==========================================================================1201 Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)1202 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt)1203 Instruction Type: CVI_VX_DV1204 Execution Slots: SLOT231205 ========================================================================== */1206 1207#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt)1208#endif /* __HEXAGON_ARCH___ >= 60 */1209 1210#if __HVX_ARCH__ >= 601211/* ==========================================================================1212 Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)1213 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)1214 Instruction Type: CVI_VX_DV1215 Execution Slots: SLOT231216 ========================================================================== */1217 1218#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt)1219#endif /* __HEXAGON_ARCH___ >= 60 */1220 1221#if __HVX_ARCH__ >= 601222/* ==========================================================================1223 Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b)1224 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv)1225 Instruction Type: CVI_VA1226 Execution Slots: SLOT01231227 ========================================================================== */1228 1229#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1)1230#endif /* __HEXAGON_ARCH___ >= 60 */1231 1232#if __HVX_ARCH__ >= 601233/* ==========================================================================1234 Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b)1235 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1236 Instruction Type: CVI_VA1237 Execution Slots: SLOT01231238 ========================================================================== */1239 1240#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1241#endif /* __HEXAGON_ARCH___ >= 60 */1242 1243#if __HVX_ARCH__ >= 601244/* ==========================================================================1245 Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b)1246 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1247 Instruction Type: CVI_VA1248 Execution Slots: SLOT01231249 ========================================================================== */1250 1251#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1252#endif /* __HEXAGON_ARCH___ >= 60 */1253 1254#if __HVX_ARCH__ >= 601255/* ==========================================================================1256 Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b)1257 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1258 Instruction Type: CVI_VA1259 Execution Slots: SLOT01231260 ========================================================================== */1261 1262#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1263#endif /* __HEXAGON_ARCH___ >= 60 */1264 1265#if __HVX_ARCH__ >= 601266/* ==========================================================================1267 Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h)1268 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv)1269 Instruction Type: CVI_VA1270 Execution Slots: SLOT01231271 ========================================================================== */1272 1273#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1)1274#endif /* __HEXAGON_ARCH___ >= 60 */1275 1276#if __HVX_ARCH__ >= 601277/* ==========================================================================1278 Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h)1279 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1280 Instruction Type: CVI_VA1281 Execution Slots: SLOT01231282 ========================================================================== */1283 1284#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1285#endif /* __HEXAGON_ARCH___ >= 60 */1286 1287#if __HVX_ARCH__ >= 601288/* ==========================================================================1289 Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h)1290 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1291 Instruction Type: CVI_VA1292 Execution Slots: SLOT01231293 ========================================================================== */1294 1295#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1296#endif /* __HEXAGON_ARCH___ >= 60 */1297 1298#if __HVX_ARCH__ >= 601299/* ==========================================================================1300 Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h)1301 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1302 Instruction Type: CVI_VA1303 Execution Slots: SLOT01231304 ========================================================================== */1305 1306#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1307#endif /* __HEXAGON_ARCH___ >= 60 */1308 1309#if __HVX_ARCH__ >= 601310/* ==========================================================================1311 Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w)1312 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv)1313 Instruction Type: CVI_VA1314 Execution Slots: SLOT01231315 ========================================================================== */1316 1317#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1)1318#endif /* __HEXAGON_ARCH___ >= 60 */1319 1320#if __HVX_ARCH__ >= 601321/* ==========================================================================1322 Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w)1323 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1324 Instruction Type: CVI_VA1325 Execution Slots: SLOT01231326 ========================================================================== */1327 1328#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1329#endif /* __HEXAGON_ARCH___ >= 60 */1330 1331#if __HVX_ARCH__ >= 601332/* ==========================================================================1333 Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w)1334 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1335 Instruction Type: CVI_VA1336 Execution Slots: SLOT01231337 ========================================================================== */1338 1339#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1340#endif /* __HEXAGON_ARCH___ >= 60 */1341 1342#if __HVX_ARCH__ >= 601343/* ==========================================================================1344 Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w)1345 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1346 Instruction Type: CVI_VA1347 Execution Slots: SLOT01231348 ========================================================================== */1349 1350#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1351#endif /* __HEXAGON_ARCH___ >= 60 */1352 1353#if __HVX_ARCH__ >= 601354/* ==========================================================================1355 Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b)1356 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv)1357 Instruction Type: CVI_VA1358 Execution Slots: SLOT01231359 ========================================================================== */1360 1361#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1)1362#endif /* __HEXAGON_ARCH___ >= 60 */1363 1364#if __HVX_ARCH__ >= 601365/* ==========================================================================1366 Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b)1367 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1368 Instruction Type: CVI_VA1369 Execution Slots: SLOT01231370 ========================================================================== */1371 1372#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1373#endif /* __HEXAGON_ARCH___ >= 60 */1374 1375#if __HVX_ARCH__ >= 601376/* ==========================================================================1377 Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b)1378 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1379 Instruction Type: CVI_VA1380 Execution Slots: SLOT01231381 ========================================================================== */1382 1383#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1384#endif /* __HEXAGON_ARCH___ >= 60 */1385 1386#if __HVX_ARCH__ >= 601387/* ==========================================================================1388 Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b)1389 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1390 Instruction Type: CVI_VA1391 Execution Slots: SLOT01231392 ========================================================================== */1393 1394#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1395#endif /* __HEXAGON_ARCH___ >= 60 */1396 1397#if __HVX_ARCH__ >= 601398/* ==========================================================================1399 Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h)1400 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv)1401 Instruction Type: CVI_VA1402 Execution Slots: SLOT01231403 ========================================================================== */1404 1405#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1)1406#endif /* __HEXAGON_ARCH___ >= 60 */1407 1408#if __HVX_ARCH__ >= 601409/* ==========================================================================1410 Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h)1411 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1412 Instruction Type: CVI_VA1413 Execution Slots: SLOT01231414 ========================================================================== */1415 1416#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1417#endif /* __HEXAGON_ARCH___ >= 60 */1418 1419#if __HVX_ARCH__ >= 601420/* ==========================================================================1421 Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h)1422 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1423 Instruction Type: CVI_VA1424 Execution Slots: SLOT01231425 ========================================================================== */1426 1427#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1428#endif /* __HEXAGON_ARCH___ >= 60 */1429 1430#if __HVX_ARCH__ >= 601431/* ==========================================================================1432 Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h)1433 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1434 Instruction Type: CVI_VA1435 Execution Slots: SLOT01231436 ========================================================================== */1437 1438#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1439#endif /* __HEXAGON_ARCH___ >= 60 */1440 1441#if __HVX_ARCH__ >= 601442/* ==========================================================================1443 Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub)1444 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv)1445 Instruction Type: CVI_VA1446 Execution Slots: SLOT01231447 ========================================================================== */1448 1449#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1)1450#endif /* __HEXAGON_ARCH___ >= 60 */1451 1452#if __HVX_ARCH__ >= 601453/* ==========================================================================1454 Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)1455 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1456 Instruction Type: CVI_VA1457 Execution Slots: SLOT01231458 ========================================================================== */1459 1460#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1461#endif /* __HEXAGON_ARCH___ >= 60 */1462 1463#if __HVX_ARCH__ >= 601464/* ==========================================================================1465 Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)1466 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1467 Instruction Type: CVI_VA1468 Execution Slots: SLOT01231469 ========================================================================== */1470 1471#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1472#endif /* __HEXAGON_ARCH___ >= 60 */1473 1474#if __HVX_ARCH__ >= 601475/* ==========================================================================1476 Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)1477 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1478 Instruction Type: CVI_VA1479 Execution Slots: SLOT01231480 ========================================================================== */1481 1482#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1483#endif /* __HEXAGON_ARCH___ >= 60 */1484 1485#if __HVX_ARCH__ >= 601486/* ==========================================================================1487 Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh)1488 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)1489 Instruction Type: CVI_VA1490 Execution Slots: SLOT01231491 ========================================================================== */1492 1493#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1)1494#endif /* __HEXAGON_ARCH___ >= 60 */1495 1496#if __HVX_ARCH__ >= 601497/* ==========================================================================1498 Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)1499 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1500 Instruction Type: CVI_VA1501 Execution Slots: SLOT01231502 ========================================================================== */1503 1504#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1505#endif /* __HEXAGON_ARCH___ >= 60 */1506 1507#if __HVX_ARCH__ >= 601508/* ==========================================================================1509 Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)1510 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1511 Instruction Type: CVI_VA1512 Execution Slots: SLOT01231513 ========================================================================== */1514 1515#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1516#endif /* __HEXAGON_ARCH___ >= 60 */1517 1518#if __HVX_ARCH__ >= 601519/* ==========================================================================1520 Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)1521 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1522 Instruction Type: CVI_VA1523 Execution Slots: SLOT01231524 ========================================================================== */1525 1526#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1527#endif /* __HEXAGON_ARCH___ >= 60 */1528 1529#if __HVX_ARCH__ >= 601530/* ==========================================================================1531 Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw)1532 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)1533 Instruction Type: CVI_VA1534 Execution Slots: SLOT01231535 ========================================================================== */1536 1537#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1)1538#endif /* __HEXAGON_ARCH___ >= 60 */1539 1540#if __HVX_ARCH__ >= 601541/* ==========================================================================1542 Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)1543 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1544 Instruction Type: CVI_VA1545 Execution Slots: SLOT01231546 ========================================================================== */1547 1548#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1549#endif /* __HEXAGON_ARCH___ >= 60 */1550 1551#if __HVX_ARCH__ >= 601552/* ==========================================================================1553 Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)1554 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1555 Instruction Type: CVI_VA1556 Execution Slots: SLOT01231557 ========================================================================== */1558 1559#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1560#endif /* __HEXAGON_ARCH___ >= 60 */1561 1562#if __HVX_ARCH__ >= 601563/* ==========================================================================1564 Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)1565 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1566 Instruction Type: CVI_VA1567 Execution Slots: SLOT01231568 ========================================================================== */1569 1570#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1571#endif /* __HEXAGON_ARCH___ >= 60 */1572 1573#if __HVX_ARCH__ >= 601574/* ==========================================================================1575 Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w)1576 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv)1577 Instruction Type: CVI_VA1578 Execution Slots: SLOT01231579 ========================================================================== */1580 1581#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1)1582#endif /* __HEXAGON_ARCH___ >= 60 */1583 1584#if __HVX_ARCH__ >= 601585/* ==========================================================================1586 Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w)1587 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1588 Instruction Type: CVI_VA1589 Execution Slots: SLOT01231590 ========================================================================== */1591 1592#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1593#endif /* __HEXAGON_ARCH___ >= 60 */1594 1595#if __HVX_ARCH__ >= 601596/* ==========================================================================1597 Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w)1598 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1599 Instruction Type: CVI_VA1600 Execution Slots: SLOT01231601 ========================================================================== */1602 1603#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1604#endif /* __HEXAGON_ARCH___ >= 60 */1605 1606#if __HVX_ARCH__ >= 601607/* ==========================================================================1608 Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w)1609 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)1610 Instruction Type: CVI_VA1611 Execution Slots: SLOT01231612 ========================================================================== */1613 1614#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)1615#endif /* __HEXAGON_ARCH___ >= 60 */1616 1617#if __HVX_ARCH__ >= 601618/* ==========================================================================1619 Assembly Syntax: Vx32.w=vinsert(Rt32)1620 C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt)1621 Instruction Type: CVI_VX_LATE1622 Execution Slots: SLOT231623 ========================================================================== */1624 1625#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt)1626#endif /* __HEXAGON_ARCH___ >= 60 */1627 1628#if __HVX_ARCH__ >= 601629/* ==========================================================================1630 Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8)1631 C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)1632 Instruction Type: CVI_VP1633 Execution Slots: SLOT01231634 ========================================================================== */1635 1636#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt)1637#endif /* __HEXAGON_ARCH___ >= 60 */1638 1639#if __HVX_ARCH__ >= 601640/* ==========================================================================1641 Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3)1642 C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)1643 Instruction Type: CVI_VP1644 Execution Slots: SLOT01231645 ========================================================================== */1646 1647#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3)1648#endif /* __HEXAGON_ARCH___ >= 60 */1649 1650#if __HVX_ARCH__ >= 601651/* ==========================================================================1652 Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32)1653 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt)1654 Instruction Type: CVI_VS1655 Execution Slots: SLOT01231656 ========================================================================== */1657 1658#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt)1659#endif /* __HEXAGON_ARCH___ >= 60 */1660 1661#if __HVX_ARCH__ >= 601662/* ==========================================================================1663 Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h)1664 C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv)1665 Instruction Type: CVI_VS1666 Execution Slots: SLOT01231667 ========================================================================== */1668 1669#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv)1670#endif /* __HEXAGON_ARCH___ >= 60 */1671 1672#if __HVX_ARCH__ >= 601673/* ==========================================================================1674 Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32)1675 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt)1676 Instruction Type: CVI_VS1677 Execution Slots: SLOT01231678 ========================================================================== */1679 1680#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt)1681#endif /* __HEXAGON_ARCH___ >= 60 */1682 1683#if __HVX_ARCH__ >= 601684/* ==========================================================================1685 Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w)1686 C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv)1687 Instruction Type: CVI_VS1688 Execution Slots: SLOT01231689 ========================================================================== */1690 1691#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv)1692#endif /* __HEXAGON_ARCH___ >= 60 */1693 1694#if __HVX_ARCH__ >= 601695/* ==========================================================================1696 Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)1697 C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)1698 Instruction Type: CVI_VP1699 Execution Slots: SLOT01231700 ========================================================================== */1701 1702#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt)1703#endif /* __HEXAGON_ARCH___ >= 60 */1704 1705#if __HVX_ARCH__ >= 601706/* ==========================================================================1707 Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)1708 C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)1709 Instruction Type: CVI_VP_VS1710 Execution Slots: SLOT01231711 ========================================================================== */1712 1713#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt)1714#endif /* __HEXAGON_ARCH___ >= 60 */1715 1716#if __HVX_ARCH__ >= 601717/* ==========================================================================1718 Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)1719 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)1720 Instruction Type: CVI_VP_VS1721 Execution Slots: SLOT01231722 ========================================================================== */1723 1724#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt)1725#endif /* __HEXAGON_ARCH___ >= 60 */1726 1727#if __HVX_ARCH__ >= 601728/* ==========================================================================1729 Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)1730 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)1731 Instruction Type: CVI_VP_VS1732 Execution Slots: SLOT01231733 ========================================================================== */1734 1735#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt)1736#endif /* __HEXAGON_ARCH___ >= 60 */1737 1738#if __HVX_ARCH__ >= 601739/* ==========================================================================1740 Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h)1741 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv)1742 Instruction Type: CVI_VA1743 Execution Slots: SLOT01231744 ========================================================================== */1745 1746#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv)1747#endif /* __HEXAGON_ARCH___ >= 60 */1748 1749#if __HVX_ARCH__ >= 601750/* ==========================================================================1751 Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub)1752 C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv)1753 Instruction Type: CVI_VA1754 Execution Slots: SLOT01231755 ========================================================================== */1756 1757#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv)1758#endif /* __HEXAGON_ARCH___ >= 60 */1759 1760#if __HVX_ARCH__ >= 601761/* ==========================================================================1762 Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh)1763 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)1764 Instruction Type: CVI_VA1765 Execution Slots: SLOT01231766 ========================================================================== */1767 1768#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv)1769#endif /* __HEXAGON_ARCH___ >= 60 */1770 1771#if __HVX_ARCH__ >= 601772/* ==========================================================================1773 Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w)1774 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv)1775 Instruction Type: CVI_VA1776 Execution Slots: SLOT01231777 ========================================================================== */1778 1779#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv)1780#endif /* __HEXAGON_ARCH___ >= 60 */1781 1782#if __HVX_ARCH__ >= 601783/* ==========================================================================1784 Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h)1785 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv)1786 Instruction Type: CVI_VA1787 Execution Slots: SLOT01231788 ========================================================================== */1789 1790#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv)1791#endif /* __HEXAGON_ARCH___ >= 60 */1792 1793#if __HVX_ARCH__ >= 601794/* ==========================================================================1795 Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub)1796 C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv)1797 Instruction Type: CVI_VA1798 Execution Slots: SLOT01231799 ========================================================================== */1800 1801#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv)1802#endif /* __HEXAGON_ARCH___ >= 60 */1803 1804#if __HVX_ARCH__ >= 601805/* ==========================================================================1806 Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh)1807 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)1808 Instruction Type: CVI_VA1809 Execution Slots: SLOT01231810 ========================================================================== */1811 1812#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv)1813#endif /* __HEXAGON_ARCH___ >= 60 */1814 1815#if __HVX_ARCH__ >= 601816/* ==========================================================================1817 Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w)1818 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv)1819 Instruction Type: CVI_VA1820 Execution Slots: SLOT01231821 ========================================================================== */1822 1823#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv)1824#endif /* __HEXAGON_ARCH___ >= 60 */1825 1826#if __HVX_ARCH__ >= 601827/* ==========================================================================1828 Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b)1829 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt)1830 Instruction Type: CVI_VX_DV1831 Execution Slots: SLOT231832 ========================================================================== */1833 1834#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt)1835#endif /* __HEXAGON_ARCH___ >= 60 */1836 1837#if __HVX_ARCH__ >= 601838/* ==========================================================================1839 Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)1840 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)1841 Instruction Type: CVI_VX_DV1842 Execution Slots: SLOT231843 ========================================================================== */1844 1845#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt)1846#endif /* __HEXAGON_ARCH___ >= 60 */1847 1848#if __HVX_ARCH__ >= 601849/* ==========================================================================1850 Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)1851 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)1852 Instruction Type: CVI_VX_DV1853 Execution Slots: SLOT231854 ========================================================================== */1855 1856#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv)1857#endif /* __HEXAGON_ARCH___ >= 60 */1858 1859#if __HVX_ARCH__ >= 601860/* ==========================================================================1861 Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)1862 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv)1863 Instruction Type: CVI_VX_DV1864 Execution Slots: SLOT231865 ========================================================================== */1866 1867#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv)1868#endif /* __HEXAGON_ARCH___ >= 60 */1869 1870#if __HVX_ARCH__ >= 601871/* ==========================================================================1872 Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b)1873 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt)1874 Instruction Type: CVI_VX_DV1875 Execution Slots: SLOT231876 ========================================================================== */1877 1878#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt)1879#endif /* __HEXAGON_ARCH___ >= 60 */1880 1881#if __HVX_ARCH__ >= 601882/* ==========================================================================1883 Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b)1884 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)1885 Instruction Type: CVI_VX_DV1886 Execution Slots: SLOT231887 ========================================================================== */1888 1889#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt)1890#endif /* __HEXAGON_ARCH___ >= 60 */1891 1892#if __HVX_ARCH__ >= 601893/* ==========================================================================1894 Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b)1895 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt)1896 Instruction Type: CVI_VX_DV1897 Execution Slots: SLOT231898 ========================================================================== */1899 1900#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt)1901#endif /* __HEXAGON_ARCH___ >= 60 */1902 1903#if __HVX_ARCH__ >= 601904/* ==========================================================================1905 Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b)1906 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)1907 Instruction Type: CVI_VX_DV1908 Execution Slots: SLOT231909 ========================================================================== */1910 1911#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt)1912#endif /* __HEXAGON_ARCH___ >= 60 */1913 1914#if __HVX_ARCH__ >= 601915/* ==========================================================================1916 Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b)1917 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)1918 Instruction Type: CVI_VX_DV1919 Execution Slots: SLOT231920 ========================================================================== */1921 1922#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv)1923#endif /* __HEXAGON_ARCH___ >= 60 */1924 1925#if __HVX_ARCH__ >= 601926/* ==========================================================================1927 Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b)1928 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)1929 Instruction Type: CVI_VX_DV1930 Execution Slots: SLOT231931 ========================================================================== */1932 1933#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv)1934#endif /* __HEXAGON_ARCH___ >= 60 */1935 1936#if __HVX_ARCH__ >= 601937/* ==========================================================================1938 Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b)1939 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)1940 Instruction Type: CVI_VX_DV1941 Execution Slots: SLOT231942 ========================================================================== */1943 1944#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv)1945#endif /* __HEXAGON_ARCH___ >= 60 */1946 1947#if __HVX_ARCH__ >= 601948/* ==========================================================================1949 Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b)1950 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)1951 Instruction Type: CVI_VX_DV1952 Execution Slots: SLOT231953 ========================================================================== */1954 1955#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv)1956#endif /* __HEXAGON_ARCH___ >= 60 */1957 1958#if __HVX_ARCH__ >= 601959/* ==========================================================================1960 Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh)1961 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)1962 Instruction Type: CVI_VX_DV1963 Execution Slots: SLOT231964 ========================================================================== */1965 1966#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv)1967#endif /* __HEXAGON_ARCH___ >= 60 */1968 1969#if __HVX_ARCH__ >= 601970/* ==========================================================================1971 Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h)1972 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt)1973 Instruction Type: CVI_VX_DV1974 Execution Slots: SLOT231975 ========================================================================== */1976 1977#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt)1978#endif /* __HEXAGON_ARCH___ >= 60 */1979 1980#if __HVX_ARCH__ >= 601981/* ==========================================================================1982 Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat1983 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)1984 Instruction Type: CVI_VX_DV1985 Execution Slots: SLOT231986 ========================================================================== */1987 1988#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt)1989#endif /* __HEXAGON_ARCH___ >= 60 */1990 1991#if __HVX_ARCH__ >= 601992/* ==========================================================================1993 Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat1994 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt)1995 Instruction Type: CVI_VX1996 Execution Slots: SLOT231997 ========================================================================== */1998 1999#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt)2000#endif /* __HEXAGON_ARCH___ >= 60 */2001 2002#if __HVX_ARCH__ >= 602003/* ==========================================================================2004 Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat2005 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt)2006 Instruction Type: CVI_VX2007 Execution Slots: SLOT232008 ========================================================================== */2009 2010#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt)2011#endif /* __HEXAGON_ARCH___ >= 60 */2012 2013#if __HVX_ARCH__ >= 602014/* ==========================================================================2015 Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh)2016 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv)2017 Instruction Type: CVI_VX_DV2018 Execution Slots: SLOT232019 ========================================================================== */2020 2021#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv)2022#endif /* __HEXAGON_ARCH___ >= 60 */2023 2024#if __HVX_ARCH__ >= 602025/* ==========================================================================2026 Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh)2027 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)2028 Instruction Type: CVI_VX_DV2029 Execution Slots: SLOT232030 ========================================================================== */2031 2032#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv)2033#endif /* __HEXAGON_ARCH___ >= 60 */2034 2035#if __HVX_ARCH__ >= 602036/* ==========================================================================2037 Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h)2038 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv)2039 Instruction Type: CVI_VX_DV2040 Execution Slots: SLOT232041 ========================================================================== */2042 2043#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv)2044#endif /* __HEXAGON_ARCH___ >= 60 */2045 2046#if __HVX_ARCH__ >= 602047/* ==========================================================================2048 Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h)2049 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)2050 Instruction Type: CVI_VX_DV2051 Execution Slots: SLOT232052 ========================================================================== */2053 2054#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv)2055#endif /* __HEXAGON_ARCH___ >= 60 */2056 2057#if __HVX_ARCH__ >= 602058/* ==========================================================================2059 Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat2060 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)2061 Instruction Type: CVI_VX2062 Execution Slots: SLOT232063 ========================================================================== */2064 2065#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv)2066#endif /* __HEXAGON_ARCH___ >= 60 */2067 2068#if __HVX_ARCH__ >= 602069/* ==========================================================================2070 Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h)2071 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv)2072 Instruction Type: CVI_VX2073 Execution Slots: SLOT232074 ========================================================================== */2075 2076#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv)2077#endif /* __HEXAGON_ARCH___ >= 60 */2078 2079#if __HVX_ARCH__ >= 602080/* ==========================================================================2081 Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h)2082 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2083 Instruction Type: CVI_VX_DV2084 Execution Slots: SLOT232085 ========================================================================== */2086 2087#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv)2088#endif /* __HEXAGON_ARCH___ >= 60 */2089 2090#if __HVX_ARCH__ >= 602091/* ==========================================================================2092 Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh)2093 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv)2094 Instruction Type: CVI_VX_DV2095 Execution Slots: SLOT232096 ========================================================================== */2097 2098#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv)2099#endif /* __HEXAGON_ARCH___ >= 60 */2100 2101#if __HVX_ARCH__ >= 602102/* ==========================================================================2103 Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh)2104 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2105 Instruction Type: CVI_VX_DV2106 Execution Slots: SLOT232107 ========================================================================== */2108 2109#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv)2110#endif /* __HEXAGON_ARCH___ >= 60 */2111 2112#if __HVX_ARCH__ >= 602113/* ==========================================================================2114 Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h)2115 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv)2116 Instruction Type: CVI_VX_DV2117 Execution Slots: SLOT232118 ========================================================================== */2119 2120#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv)2121#endif /* __HEXAGON_ARCH___ >= 60 */2122 2123#if __HVX_ARCH__ >= 602124/* ==========================================================================2125 Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h)2126 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2127 Instruction Type: CVI_VX_DV2128 Execution Slots: SLOT232129 ========================================================================== */2130 2131#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv)2132#endif /* __HEXAGON_ARCH___ >= 60 */2133 2134#if __HVX_ARCH__ >= 602135/* ==========================================================================2136 Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b)2137 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt)2138 Instruction Type: CVI_VX2139 Execution Slots: SLOT232140 ========================================================================== */2141 2142#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt)2143#endif /* __HEXAGON_ARCH___ >= 60 */2144 2145#if __HVX_ARCH__ >= 602146/* ==========================================================================2147 Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b)2148 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)2149 Instruction Type: CVI_VX2150 Execution Slots: SLOT232151 ========================================================================== */2152 2153#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt)2154#endif /* __HEXAGON_ARCH___ >= 60 */2155 2156#if __HVX_ARCH__ >= 602157/* ==========================================================================2158 Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h)2159 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv)2160 Instruction Type: CVI_VX_DV2161 Execution Slots: SLOT232162 ========================================================================== */2163 2164#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv)2165#endif /* __HEXAGON_ARCH___ >= 60 */2166 2167#if __HVX_ARCH__ >= 602168/* ==========================================================================2169 Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b)2170 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt)2171 Instruction Type: CVI_VX2172 Execution Slots: SLOT232173 ========================================================================== */2174 2175#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt)2176#endif /* __HEXAGON_ARCH___ >= 60 */2177 2178#if __HVX_ARCH__ >= 602179/* ==========================================================================2180 Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b)2181 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)2182 Instruction Type: CVI_VX2183 Execution Slots: SLOT232184 ========================================================================== */2185 2186#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt)2187#endif /* __HEXAGON_ARCH___ >= 60 */2188 2189#if __HVX_ARCH__ >= 602190/* ==========================================================================2191 Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h)2192 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt)2193 Instruction Type: CVI_VX_DV2194 Execution Slots: SLOT232195 ========================================================================== */2196 2197#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt)2198#endif /* __HEXAGON_ARCH___ >= 60 */2199 2200#if __HVX_ARCH__ >= 602201/* ==========================================================================2202 Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h)2203 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)2204 Instruction Type: CVI_VX_DV2205 Execution Slots: SLOT232206 ========================================================================== */2207 2208#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt)2209#endif /* __HEXAGON_ARCH___ >= 60 */2210 2211#if __HVX_ARCH__ >= 602212/* ==========================================================================2213 Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat2214 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv)2215 Instruction Type: CVI_VX_DV2216 Execution Slots: SLOT232217 ========================================================================== */2218 2219#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv)2220#endif /* __HEXAGON_ARCH___ >= 60 */2221 2222#if __HVX_ARCH__ >= 602223/* ==========================================================================2224 Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat2225 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)2226 Instruction Type: CVI_VX_DV2227 Execution Slots: SLOT232228 ========================================================================== */2229 2230#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv)2231#endif /* __HEXAGON_ARCH___ >= 60 */2232 2233#if __HVX_ARCH__ >= 602234/* ==========================================================================2235 Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift2236 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2237 Instruction Type: CVI_VX_DV2238 Execution Slots: SLOT232239 ========================================================================== */2240 2241#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv)2242#endif /* __HEXAGON_ARCH___ >= 60 */2243 2244#if __HVX_ARCH__ >= 602245/* ==========================================================================2246 Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift2247 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2248 Instruction Type: CVI_VX_DV2249 Execution Slots: SLOT232250 ========================================================================== */2251 2252#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv)2253#endif /* __HEXAGON_ARCH___ >= 60 */2254 2255#if __HVX_ARCH__ >= 602256/* ==========================================================================2257 Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)2258 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt)2259 Instruction Type: CVI_VX_DV2260 Execution Slots: SLOT232261 ========================================================================== */2262 2263#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt)2264#endif /* __HEXAGON_ARCH___ >= 60 */2265 2266#if __HVX_ARCH__ >= 602267/* ==========================================================================2268 Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)2269 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)2270 Instruction Type: CVI_VX_DV2271 Execution Slots: SLOT232272 ========================================================================== */2273 2274#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt)2275#endif /* __HEXAGON_ARCH___ >= 60 */2276 2277#if __HVX_ARCH__ >= 602278/* ==========================================================================2279 Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)2280 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)2281 Instruction Type: CVI_VX_DV2282 Execution Slots: SLOT232283 ========================================================================== */2284 2285#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv)2286#endif /* __HEXAGON_ARCH___ >= 60 */2287 2288#if __HVX_ARCH__ >= 602289/* ==========================================================================2290 Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)2291 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)2292 Instruction Type: CVI_VX_DV2293 Execution Slots: SLOT232294 ========================================================================== */2295 2296#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv)2297#endif /* __HEXAGON_ARCH___ >= 60 */2298 2299#if __HVX_ARCH__ >= 602300/* ==========================================================================2301 Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)2302 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt)2303 Instruction Type: CVI_VX_DV2304 Execution Slots: SLOT232305 ========================================================================== */2306 2307#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt)2308#endif /* __HEXAGON_ARCH___ >= 60 */2309 2310#if __HVX_ARCH__ >= 602311/* ==========================================================================2312 Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)2313 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)2314 Instruction Type: CVI_VX_DV2315 Execution Slots: SLOT232316 ========================================================================== */2317 2318#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt)2319#endif /* __HEXAGON_ARCH___ >= 60 */2320 2321#if __HVX_ARCH__ >= 602322/* ==========================================================================2323 Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)2324 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)2325 Instruction Type: CVI_VX_DV2326 Execution Slots: SLOT232327 ========================================================================== */2328 2329#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv)2330#endif /* __HEXAGON_ARCH___ >= 60 */2331 2332#if __HVX_ARCH__ >= 602333/* ==========================================================================2334 Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)2335 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)2336 Instruction Type: CVI_VX_DV2337 Execution Slots: SLOT232338 ========================================================================== */2339 2340#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv)2341#endif /* __HEXAGON_ARCH___ >= 60 */2342 2343#if __HVX_ARCH__ >= 602344/* ==========================================================================2345 Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32)2346 C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)2347 Instruction Type: CVI_VA2348 Execution Slots: SLOT01232349 ========================================================================== */2350 2351#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)2352#endif /* __HEXAGON_ARCH___ >= 60 */2353 2354#if __HVX_ARCH__ >= 602355/* ==========================================================================2356 Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h)2357 C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)2358 Instruction Type: CVI_VA2359 Execution Slots: SLOT01232360 ========================================================================== */2361 2362#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv)2363#endif /* __HEXAGON_ARCH___ >= 60 */2364 2365#if __HVX_ARCH__ >= 602366/* ==========================================================================2367 Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub)2368 C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)2369 Instruction Type: CVI_VA2370 Execution Slots: SLOT01232371 ========================================================================== */2372 2373#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv)2374#endif /* __HEXAGON_ARCH___ >= 60 */2375 2376#if __HVX_ARCH__ >= 602377/* ==========================================================================2378 Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w)2379 C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)2380 Instruction Type: CVI_VA2381 Execution Slots: SLOT01232382 ========================================================================== */2383 2384#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv)2385#endif /* __HEXAGON_ARCH___ >= 60 */2386 2387#if __HVX_ARCH__ >= 602388/* ==========================================================================2389 Assembly Syntax: Vd32.h=vnormamt(Vu32.h)2390 C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu)2391 Instruction Type: CVI_VS2392 Execution Slots: SLOT01232393 ========================================================================== */2394 2395#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu)2396#endif /* __HEXAGON_ARCH___ >= 60 */2397 2398#if __HVX_ARCH__ >= 602399/* ==========================================================================2400 Assembly Syntax: Vd32.w=vnormamt(Vu32.w)2401 C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu)2402 Instruction Type: CVI_VS2403 Execution Slots: SLOT01232404 ========================================================================== */2405 2406#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu)2407#endif /* __HEXAGON_ARCH___ >= 60 */2408 2409#if __HVX_ARCH__ >= 602410/* ==========================================================================2411 Assembly Syntax: Vd32=vnot(Vu32)2412 C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu)2413 Instruction Type: CVI_VA2414 Execution Slots: SLOT01232415 ========================================================================== */2416 2417#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu)2418#endif /* __HEXAGON_ARCH___ >= 60 */2419 2420#if __HVX_ARCH__ >= 602421/* ==========================================================================2422 Assembly Syntax: Vd32=vor(Vu32,Vv32)2423 C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv)2424 Instruction Type: CVI_VA2425 Execution Slots: SLOT01232426 ========================================================================== */2427 2428#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv)2429#endif /* __HEXAGON_ARCH___ >= 60 */2430 2431#if __HVX_ARCH__ >= 602432/* ==========================================================================2433 Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h)2434 C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv)2435 Instruction Type: CVI_VP2436 Execution Slots: SLOT01232437 ========================================================================== */2438 2439#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv)2440#endif /* __HEXAGON_ARCH___ >= 60 */2441 2442#if __HVX_ARCH__ >= 602443/* ==========================================================================2444 Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w)2445 C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv)2446 Instruction Type: CVI_VP2447 Execution Slots: SLOT01232448 ========================================================================== */2449 2450#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv)2451#endif /* __HEXAGON_ARCH___ >= 60 */2452 2453#if __HVX_ARCH__ >= 602454/* ==========================================================================2455 Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat2456 C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)2457 Instruction Type: CVI_VP2458 Execution Slots: SLOT01232459 ========================================================================== */2460 2461#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv)2462#endif /* __HEXAGON_ARCH___ >= 60 */2463 2464#if __HVX_ARCH__ >= 602465/* ==========================================================================2466 Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat2467 C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)2468 Instruction Type: CVI_VP2469 Execution Slots: SLOT01232470 ========================================================================== */2471 2472#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv)2473#endif /* __HEXAGON_ARCH___ >= 60 */2474 2475#if __HVX_ARCH__ >= 602476/* ==========================================================================2477 Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h)2478 C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv)2479 Instruction Type: CVI_VP2480 Execution Slots: SLOT01232481 ========================================================================== */2482 2483#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv)2484#endif /* __HEXAGON_ARCH___ >= 60 */2485 2486#if __HVX_ARCH__ >= 602487/* ==========================================================================2488 Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w)2489 C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv)2490 Instruction Type: CVI_VP2491 Execution Slots: SLOT01232492 ========================================================================== */2493 2494#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv)2495#endif /* __HEXAGON_ARCH___ >= 60 */2496 2497#if __HVX_ARCH__ >= 602498/* ==========================================================================2499 Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat2500 C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)2501 Instruction Type: CVI_VP2502 Execution Slots: SLOT01232503 ========================================================================== */2504 2505#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv)2506#endif /* __HEXAGON_ARCH___ >= 60 */2507 2508#if __HVX_ARCH__ >= 602509/* ==========================================================================2510 Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat2511 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)2512 Instruction Type: CVI_VP2513 Execution Slots: SLOT01232514 ========================================================================== */2515 2516#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv)2517#endif /* __HEXAGON_ARCH___ >= 60 */2518 2519#if __HVX_ARCH__ >= 602520/* ==========================================================================2521 Assembly Syntax: Vd32.h=vpopcount(Vu32.h)2522 C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu)2523 Instruction Type: CVI_VS2524 Execution Slots: SLOT01232525 ========================================================================== */2526 2527#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu)2528#endif /* __HEXAGON_ARCH___ >= 60 */2529 2530#if __HVX_ARCH__ >= 602531/* ==========================================================================2532 Assembly Syntax: Vd32=vrdelta(Vu32,Vv32)2533 C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv)2534 Instruction Type: CVI_VP2535 Execution Slots: SLOT01232536 ========================================================================== */2537 2538#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv)2539#endif /* __HEXAGON_ARCH___ >= 60 */2540 2541#if __HVX_ARCH__ >= 602542/* ==========================================================================2543 Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b)2544 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt)2545 Instruction Type: CVI_VX2546 Execution Slots: SLOT232547 ========================================================================== */2548 2549#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt)2550#endif /* __HEXAGON_ARCH___ >= 60 */2551 2552#if __HVX_ARCH__ >= 602553/* ==========================================================================2554 Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b)2555 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)2556 Instruction Type: CVI_VX2557 Execution Slots: SLOT232558 ========================================================================== */2559 2560#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt)2561#endif /* __HEXAGON_ARCH___ >= 60 */2562 2563#if __HVX_ARCH__ >= 602564/* ==========================================================================2565 Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)2566 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2567 Instruction Type: CVI_VX_DV2568 Execution Slots: SLOT232569 ========================================================================== */2570 2571#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1)2572#endif /* __HEXAGON_ARCH___ >= 60 */2573 2574#if __HVX_ARCH__ >= 602575/* ==========================================================================2576 Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)2577 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2578 Instruction Type: CVI_VX_DV2579 Execution Slots: SLOT232580 ========================================================================== */2581 2582#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1)2583#endif /* __HEXAGON_ARCH___ >= 60 */2584 2585#if __HVX_ARCH__ >= 602586/* ==========================================================================2587 Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b)2588 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)2589 Instruction Type: CVI_VX2590 Execution Slots: SLOT232591 ========================================================================== */2592 2593#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv)2594#endif /* __HEXAGON_ARCH___ >= 60 */2595 2596#if __HVX_ARCH__ >= 602597/* ==========================================================================2598 Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b)2599 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2600 Instruction Type: CVI_VX2601 Execution Slots: SLOT232602 ========================================================================== */2603 2604#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv)2605#endif /* __HEXAGON_ARCH___ >= 60 */2606 2607#if __HVX_ARCH__ >= 602608/* ==========================================================================2609 Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b)2610 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)2611 Instruction Type: CVI_VX2612 Execution Slots: SLOT232613 ========================================================================== */2614 2615#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv)2616#endif /* __HEXAGON_ARCH___ >= 60 */2617 2618#if __HVX_ARCH__ >= 602619/* ==========================================================================2620 Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b)2621 C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2622 Instruction Type: CVI_VX2623 Execution Slots: SLOT232624 ========================================================================== */2625 2626#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv)2627#endif /* __HEXAGON_ARCH___ >= 60 */2628 2629#if __HVX_ARCH__ >= 602630/* ==========================================================================2631 Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)2632 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt)2633 Instruction Type: CVI_VX2634 Execution Slots: SLOT232635 ========================================================================== */2636 2637#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt)2638#endif /* __HEXAGON_ARCH___ >= 60 */2639 2640#if __HVX_ARCH__ >= 602641/* ==========================================================================2642 Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)2643 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)2644 Instruction Type: CVI_VX2645 Execution Slots: SLOT232646 ========================================================================== */2647 2648#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt)2649#endif /* __HEXAGON_ARCH___ >= 60 */2650 2651#if __HVX_ARCH__ >= 602652/* ==========================================================================2653 Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)2654 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2655 Instruction Type: CVI_VX_DV2656 Execution Slots: SLOT232657 ========================================================================== */2658 2659#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1)2660#endif /* __HEXAGON_ARCH___ >= 60 */2661 2662#if __HVX_ARCH__ >= 602663/* ==========================================================================2664 Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)2665 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2666 Instruction Type: CVI_VX_DV2667 Execution Slots: SLOT232668 ========================================================================== */2669 2670#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1)2671#endif /* __HEXAGON_ARCH___ >= 60 */2672 2673#if __HVX_ARCH__ >= 602674/* ==========================================================================2675 Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)2676 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)2677 Instruction Type: CVI_VX2678 Execution Slots: SLOT232679 ========================================================================== */2680 2681#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv)2682#endif /* __HEXAGON_ARCH___ >= 60 */2683 2684#if __HVX_ARCH__ >= 602685/* ==========================================================================2686 Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)2687 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)2688 Instruction Type: CVI_VX2689 Execution Slots: SLOT232690 ========================================================================== */2691 2692#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv)2693#endif /* __HEXAGON_ARCH___ >= 60 */2694 2695#if __HVX_ARCH__ >= 602696/* ==========================================================================2697 Assembly Syntax: Vd32=vror(Vu32,Rt32)2698 C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt)2699 Instruction Type: CVI_VP2700 Execution Slots: SLOT01232701 ========================================================================== */2702 2703#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt)2704#endif /* __HEXAGON_ARCH___ >= 60 */2705 2706#if __HVX_ARCH__ >= 602707/* ==========================================================================2708 Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat2709 C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)2710 Instruction Type: CVI_VS2711 Execution Slots: SLOT01232712 ========================================================================== */2713 2714#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv)2715#endif /* __HEXAGON_ARCH___ >= 60 */2716 2717#if __HVX_ARCH__ >= 602718/* ==========================================================================2719 Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat2720 C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)2721 Instruction Type: CVI_VS2722 Execution Slots: SLOT01232723 ========================================================================== */2724 2725#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv)2726#endif /* __HEXAGON_ARCH___ >= 60 */2727 2728#if __HVX_ARCH__ >= 602729/* ==========================================================================2730 Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat2731 C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)2732 Instruction Type: CVI_VS2733 Execution Slots: SLOT01232734 ========================================================================== */2735 2736#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv)2737#endif /* __HEXAGON_ARCH___ >= 60 */2738 2739#if __HVX_ARCH__ >= 602740/* ==========================================================================2741 Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat2742 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)2743 Instruction Type: CVI_VS2744 Execution Slots: SLOT01232745 ========================================================================== */2746 2747#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv)2748#endif /* __HEXAGON_ARCH___ >= 60 */2749 2750#if __HVX_ARCH__ >= 602751/* ==========================================================================2752 Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)2753 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2754 Instruction Type: CVI_VX_DV2755 Execution Slots: SLOT232756 ========================================================================== */2757 2758#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1)2759#endif /* __HEXAGON_ARCH___ >= 60 */2760 2761#if __HVX_ARCH__ >= 602762/* ==========================================================================2763 Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)2764 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)2765 Instruction Type: CVI_VX_DV2766 Execution Slots: SLOT232767 ========================================================================== */2768 2769#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1)2770#endif /* __HEXAGON_ARCH___ >= 60 */2771 2772#if __HVX_ARCH__ >= 602773/* ==========================================================================2774 Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h)2775 C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv)2776 Instruction Type: CVI_VA2777 Execution Slots: SLOT01232778 ========================================================================== */2779 2780#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv)2781#endif /* __HEXAGON_ARCH___ >= 60 */2782 2783#if __HVX_ARCH__ >= 602784/* ==========================================================================2785 Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w)2786 C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv)2787 Instruction Type: CVI_VA2788 Execution Slots: SLOT01232789 ========================================================================== */2790 2791#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv)2792#endif /* __HEXAGON_ARCH___ >= 60 */2793 2794#if __HVX_ARCH__ >= 602795/* ==========================================================================2796 Assembly Syntax: Vdd32.h=vsxt(Vu32.b)2797 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu)2798 Instruction Type: CVI_VA_DV2799 Execution Slots: SLOT01232800 ========================================================================== */2801 2802#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu)2803#endif /* __HEXAGON_ARCH___ >= 60 */2804 2805#if __HVX_ARCH__ >= 602806/* ==========================================================================2807 Assembly Syntax: Vdd32.w=vsxt(Vu32.h)2808 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu)2809 Instruction Type: CVI_VA_DV2810 Execution Slots: SLOT01232811 ========================================================================== */2812 2813#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu)2814#endif /* __HEXAGON_ARCH___ >= 60 */2815 2816#if __HVX_ARCH__ >= 602817/* ==========================================================================2818 Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h)2819 C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv)2820 Instruction Type: CVI_VA2821 Execution Slots: SLOT01232822 ========================================================================== */2823 2824#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv)2825#endif /* __HEXAGON_ARCH___ >= 60 */2826 2827#if __HVX_ARCH__ >= 602828/* ==========================================================================2829 Assembly Syntax: Vd32.b=vshuff(Vu32.b)2830 C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu)2831 Instruction Type: CVI_VP2832 Execution Slots: SLOT01232833 ========================================================================== */2834 2835#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu)2836#endif /* __HEXAGON_ARCH___ >= 60 */2837 2838#if __HVX_ARCH__ >= 602839/* ==========================================================================2840 Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b)2841 C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv)2842 Instruction Type: CVI_VA2843 Execution Slots: SLOT01232844 ========================================================================== */2845 2846#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv)2847#endif /* __HEXAGON_ARCH___ >= 60 */2848 2849#if __HVX_ARCH__ >= 602850/* ==========================================================================2851 Assembly Syntax: Vd32.h=vshuff(Vu32.h)2852 C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu)2853 Instruction Type: CVI_VP2854 Execution Slots: SLOT01232855 ========================================================================== */2856 2857#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu)2858#endif /* __HEXAGON_ARCH___ >= 60 */2859 2860#if __HVX_ARCH__ >= 602861/* ==========================================================================2862 Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b)2863 C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv)2864 Instruction Type: CVI_VA2865 Execution Slots: SLOT01232866 ========================================================================== */2867 2868#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv)2869#endif /* __HEXAGON_ARCH___ >= 60 */2870 2871#if __HVX_ARCH__ >= 602872/* ==========================================================================2873 Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8)2874 C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)2875 Instruction Type: CVI_VP_VS2876 Execution Slots: SLOT01232877 ========================================================================== */2878 2879#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt)2880#endif /* __HEXAGON_ARCH___ >= 60 */2881 2882#if __HVX_ARCH__ >= 602883/* ==========================================================================2884 Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b)2885 C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv)2886 Instruction Type: CVI_VA_DV2887 Execution Slots: SLOT01232888 ========================================================================== */2889 2890#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv)2891#endif /* __HEXAGON_ARCH___ >= 60 */2892 2893#if __HVX_ARCH__ >= 602894/* ==========================================================================2895 Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h)2896 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv)2897 Instruction Type: CVI_VA_DV2898 Execution Slots: SLOT01232899 ========================================================================== */2900 2901#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv)2902#endif /* __HEXAGON_ARCH___ >= 60 */2903 2904#if __HVX_ARCH__ >= 602905/* ==========================================================================2906 Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h)2907 C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv)2908 Instruction Type: CVI_VA2909 Execution Slots: SLOT01232910 ========================================================================== */2911 2912#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv)2913#endif /* __HEXAGON_ARCH___ >= 60 */2914 2915#if __HVX_ARCH__ >= 602916/* ==========================================================================2917 Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b)2918 C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv)2919 Instruction Type: CVI_VA2920 Execution Slots: SLOT01232921 ========================================================================== */2922 2923#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv)2924#endif /* __HEXAGON_ARCH___ >= 60 */2925 2926#if __HVX_ARCH__ >= 602927/* ==========================================================================2928 Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b)2929 C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)2930 Instruction Type: CVI_VA_DV2931 Execution Slots: SLOT01232932 ========================================================================== */2933 2934#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv)2935#endif /* __HEXAGON_ARCH___ >= 60 */2936 2937#if __HVX_ARCH__ >= 602938/* ==========================================================================2939 Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b2940 C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)2941 Instruction Type: CVI_VA2942 Execution Slots: SLOT01232943 ========================================================================== */2944 2945#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)2946#endif /* __HEXAGON_ARCH___ >= 60 */2947 2948#if __HVX_ARCH__ >= 602949/* ==========================================================================2950 Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b2951 C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)2952 Instruction Type: CVI_VA2953 Execution Slots: SLOT01232954 ========================================================================== */2955 2956#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)2957#endif /* __HEXAGON_ARCH___ >= 60 */2958 2959#if __HVX_ARCH__ >= 602960/* ==========================================================================2961 Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h)2962 C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)2963 Instruction Type: CVI_VA2964 Execution Slots: SLOT01232965 ========================================================================== */2966 2967#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv)2968#endif /* __HEXAGON_ARCH___ >= 60 */2969 2970#if __HVX_ARCH__ >= 602971/* ==========================================================================2972 Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h)2973 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)2974 Instruction Type: CVI_VA_DV2975 Execution Slots: SLOT01232976 ========================================================================== */2977 2978#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv)2979#endif /* __HEXAGON_ARCH___ >= 60 */2980 2981#if __HVX_ARCH__ >= 602982/* ==========================================================================2983 Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h2984 C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)2985 Instruction Type: CVI_VA2986 Execution Slots: SLOT01232987 ========================================================================== */2988 2989#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)2990#endif /* __HEXAGON_ARCH___ >= 60 */2991 2992#if __HVX_ARCH__ >= 602993/* ==========================================================================2994 Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h2995 C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)2996 Instruction Type: CVI_VA2997 Execution Slots: SLOT01232998 ========================================================================== */2999 3000#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)3001#endif /* __HEXAGON_ARCH___ >= 60 */3002 3003#if __HVX_ARCH__ >= 603004/* ==========================================================================3005 Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat3006 C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)3007 Instruction Type: CVI_VA3008 Execution Slots: SLOT01233009 ========================================================================== */3010 3011#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv)3012#endif /* __HEXAGON_ARCH___ >= 60 */3013 3014#if __HVX_ARCH__ >= 603015/* ==========================================================================3016 Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat3017 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3018 Instruction Type: CVI_VA_DV3019 Execution Slots: SLOT01233020 ========================================================================== */3021 3022#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv)3023#endif /* __HEXAGON_ARCH___ >= 60 */3024 3025#if __HVX_ARCH__ >= 603026/* ==========================================================================3027 Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h)3028 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)3029 Instruction Type: CVI_VX_DV3030 Execution Slots: SLOT233031 ========================================================================== */3032 3033#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv)3034#endif /* __HEXAGON_ARCH___ >= 60 */3035 3036#if __HVX_ARCH__ >= 603037/* ==========================================================================3038 Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub)3039 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv)3040 Instruction Type: CVI_VX_DV3041 Execution Slots: SLOT233042 ========================================================================== */3043 3044#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv)3045#endif /* __HEXAGON_ARCH___ >= 60 */3046 3047#if __HVX_ARCH__ >= 603048/* ==========================================================================3049 Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat3050 C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)3051 Instruction Type: CVI_VA3052 Execution Slots: SLOT01233053 ========================================================================== */3054 3055#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv)3056#endif /* __HEXAGON_ARCH___ >= 60 */3057 3058#if __HVX_ARCH__ >= 603059/* ==========================================================================3060 Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat3061 C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3062 Instruction Type: CVI_VA_DV3063 Execution Slots: SLOT01233064 ========================================================================== */3065 3066#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv)3067#endif /* __HEXAGON_ARCH___ >= 60 */3068 3069#if __HVX_ARCH__ >= 603070/* ==========================================================================3071 Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat3072 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)3073 Instruction Type: CVI_VA3074 Execution Slots: SLOT01233075 ========================================================================== */3076 3077#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv)3078#endif /* __HEXAGON_ARCH___ >= 60 */3079 3080#if __HVX_ARCH__ >= 603081/* ==========================================================================3082 Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat3083 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3084 Instruction Type: CVI_VA_DV3085 Execution Slots: SLOT01233086 ========================================================================== */3087 3088#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv)3089#endif /* __HEXAGON_ARCH___ >= 60 */3090 3091#if __HVX_ARCH__ >= 603092/* ==========================================================================3093 Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh)3094 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)3095 Instruction Type: CVI_VX_DV3096 Execution Slots: SLOT233097 ========================================================================== */3098 3099#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv)3100#endif /* __HEXAGON_ARCH___ >= 60 */3101 3102#if __HVX_ARCH__ >= 603103/* ==========================================================================3104 Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w)3105 C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv)3106 Instruction Type: CVI_VA3107 Execution Slots: SLOT01233108 ========================================================================== */3109 3110#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv)3111#endif /* __HEXAGON_ARCH___ >= 60 */3112 3113#if __HVX_ARCH__ >= 603114/* ==========================================================================3115 Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w)3116 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3117 Instruction Type: CVI_VA_DV3118 Execution Slots: SLOT01233119 ========================================================================== */3120 3121#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv)3122#endif /* __HEXAGON_ARCH___ >= 60 */3123 3124#if __HVX_ARCH__ >= 603125/* ==========================================================================3126 Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w3127 C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)3128 Instruction Type: CVI_VA3129 Execution Slots: SLOT01233130 ========================================================================== */3131 3132#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)3133#endif /* __HEXAGON_ARCH___ >= 60 */3134 3135#if __HVX_ARCH__ >= 603136/* ==========================================================================3137 Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w3138 C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)3139 Instruction Type: CVI_VA3140 Execution Slots: SLOT01233141 ========================================================================== */3142 3143#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)3144#endif /* __HEXAGON_ARCH___ >= 60 */3145 3146#if __HVX_ARCH__ >= 603147/* ==========================================================================3148 Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat3149 C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)3150 Instruction Type: CVI_VA3151 Execution Slots: SLOT01233152 ========================================================================== */3153 3154#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv)3155#endif /* __HEXAGON_ARCH___ >= 60 */3156 3157#if __HVX_ARCH__ >= 603158/* ==========================================================================3159 Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat3160 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3161 Instruction Type: CVI_VA_DV3162 Execution Slots: SLOT01233163 ========================================================================== */3164 3165#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv)3166#endif /* __HEXAGON_ARCH___ >= 60 */3167 3168#if __HVX_ARCH__ >= 603169/* ==========================================================================3170 Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32)3171 C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)3172 Instruction Type: CVI_VA_DV3173 Execution Slots: SLOT01233174 ========================================================================== */3175 3176#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv)3177#endif /* __HEXAGON_ARCH___ >= 60 */3178 3179#if __HVX_ARCH__ >= 603180/* ==========================================================================3181 Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b)3182 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt)3183 Instruction Type: CVI_VX_DV3184 Execution Slots: SLOT233185 ========================================================================== */3186 3187#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt)3188#endif /* __HEXAGON_ARCH___ >= 60 */3189 3190#if __HVX_ARCH__ >= 603191/* ==========================================================================3192 Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)3193 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)3194 Instruction Type: CVI_VX_DV3195 Execution Slots: SLOT233196 ========================================================================== */3197 3198#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt)3199#endif /* __HEXAGON_ARCH___ >= 60 */3200 3201#if __HVX_ARCH__ >= 603202/* ==========================================================================3203 Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)3204 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)3205 Instruction Type: CVI_VX_DV3206 Execution Slots: SLOT233207 ========================================================================== */3208 3209#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt)3210#endif /* __HEXAGON_ARCH___ >= 60 */3211 3212#if __HVX_ARCH__ >= 603213/* ==========================================================================3214 Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)3215 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)3216 Instruction Type: CVI_VX_DV3217 Execution Slots: SLOT233218 ========================================================================== */3219 3220#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt)3221#endif /* __HEXAGON_ARCH___ >= 60 */3222 3223#if __HVX_ARCH__ >= 603224/* ==========================================================================3225 Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b)3226 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)3227 Instruction Type: CVI_VX_DV3228 Execution Slots: SLOT233229 ========================================================================== */3230 3231#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt)3232#endif /* __HEXAGON_ARCH___ >= 60 */3233 3234#if __HVX_ARCH__ >= 603235/* ==========================================================================3236 Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)3237 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)3238 Instruction Type: CVI_VX_DV3239 Execution Slots: SLOT233240 ========================================================================== */3241 3242#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt)3243#endif /* __HEXAGON_ARCH___ >= 60 */3244 3245#if __HVX_ARCH__ >= 603246/* ==========================================================================3247 Assembly Syntax: Vdd32.h=vunpack(Vu32.b)3248 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu)3249 Instruction Type: CVI_VP_VS3250 Execution Slots: SLOT01233251 ========================================================================== */3252 3253#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu)3254#endif /* __HEXAGON_ARCH___ >= 60 */3255 3256#if __HVX_ARCH__ >= 603257/* ==========================================================================3258 Assembly Syntax: Vdd32.w=vunpack(Vu32.h)3259 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu)3260 Instruction Type: CVI_VP_VS3261 Execution Slots: SLOT01233262 ========================================================================== */3263 3264#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu)3265#endif /* __HEXAGON_ARCH___ >= 60 */3266 3267#if __HVX_ARCH__ >= 603268/* ==========================================================================3269 Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b)3270 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu)3271 Instruction Type: CVI_VP_VS3272 Execution Slots: SLOT01233273 ========================================================================== */3274 3275#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu)3276#endif /* __HEXAGON_ARCH___ >= 60 */3277 3278#if __HVX_ARCH__ >= 603279/* ==========================================================================3280 Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h)3281 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu)3282 Instruction Type: CVI_VP_VS3283 Execution Slots: SLOT01233284 ========================================================================== */3285 3286#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu)3287#endif /* __HEXAGON_ARCH___ >= 60 */3288 3289#if __HVX_ARCH__ >= 603290/* ==========================================================================3291 Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub)3292 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu)3293 Instruction Type: CVI_VP_VS3294 Execution Slots: SLOT01233295 ========================================================================== */3296 3297#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu)3298#endif /* __HEXAGON_ARCH___ >= 60 */3299 3300#if __HVX_ARCH__ >= 603301/* ==========================================================================3302 Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh)3303 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu)3304 Instruction Type: CVI_VP_VS3305 Execution Slots: SLOT01233306 ========================================================================== */3307 3308#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu)3309#endif /* __HEXAGON_ARCH___ >= 60 */3310 3311#if __HVX_ARCH__ >= 603312/* ==========================================================================3313 Assembly Syntax: Vd32=vxor(Vu32,Vv32)3314 C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv)3315 Instruction Type: CVI_VA3316 Execution Slots: SLOT01233317 ========================================================================== */3318 3319#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv)3320#endif /* __HEXAGON_ARCH___ >= 60 */3321 3322#if __HVX_ARCH__ >= 603323/* ==========================================================================3324 Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub)3325 C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu)3326 Instruction Type: CVI_VA_DV3327 Execution Slots: SLOT01233328 ========================================================================== */3329 3330#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu)3331#endif /* __HEXAGON_ARCH___ >= 60 */3332 3333#if __HVX_ARCH__ >= 603334/* ==========================================================================3335 Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh)3336 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu)3337 Instruction Type: CVI_VA_DV3338 Execution Slots: SLOT01233339 ========================================================================== */3340 3341#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu)3342#endif /* __HEXAGON_ARCH___ >= 60 */3343 3344#if __HVX_ARCH__ >= 623345/* ==========================================================================3346 Assembly Syntax: Vd32.b=vsplat(Rt32)3347 C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt)3348 Instruction Type: CVI_VX_LATE3349 Execution Slots: SLOT233350 ========================================================================== */3351 3352#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt)3353#endif /* __HEXAGON_ARCH___ >= 62 */3354 3355#if __HVX_ARCH__ >= 623356/* ==========================================================================3357 Assembly Syntax: Vd32.h=vsplat(Rt32)3358 C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt)3359 Instruction Type: CVI_VX_LATE3360 Execution Slots: SLOT233361 ========================================================================== */3362 3363#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt)3364#endif /* __HEXAGON_ARCH___ >= 62 */3365 3366#if __HVX_ARCH__ >= 623367/* ==========================================================================3368 Assembly Syntax: Qd4=vsetq2(Rt32)3369 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt)3370 Instruction Type: CVI_VP3371 Execution Slots: SLOT01233372 ========================================================================== */3373 3374#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1)3375#endif /* __HEXAGON_ARCH___ >= 62 */3376 3377#if __HVX_ARCH__ >= 623378/* ==========================================================================3379 Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h)3380 C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt)3381 Instruction Type: CVI_VA_DV3382 Execution Slots: SLOT01233383 ========================================================================== */3384 3385#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)3386#endif /* __HEXAGON_ARCH___ >= 62 */3387 3388#if __HVX_ARCH__ >= 623389/* ==========================================================================3390 Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w)3391 C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt)3392 Instruction Type: CVI_VA_DV3393 Execution Slots: SLOT01233394 ========================================================================== */3395 3396#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)3397#endif /* __HEXAGON_ARCH___ >= 62 */3398 3399#if __HVX_ARCH__ >= 623400/* ==========================================================================3401 Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat3402 C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)3403 Instruction Type: CVI_VA3404 Execution Slots: SLOT01233405 ========================================================================== */3406 3407#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv)3408#endif /* __HEXAGON_ARCH___ >= 62 */3409 3410#if __HVX_ARCH__ >= 623411/* ==========================================================================3412 Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat3413 C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3414 Instruction Type: CVI_VA_DV3415 Execution Slots: SLOT01233416 ========================================================================== */3417 3418#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv)3419#endif /* __HEXAGON_ARCH___ >= 62 */3420 3421#if __HVX_ARCH__ >= 623422/* ==========================================================================3423 Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry3424 C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)3425 Instruction Type: CVI_VA3426 Execution Slots: SLOT01233427 ========================================================================== */3428 3429#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx)3430#endif /* __HEXAGON_ARCH___ >= 62 */3431 3432#if __HVX_ARCH__ >= 623433/* ==========================================================================3434 Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h)3435 C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv)3436 Instruction Type: CVI_VS3437 Execution Slots: SLOT01233438 ========================================================================== */3439 3440#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv)3441#endif /* __HEXAGON_ARCH___ >= 62 */3442 3443#if __HVX_ARCH__ >= 623444/* ==========================================================================3445 Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w)3446 C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv)3447 Instruction Type: CVI_VS3448 Execution Slots: SLOT01233449 ========================================================================== */3450 3451#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv)3452#endif /* __HEXAGON_ARCH___ >= 62 */3453 3454#if __HVX_ARCH__ >= 623455/* ==========================================================================3456 Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h)3457 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)3458 Instruction Type: CVI_VX_DV3459 Execution Slots: SLOT233460 ========================================================================== */3461 3462#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv)3463#endif /* __HEXAGON_ARCH___ >= 62 */3464 3465#if __HVX_ARCH__ >= 623466/* ==========================================================================3467 Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub)3468 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)3469 Instruction Type: CVI_VX_DV3470 Execution Slots: SLOT233471 ========================================================================== */3472 3473#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv)3474#endif /* __HEXAGON_ARCH___ >= 62 */3475 3476#if __HVX_ARCH__ >= 623477/* ==========================================================================3478 Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat3479 C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)3480 Instruction Type: CVI_VA3481 Execution Slots: SLOT01233482 ========================================================================== */3483 3484#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv)3485#endif /* __HEXAGON_ARCH___ >= 62 */3486 3487#if __HVX_ARCH__ >= 623488/* ==========================================================================3489 Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh)3490 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)3491 Instruction Type: CVI_VX_DV3492 Execution Slots: SLOT233493 ========================================================================== */3494 3495#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv)3496#endif /* __HEXAGON_ARCH___ >= 62 */3497 3498#if __HVX_ARCH__ >= 623499/* ==========================================================================3500 Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat3501 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)3502 Instruction Type: CVI_VA3503 Execution Slots: SLOT01233504 ========================================================================== */3505 3506#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv)3507#endif /* __HEXAGON_ARCH___ >= 62 */3508 3509#if __HVX_ARCH__ >= 623510/* ==========================================================================3511 Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat3512 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3513 Instruction Type: CVI_VA_DV3514 Execution Slots: SLOT01233515 ========================================================================== */3516 3517#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv)3518#endif /* __HEXAGON_ARCH___ >= 62 */3519 3520#if __HVX_ARCH__ >= 623521/* ==========================================================================3522 Assembly Syntax: Vd32=vand(!Qu4,Rt32)3523 C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt)3524 Instruction Type: CVI_VX_LATE3525 Execution Slots: SLOT233526 ========================================================================== */3527 3528#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)3529#endif /* __HEXAGON_ARCH___ >= 62 */3530 3531#if __HVX_ARCH__ >= 623532/* ==========================================================================3533 Assembly Syntax: Vx32|=vand(!Qu4,Rt32)3534 C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)3535 Instruction Type: CVI_VX_LATE3536 Execution Slots: SLOT233537 ========================================================================== */3538 3539#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt)3540#endif /* __HEXAGON_ARCH___ >= 62 */3541 3542#if __HVX_ARCH__ >= 623543/* ==========================================================================3544 Assembly Syntax: Vd32=vand(!Qv4,Vu32)3545 C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu)3546 Instruction Type: CVI_VA3547 Execution Slots: SLOT01233548 ========================================================================== */3549 3550#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)3551#endif /* __HEXAGON_ARCH___ >= 62 */3552 3553#if __HVX_ARCH__ >= 623554/* ==========================================================================3555 Assembly Syntax: Vd32=vand(Qv4,Vu32)3556 C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu)3557 Instruction Type: CVI_VA3558 Execution Slots: SLOT01233559 ========================================================================== */3560 3561#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu)3562#endif /* __HEXAGON_ARCH___ >= 62 */3563 3564#if __HVX_ARCH__ >= 623565/* ==========================================================================3566 Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat3567 C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3568 Instruction Type: CVI_VS3569 Execution Slots: SLOT01233570 ========================================================================== */3571 3572#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt)3573#endif /* __HEXAGON_ARCH___ >= 62 */3574 3575#if __HVX_ARCH__ >= 623576/* ==========================================================================3577 Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat3578 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3579 Instruction Type: CVI_VS3580 Execution Slots: SLOT01233581 ========================================================================== */3582 3583#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt)3584#endif /* __HEXAGON_ARCH___ >= 62 */3585 3586#if __HVX_ARCH__ >= 623587/* ==========================================================================3588 Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat3589 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3590 Instruction Type: CVI_VS3591 Execution Slots: SLOT01233592 ========================================================================== */3593 3594#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt)3595#endif /* __HEXAGON_ARCH___ >= 62 */3596 3597#if __HVX_ARCH__ >= 623598/* ==========================================================================3599 Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32)3600 C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt)3601 Instruction Type: CVI_VS3602 Execution Slots: SLOT01233603 ========================================================================== */3604 3605#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt)3606#endif /* __HEXAGON_ARCH___ >= 62 */3607 3608#if __HVX_ARCH__ >= 623609/* ==========================================================================3610 Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch3611 C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3612 Instruction Type: CVI_VP3613 Execution Slots: SLOT01233614 ========================================================================== */3615 3616#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt)3617#endif /* __HEXAGON_ARCH___ >= 62 */3618 3619#if __HVX_ARCH__ >= 623620/* ==========================================================================3621 Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)3622 C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)3623 Instruction Type: CVI_VP_VS3624 Execution Slots: SLOT01233625 ========================================================================== */3626 3627#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3)3628#endif /* __HEXAGON_ARCH___ >= 62 */3629 3630#if __HVX_ARCH__ >= 623631/* ==========================================================================3632 Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)3633 C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)3634 Instruction Type: CVI_VP3635 Execution Slots: SLOT01233636 ========================================================================== */3637 3638#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3)3639#endif /* __HEXAGON_ARCH___ >= 62 */3640 3641#if __HVX_ARCH__ >= 623642/* ==========================================================================3643 Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch3644 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3645 Instruction Type: CVI_VP_VS3646 Execution Slots: SLOT01233647 ========================================================================== */3648 3649#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt)3650#endif /* __HEXAGON_ARCH___ >= 62 */3651 3652#if __HVX_ARCH__ >= 623653/* ==========================================================================3654 Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)3655 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)3656 Instruction Type: CVI_VP_VS3657 Execution Slots: SLOT01233658 ========================================================================== */3659 3660#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3)3661#endif /* __HEXAGON_ARCH___ >= 62 */3662 3663#if __HVX_ARCH__ >= 623664/* ==========================================================================3665 Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)3666 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)3667 Instruction Type: CVI_VP_VS3668 Execution Slots: SLOT01233669 ========================================================================== */3670 3671#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3)3672#endif /* __HEXAGON_ARCH___ >= 62 */3673 3674#if __HVX_ARCH__ >= 623675/* ==========================================================================3676 Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b)3677 C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv)3678 Instruction Type: CVI_VA3679 Execution Slots: SLOT01233680 ========================================================================== */3681 3682#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv)3683#endif /* __HEXAGON_ARCH___ >= 62 */3684 3685#if __HVX_ARCH__ >= 623686/* ==========================================================================3687 Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b)3688 C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv)3689 Instruction Type: CVI_VA3690 Execution Slots: SLOT01233691 ========================================================================== */3692 3693#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv)3694#endif /* __HEXAGON_ARCH___ >= 62 */3695 3696#if __HVX_ARCH__ >= 623697/* ==========================================================================3698 Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b)3699 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt)3700 Instruction Type: CVI_VX_DV3701 Execution Slots: SLOT233702 ========================================================================== */3703 3704#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt)3705#endif /* __HEXAGON_ARCH___ >= 62 */3706 3707#if __HVX_ARCH__ >= 623708/* ==========================================================================3709 Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)3710 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)3711 Instruction Type: CVI_VX_DV3712 Execution Slots: SLOT233713 ========================================================================== */3714 3715#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt)3716#endif /* __HEXAGON_ARCH___ >= 62 */3717 3718#if __HVX_ARCH__ >= 623719/* ==========================================================================3720 Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh)3721 C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)3722 Instruction Type: CVI_VX_DV3723 Execution Slots: SLOT233724 ========================================================================== */3725 3726#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv)3727#endif /* __HEXAGON_ARCH___ >= 62 */3728 3729#if __HVX_ARCH__ >= 623730/* ==========================================================================3731 Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub)3732 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt)3733 Instruction Type: CVI_VX3734 Execution Slots: SLOT233735 ========================================================================== */3736 3737#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt)3738#endif /* __HEXAGON_ARCH___ >= 62 */3739 3740#if __HVX_ARCH__ >= 623741/* ==========================================================================3742 Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub)3743 C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)3744 Instruction Type: CVI_VX3745 Execution Slots: SLOT233746 ========================================================================== */3747 3748#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt)3749#endif /* __HEXAGON_ARCH___ >= 62 */3750 3751#if __HVX_ARCH__ >= 623752/* ==========================================================================3753 Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h)3754 C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)3755 Instruction Type: CVI_VX_DV3756 Execution Slots: SLOT233757 ========================================================================== */3758 3759#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv)3760#endif /* __HEXAGON_ARCH___ >= 62 */3761 3762#if __HVX_ARCH__ >= 623763/* ==========================================================================3764 Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat3765 C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)3766 Instruction Type: CVI_VS3767 Execution Slots: SLOT01233768 ========================================================================== */3769 3770#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv)3771#endif /* __HEXAGON_ARCH___ >= 62 */3772 3773#if __HVX_ARCH__ >= 623774/* ==========================================================================3775 Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat3776 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)3777 Instruction Type: CVI_VS3778 Execution Slots: SLOT01233779 ========================================================================== */3780 3781#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv)3782#endif /* __HEXAGON_ARCH___ >= 62 */3783 3784#if __HVX_ARCH__ >= 623785/* ==========================================================================3786 Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw)3787 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)3788 Instruction Type: CVI_VA3789 Execution Slots: SLOT01233790 ========================================================================== */3791 3792#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv)3793#endif /* __HEXAGON_ARCH___ >= 62 */3794 3795#if __HVX_ARCH__ >= 623796/* ==========================================================================3797 Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat3798 C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)3799 Instruction Type: CVI_VA3800 Execution Slots: SLOT01233801 ========================================================================== */3802 3803#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv)3804#endif /* __HEXAGON_ARCH___ >= 62 */3805 3806#if __HVX_ARCH__ >= 623807/* ==========================================================================3808 Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat3809 C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3810 Instruction Type: CVI_VA_DV3811 Execution Slots: SLOT01233812 ========================================================================== */3813 3814#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv)3815#endif /* __HEXAGON_ARCH___ >= 62 */3816 3817#if __HVX_ARCH__ >= 623818/* ==========================================================================3819 Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry3820 C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)3821 Instruction Type: CVI_VA3822 Execution Slots: SLOT01233823 ========================================================================== */3824 3825#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx)3826#endif /* __HEXAGON_ARCH___ >= 62 */3827 3828#if __HVX_ARCH__ >= 623829/* ==========================================================================3830 Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat3831 C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)3832 Instruction Type: CVI_VA3833 Execution Slots: SLOT01233834 ========================================================================== */3835 3836#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv)3837#endif /* __HEXAGON_ARCH___ >= 62 */3838 3839#if __HVX_ARCH__ >= 623840/* ==========================================================================3841 Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat3842 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)3843 Instruction Type: CVI_VA3844 Execution Slots: SLOT01233845 ========================================================================== */3846 3847#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv)3848#endif /* __HEXAGON_ARCH___ >= 62 */3849 3850#if __HVX_ARCH__ >= 623851/* ==========================================================================3852 Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat3853 C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)3854 Instruction Type: CVI_VA_DV3855 Execution Slots: SLOT01233856 ========================================================================== */3857 3858#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv)3859#endif /* __HEXAGON_ARCH___ >= 62 */3860 3861#if __HVX_ARCH__ >= 653862/* ==========================================================================3863 Assembly Syntax: Vd32.b=vabs(Vu32.b)3864 C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu)3865 Instruction Type: CVI_VA3866 Execution Slots: SLOT01233867 ========================================================================== */3868 3869#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu)3870#endif /* __HEXAGON_ARCH___ >= 65 */3871 3872#if __HVX_ARCH__ >= 653873/* ==========================================================================3874 Assembly Syntax: Vd32.b=vabs(Vu32.b):sat3875 C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu)3876 Instruction Type: CVI_VA3877 Execution Slots: SLOT01233878 ========================================================================== */3879 3880#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu)3881#endif /* __HEXAGON_ARCH___ >= 65 */3882 3883#if __HVX_ARCH__ >= 653884/* ==========================================================================3885 Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32)3886 C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)3887 Instruction Type: CVI_VS3888 Execution Slots: SLOT01233889 ========================================================================== */3890 3891#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt)3892#endif /* __HEXAGON_ARCH___ >= 65 */3893 3894#if __HVX_ARCH__ >= 653895/* ==========================================================================3896 Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32)3897 C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)3898 Instruction Type: CVI_VS3899 Execution Slots: SLOT01233900 ========================================================================== */3901 3902#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt)3903#endif /* __HEXAGON_ARCH___ >= 65 */3904 3905#if __HVX_ARCH__ >= 653906/* ==========================================================================3907 Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat3908 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3909 Instruction Type: CVI_VS3910 Execution Slots: SLOT01233911 ========================================================================== */3912 3913#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt)3914#endif /* __HEXAGON_ARCH___ >= 65 */3915 3916#if __HVX_ARCH__ >= 653917/* ==========================================================================3918 Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat3919 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3920 Instruction Type: CVI_VS3921 Execution Slots: SLOT01233922 ========================================================================== */3923 3924#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt)3925#endif /* __HEXAGON_ARCH___ >= 65 */3926 3927#if __HVX_ARCH__ >= 653928/* ==========================================================================3929 Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat3930 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)3931 Instruction Type: CVI_VS3932 Execution Slots: SLOT01233933 ========================================================================== */3934 3935#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt)3936#endif /* __HEXAGON_ARCH___ >= 65 */3937 3938#if __HVX_ARCH__ >= 653939/* ==========================================================================3940 Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b)3941 C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)3942 Instruction Type: CVI_VA3943 Execution Slots: SLOT01233944 ========================================================================== */3945 3946#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv)3947#endif /* __HEXAGON_ARCH___ >= 65 */3948 3949#if __HVX_ARCH__ >= 653950/* ==========================================================================3951 Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd3952 C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv)3953 Instruction Type: CVI_VA3954 Execution Slots: SLOT01233955 ========================================================================== */3956 3957#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv)3958#endif /* __HEXAGON_ARCH___ >= 65 */3959 3960#if __HVX_ARCH__ >= 653961/* ==========================================================================3962 Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw)3963 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)3964 Instruction Type: CVI_VA3965 Execution Slots: SLOT01233966 ========================================================================== */3967 3968#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv)3969#endif /* __HEXAGON_ARCH___ >= 65 */3970 3971#if __HVX_ARCH__ >= 653972/* ==========================================================================3973 Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd3974 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv)3975 Instruction Type: CVI_VA3976 Execution Slots: SLOT01233977 ========================================================================== */3978 3979#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv)3980#endif /* __HEXAGON_ARCH___ >= 65 */3981 3982#if __HVX_ARCH__ >= 653983/* ==========================================================================3984 Assembly Syntax: Vdd32=#03985 C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero()3986 Instruction Type: MAPPING3987 Execution Slots: SLOT01233988 ========================================================================== */3989 3990#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)()3991#endif /* __HEXAGON_ARCH___ >= 65 */3992 3993#if __HVX_ARCH__ >= 653994/* ==========================================================================3995 Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h3996 C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)3997 Instruction Type: CVI_GATHER3998 Execution Slots: SLOT013999 ========================================================================== */4000 4001#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv)4002#endif /* __HEXAGON_ARCH___ >= 65 */4003 4004#if __HVX_ARCH__ >= 654005/* ==========================================================================4006 Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h4007 C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)4008 Instruction Type: CVI_GATHER4009 Execution Slots: SLOT014010 ========================================================================== */4011 4012#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)4013#endif /* __HEXAGON_ARCH___ >= 65 */4014 4015#if __HVX_ARCH__ >= 654016/* ==========================================================================4017 Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h4018 C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)4019 Instruction Type: CVI_GATHER_DV4020 Execution Slots: SLOT014021 ========================================================================== */4022 4023#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv)4024#endif /* __HEXAGON_ARCH___ >= 65 */4025 4026#if __HVX_ARCH__ >= 654027/* ==========================================================================4028 Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h4029 C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)4030 Instruction Type: CVI_GATHER_DV4031 Execution Slots: SLOT014032 ========================================================================== */4033 4034#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv)4035#endif /* __HEXAGON_ARCH___ >= 65 */4036 4037#if __HVX_ARCH__ >= 654038/* ==========================================================================4039 Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w4040 C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)4041 Instruction Type: CVI_GATHER4042 Execution Slots: SLOT014043 ========================================================================== */4044 4045#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv)4046#endif /* __HEXAGON_ARCH___ >= 65 */4047 4048#if __HVX_ARCH__ >= 654049/* ==========================================================================4050 Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w4051 C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)4052 Instruction Type: CVI_GATHER4053 Execution Slots: SLOT014054 ========================================================================== */4055 4056#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv)4057#endif /* __HEXAGON_ARCH___ >= 65 */4058 4059#if __HVX_ARCH__ >= 654060/* ==========================================================================4061 Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h)4062 C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt)4063 Instruction Type: CVI_VX_DV4064 Execution Slots: SLOT24065 ========================================================================== */4066 4067#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt)4068#endif /* __HEXAGON_ARCH___ >= 65 */4069 4070#if __HVX_ARCH__ >= 654071/* ==========================================================================4072 Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)4073 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt)4074 Instruction Type: CVI_VX_DV4075 Execution Slots: SLOT234076 ========================================================================== */4077 4078#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt)4079#endif /* __HEXAGON_ARCH___ >= 65 */4080 4081#if __HVX_ARCH__ >= 654082/* ==========================================================================4083 Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)4084 C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)4085 Instruction Type: CVI_VX_DV4086 Execution Slots: SLOT234087 ========================================================================== */4088 4089#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt)4090#endif /* __HEXAGON_ARCH___ >= 65 */4091 4092#if __HVX_ARCH__ >= 654093/* ==========================================================================4094 Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat4095 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)4096 Instruction Type: CVI_VX_DV4097 Execution Slots: SLOT24098 ========================================================================== */4099 4100#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt)4101#endif /* __HEXAGON_ARCH___ >= 65 */4102 4103#if __HVX_ARCH__ >= 654104/* ==========================================================================4105 Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat4106 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)4107 Instruction Type: CVI_VX_DV4108 Execution Slots: SLOT24109 ========================================================================== */4110 4111#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt)4112#endif /* __HEXAGON_ARCH___ >= 65 */4113 4114#if __HVX_ARCH__ >= 654115/* ==========================================================================4116 Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat4117 C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)4118 Instruction Type: CVI_VX_DV4119 Execution Slots: SLOT24120 ========================================================================== */4121 4122#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt)4123#endif /* __HEXAGON_ARCH___ >= 65 */4124 4125#if __HVX_ARCH__ >= 654126/* ==========================================================================4127 Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h)4128 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)4129 Instruction Type: CVI_VX_DV4130 Execution Slots: SLOT234131 ========================================================================== */4132 4133#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt)4134#endif /* __HEXAGON_ARCH___ >= 65 */4135 4136#if __HVX_ARCH__ >= 654137/* ==========================================================================4138 Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh)4139 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt)4140 Instruction Type: CVI_VX4141 Execution Slots: SLOT234142 ========================================================================== */4143 4144#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt)4145#endif /* __HEXAGON_ARCH___ >= 65 */4146 4147#if __HVX_ARCH__ >= 654148/* ==========================================================================4149 Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)4150 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)4151 Instruction Type: CVI_VX4152 Execution Slots: SLOT234153 ========================================================================== */4154 4155#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt)4156#endif /* __HEXAGON_ARCH___ >= 65 */4157 4158#if __HVX_ARCH__ >= 654159/* ==========================================================================4160 Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b)4161 C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)4162 Instruction Type: CVI_VA4163 Execution Slots: SLOT01234164 ========================================================================== */4165 4166#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv)4167#endif /* __HEXAGON_ARCH___ >= 65 */4168 4169#if __HVX_ARCH__ >= 654170/* ==========================================================================4171 Assembly Syntax: Vd32.b=prefixsum(Qv4)4172 C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv)4173 Instruction Type: CVI_VS4174 Execution Slots: SLOT01234175 ========================================================================== */4176 4177#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))4178#endif /* __HEXAGON_ARCH___ >= 65 */4179 4180#if __HVX_ARCH__ >= 654181/* ==========================================================================4182 Assembly Syntax: Vd32.h=prefixsum(Qv4)4183 C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv)4184 Instruction Type: CVI_VS4185 Execution Slots: SLOT01234186 ========================================================================== */4187 4188#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))4189#endif /* __HEXAGON_ARCH___ >= 65 */4190 4191#if __HVX_ARCH__ >= 654192/* ==========================================================================4193 Assembly Syntax: Vd32.w=prefixsum(Qv4)4194 C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv)4195 Instruction Type: CVI_VS4196 Execution Slots: SLOT01234197 ========================================================================== */4198 4199#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1))4200#endif /* __HEXAGON_ARCH___ >= 65 */4201 4202#if __HVX_ARCH__ >= 654203/* ==========================================================================4204 Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw324205 C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4206 Instruction Type: CVI_SCATTER4207 Execution Slots: SLOT04208 ========================================================================== */4209 4210#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw)4211#endif /* __HEXAGON_ARCH___ >= 65 */4212 4213#if __HVX_ARCH__ >= 654214/* ==========================================================================4215 Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw324216 C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4217 Instruction Type: CVI_SCATTER4218 Execution Slots: SLOT04219 ========================================================================== */4220 4221#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw)4222#endif /* __HEXAGON_ARCH___ >= 65 */4223 4224#if __HVX_ARCH__ >= 654225/* ==========================================================================4226 Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw324227 C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4228 Instruction Type: CVI_SCATTER4229 Execution Slots: SLOT04230 ========================================================================== */4231 4232#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)4233#endif /* __HEXAGON_ARCH___ >= 65 */4234 4235#if __HVX_ARCH__ >= 654236/* ==========================================================================4237 Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw324238 C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)4239 Instruction Type: CVI_SCATTER_DV4240 Execution Slots: SLOT04241 ========================================================================== */4242 4243#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw)4244#endif /* __HEXAGON_ARCH___ >= 65 */4245 4246#if __HVX_ARCH__ >= 654247/* ==========================================================================4248 Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw324249 C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)4250 Instruction Type: CVI_SCATTER_DV4251 Execution Slots: SLOT04252 ========================================================================== */4253 4254#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw)4255#endif /* __HEXAGON_ARCH___ >= 65 */4256 4257#if __HVX_ARCH__ >= 654258/* ==========================================================================4259 Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw324260 C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)4261 Instruction Type: CVI_SCATTER_DV4262 Execution Slots: SLOT04263 ========================================================================== */4264 4265#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw)4266#endif /* __HEXAGON_ARCH___ >= 65 */4267 4268#if __HVX_ARCH__ >= 654269/* ==========================================================================4270 Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw324271 C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4272 Instruction Type: CVI_SCATTER4273 Execution Slots: SLOT04274 ========================================================================== */4275 4276#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw)4277#endif /* __HEXAGON_ARCH___ >= 65 */4278 4279#if __HVX_ARCH__ >= 654280/* ==========================================================================4281 Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw324282 C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4283 Instruction Type: CVI_SCATTER4284 Execution Slots: SLOT04285 ========================================================================== */4286 4287#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw)4288#endif /* __HEXAGON_ARCH___ >= 65 */4289 4290#if __HVX_ARCH__ >= 654291/* ==========================================================================4292 Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw324293 C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)4294 Instruction Type: CVI_SCATTER4295 Execution Slots: SLOT04296 ========================================================================== */4297 4298#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw)4299#endif /* __HEXAGON_ARCH___ >= 65 */4300 4301#if __HVX_ARCH__ >= 664302/* ==========================================================================4303 Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat4304 C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs)4305 Instruction Type: CVI_VA4306 Execution Slots: SLOT01234307 ========================================================================== */4308 4309#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))4310#endif /* __HEXAGON_ARCH___ >= 66 */4311 4312#if __HVX_ARCH__ >= 664313/* ==========================================================================4314 Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w)4315 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)4316 Instruction Type: CVI_VP_VS4317 Execution Slots: SLOT01234318 ========================================================================== */4319 4320#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv)4321#endif /* __HEXAGON_ARCH___ >= 66 */4322 4323#if __HVX_ARCH__ >= 664324/* ==========================================================================4325 Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw)4326 C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)4327 Instruction Type: CVI_VS4328 Execution Slots: SLOT01234329 ========================================================================== */4330 4331#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv)4332#endif /* __HEXAGON_ARCH___ >= 66 */4333 4334#if __HVX_ARCH__ >= 664335/* ==========================================================================4336 Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w)4337 C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv)4338 Instruction Type: CVI_VA4339 Execution Slots: SLOT01234340 ========================================================================== */4341 4342#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv)4343#endif /* __HEXAGON_ARCH___ >= 66 */4344 4345#if __HVX_ARCH__ >= 684346/* ==========================================================================4347 Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h4348 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)4349 Instruction Type: CVI_VX_DV4350 Execution Slots: SLOT234351 ========================================================================== */4352 4353#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2)4354#endif /* __HEXAGON_ARCH___ >= 68 */4355 4356#if __HVX_ARCH__ >= 684357/* ==========================================================================4358 Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h4359 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)4360 Instruction Type: CVI_VX_DV4361 Execution Slots: SLOT234362 ========================================================================== */4363 4364#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2)4365#endif /* __HEXAGON_ARCH___ >= 68 */4366 4367#if __HVX_ARCH__ >= 684368/* ==========================================================================4369 Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v4370 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)4371 Instruction Type: CVI_VX_DV4372 Execution Slots: SLOT234373 ========================================================================== */4374 4375#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2)4376#endif /* __HEXAGON_ARCH___ >= 68 */4377 4378#if __HVX_ARCH__ >= 684379/* ==========================================================================4380 Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v4381 C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)4382 Instruction Type: CVI_VX_DV4383 Execution Slots: SLOT234384 ========================================================================== */4385 4386#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2)4387#endif /* __HEXAGON_ARCH___ >= 68 */4388 4389#if __HVX_ARCH__ >= 684390/* ==========================================================================4391 Assembly Syntax: Vd32.hf=vabs(Vu32.hf)4392 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu)4393 Instruction Type: CVI_VX_LATE4394 Execution Slots: SLOT234395 ========================================================================== */4396 4397#define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu)4398#endif /* __HEXAGON_ARCH___ >= 68 */4399 4400#if __HVX_ARCH__ >= 684401/* ==========================================================================4402 Assembly Syntax: Vd32.sf=vabs(Vu32.sf)4403 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu)4404 Instruction Type: CVI_VX_LATE4405 Execution Slots: SLOT234406 ========================================================================== */4407 4408#define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu)4409#endif /* __HEXAGON_ARCH___ >= 68 */4410 4411#if __HVX_ARCH__ >= 684412/* ==========================================================================4413 Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf)4414 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4415 Instruction Type: CVI_VS4416 Execution Slots: SLOT01234417 ========================================================================== */4418 4419#define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv)4420#endif /* __HEXAGON_ARCH___ >= 68 */4421 4422#if __HVX_ARCH__ >= 684423/* ==========================================================================4424 Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf)4425 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4426 Instruction Type: CVI_VX4427 Execution Slots: SLOT234428 ========================================================================== */4429 4430#define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv)4431#endif /* __HEXAGON_ARCH___ >= 68 */4432 4433#if __HVX_ARCH__ >= 684434/* ==========================================================================4435 Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)4436 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)4437 Instruction Type: CVI_VS4438 Execution Slots: SLOT01234439 ========================================================================== */4440 4441#define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv)4442#endif /* __HEXAGON_ARCH___ >= 68 */4443 4444#if __HVX_ARCH__ >= 684445/* ==========================================================================4446 Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)4447 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)4448 Instruction Type: CVI_VS4449 Execution Slots: SLOT01234450 ========================================================================== */4451 4452#define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv)4453#endif /* __HEXAGON_ARCH___ >= 68 */4454 4455#if __HVX_ARCH__ >= 684456/* ==========================================================================4457 Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)4458 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)4459 Instruction Type: CVI_VS4460 Execution Slots: SLOT01234461 ========================================================================== */4462 4463#define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv)4464#endif /* __HEXAGON_ARCH___ >= 68 */4465 4466#if __HVX_ARCH__ >= 684467/* ==========================================================================4468 Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)4469 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)4470 Instruction Type: CVI_VS4471 Execution Slots: SLOT01234472 ========================================================================== */4473 4474#define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv)4475#endif /* __HEXAGON_ARCH___ >= 68 */4476 4477#if __HVX_ARCH__ >= 684478/* ==========================================================================4479 Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf)4480 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4481 Instruction Type: CVI_VS4482 Execution Slots: SLOT01234483 ========================================================================== */4484 4485#define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv)4486#endif /* __HEXAGON_ARCH___ >= 68 */4487 4488#if __HVX_ARCH__ >= 684489/* ==========================================================================4490 Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf)4491 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4492 Instruction Type: CVI_VX_DV4493 Execution Slots: SLOT234494 ========================================================================== */4495 4496#define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv)4497#endif /* __HEXAGON_ARCH___ >= 68 */4498 4499#if __HVX_ARCH__ >= 684500/* ==========================================================================4501 Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf)4502 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4503 Instruction Type: CVI_VX4504 Execution Slots: SLOT234505 ========================================================================== */4506 4507#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv)4508#endif /* __HEXAGON_ARCH___ >= 68 */4509 4510#if __HVX_ARCH__ >= 684511/* ==========================================================================4512 Assembly Syntax: Vd32.w=vfmv(Vu32.w)4513 C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu)4514 Instruction Type: CVI_VX_LATE4515 Execution Slots: SLOT234516 ========================================================================== */4517 4518#define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu)4519#endif /* __HEXAGON_ARCH___ >= 68 */4520 4521#if __HVX_ARCH__ >= 684522/* ==========================================================================4523 Assembly Syntax: Vd32.hf=Vu32.qf164524 C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu)4525 Instruction Type: CVI_VS4526 Execution Slots: SLOT01234527 ========================================================================== */4528 4529#define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu)4530#endif /* __HEXAGON_ARCH___ >= 68 */4531 4532#if __HVX_ARCH__ >= 684533/* ==========================================================================4534 Assembly Syntax: Vd32.hf=Vuu32.qf324535 C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu)4536 Instruction Type: CVI_VS4537 Execution Slots: SLOT01234538 ========================================================================== */4539 4540#define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu)4541#endif /* __HEXAGON_ARCH___ >= 68 */4542 4543#if __HVX_ARCH__ >= 684544/* ==========================================================================4545 Assembly Syntax: Vd32.sf=Vu32.qf324546 C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu)4547 Instruction Type: CVI_VS4548 Execution Slots: SLOT01234549 ========================================================================== */4550 4551#define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu)4552#endif /* __HEXAGON_ARCH___ >= 68 */4553 4554#if __HVX_ARCH__ >= 684555/* ==========================================================================4556 Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf)4557 C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4558 Instruction Type: CVI_VX4559 Execution Slots: SLOT234560 ========================================================================== */4561 4562#define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv)4563#endif /* __HEXAGON_ARCH___ >= 68 */4564 4565#if __HVX_ARCH__ >= 684566/* ==========================================================================4567 Assembly Syntax: Vd32.h=vcvt(Vu32.hf)4568 C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu)4569 Instruction Type: CVI_VX4570 Execution Slots: SLOT234571 ========================================================================== */4572 4573#define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu)4574#endif /* __HEXAGON_ARCH___ >= 68 */4575 4576#if __HVX_ARCH__ >= 684577/* ==========================================================================4578 Assembly Syntax: Vdd32.hf=vcvt(Vu32.b)4579 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu)4580 Instruction Type: CVI_VX_DV4581 Execution Slots: SLOT234582 ========================================================================== */4583 4584#define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu)4585#endif /* __HEXAGON_ARCH___ >= 68 */4586 4587#if __HVX_ARCH__ >= 684588/* ==========================================================================4589 Assembly Syntax: Vd32.hf=vcvt(Vu32.h)4590 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu)4591 Instruction Type: CVI_VX4592 Execution Slots: SLOT234593 ========================================================================== */4594 4595#define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu)4596#endif /* __HEXAGON_ARCH___ >= 68 */4597 4598#if __HVX_ARCH__ >= 684599/* ==========================================================================4600 Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf)4601 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4602 Instruction Type: CVI_VX4603 Execution Slots: SLOT234604 ========================================================================== */4605 4606#define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv)4607#endif /* __HEXAGON_ARCH___ >= 68 */4608 4609#if __HVX_ARCH__ >= 684610/* ==========================================================================4611 Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub)4612 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu)4613 Instruction Type: CVI_VX_DV4614 Execution Slots: SLOT234615 ========================================================================== */4616 4617#define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu)4618#endif /* __HEXAGON_ARCH___ >= 68 */4619 4620#if __HVX_ARCH__ >= 684621/* ==========================================================================4622 Assembly Syntax: Vd32.hf=vcvt(Vu32.uh)4623 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu)4624 Instruction Type: CVI_VX4625 Execution Slots: SLOT234626 ========================================================================== */4627 4628#define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu)4629#endif /* __HEXAGON_ARCH___ >= 68 */4630 4631#if __HVX_ARCH__ >= 684632/* ==========================================================================4633 Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf)4634 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu)4635 Instruction Type: CVI_VX_DV4636 Execution Slots: SLOT234637 ========================================================================== */4638 4639#define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu)4640#endif /* __HEXAGON_ARCH___ >= 68 */4641 4642#if __HVX_ARCH__ >= 684643/* ==========================================================================4644 Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf)4645 C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4646 Instruction Type: CVI_VX4647 Execution Slots: SLOT234648 ========================================================================== */4649 4650#define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv)4651#endif /* __HEXAGON_ARCH___ >= 68 */4652 4653#if __HVX_ARCH__ >= 684654/* ==========================================================================4655 Assembly Syntax: Vd32.uh=vcvt(Vu32.hf)4656 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu)4657 Instruction Type: CVI_VX4658 Execution Slots: SLOT234659 ========================================================================== */4660 4661#define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu)4662#endif /* __HEXAGON_ARCH___ >= 68 */4663 4664#if __HVX_ARCH__ >= 684665/* ==========================================================================4666 Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)4667 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4668 Instruction Type: CVI_VX4669 Execution Slots: SLOT234670 ========================================================================== */4671 4672#define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv)4673#endif /* __HEXAGON_ARCH___ >= 68 */4674 4675#if __HVX_ARCH__ >= 684676/* ==========================================================================4677 Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)4678 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)4679 Instruction Type: CVI_VX4680 Execution Slots: SLOT234681 ========================================================================== */4682 4683#define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv)4684#endif /* __HEXAGON_ARCH___ >= 68 */4685 4686#if __HVX_ARCH__ >= 684687/* ==========================================================================4688 Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf)4689 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4690 Instruction Type: CVI_VX_LATE4691 Execution Slots: SLOT234692 ========================================================================== */4693 4694#define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv)4695#endif /* __HEXAGON_ARCH___ >= 68 */4696 4697#if __HVX_ARCH__ >= 684698/* ==========================================================================4699 Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf)4700 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4701 Instruction Type: CVI_VX_LATE4702 Execution Slots: SLOT234703 ========================================================================== */4704 4705#define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv)4706#endif /* __HEXAGON_ARCH___ >= 68 */4707 4708#if __HVX_ARCH__ >= 684709/* ==========================================================================4710 Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf)4711 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4712 Instruction Type: CVI_VX_LATE4713 Execution Slots: SLOT234714 ========================================================================== */4715 4716#define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv)4717#endif /* __HEXAGON_ARCH___ >= 68 */4718 4719#if __HVX_ARCH__ >= 684720/* ==========================================================================4721 Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf)4722 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4723 Instruction Type: CVI_VX_LATE4724 Execution Slots: SLOT234725 ========================================================================== */4726 4727#define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv)4728#endif /* __HEXAGON_ARCH___ >= 68 */4729 4730#if __HVX_ARCH__ >= 684731/* ==========================================================================4732 Assembly Syntax: Vd32.hf=vfneg(Vu32.hf)4733 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu)4734 Instruction Type: CVI_VX_LATE4735 Execution Slots: SLOT234736 ========================================================================== */4737 4738#define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu)4739#endif /* __HEXAGON_ARCH___ >= 68 */4740 4741#if __HVX_ARCH__ >= 684742/* ==========================================================================4743 Assembly Syntax: Vd32.sf=vfneg(Vu32.sf)4744 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu)4745 Instruction Type: CVI_VX_LATE4746 Execution Slots: SLOT234747 ========================================================================== */4748 4749#define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu)4750#endif /* __HEXAGON_ARCH___ >= 68 */4751 4752#if __HVX_ARCH__ >= 684753/* ==========================================================================4754 Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf)4755 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4756 Instruction Type: CVI_VA4757 Execution Slots: SLOT01234758 ========================================================================== */4759 4760#define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1)4761#endif /* __HEXAGON_ARCH___ >= 68 */4762 4763#if __HVX_ARCH__ >= 684764/* ==========================================================================4765 Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)4766 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4767 Instruction Type: CVI_VA4768 Execution Slots: SLOT01234769 ========================================================================== */4770 4771#define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4772#endif /* __HEXAGON_ARCH___ >= 68 */4773 4774#if __HVX_ARCH__ >= 684775/* ==========================================================================4776 Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)4777 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4778 Instruction Type: CVI_VA4779 Execution Slots: SLOT01234780 ========================================================================== */4781 4782#define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4783#endif /* __HEXAGON_ARCH___ >= 68 */4784 4785#if __HVX_ARCH__ >= 684786/* ==========================================================================4787 Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)4788 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4789 Instruction Type: CVI_VA4790 Execution Slots: SLOT01234791 ========================================================================== */4792 4793#define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4794#endif /* __HEXAGON_ARCH___ >= 68 */4795 4796#if __HVX_ARCH__ >= 684797/* ==========================================================================4798 Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf)4799 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4800 Instruction Type: CVI_VA4801 Execution Slots: SLOT01234802 ========================================================================== */4803 4804#define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1)4805#endif /* __HEXAGON_ARCH___ >= 68 */4806 4807#if __HVX_ARCH__ >= 684808/* ==========================================================================4809 Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)4810 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4811 Instruction Type: CVI_VA4812 Execution Slots: SLOT01234813 ========================================================================== */4814 4815#define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4816#endif /* __HEXAGON_ARCH___ >= 68 */4817 4818#if __HVX_ARCH__ >= 684819/* ==========================================================================4820 Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)4821 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4822 Instruction Type: CVI_VA4823 Execution Slots: SLOT01234824 ========================================================================== */4825 4826#define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4827#endif /* __HEXAGON_ARCH___ >= 68 */4828 4829#if __HVX_ARCH__ >= 684830/* ==========================================================================4831 Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)4832 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)4833 Instruction Type: CVI_VA4834 Execution Slots: SLOT01234835 ========================================================================== */4836 4837#define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1)4838#endif /* __HEXAGON_ARCH___ >= 68 */4839 4840#if __HVX_ARCH__ >= 684841/* ==========================================================================4842 Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf)4843 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4844 Instruction Type: CVI_VA4845 Execution Slots: SLOT01234846 ========================================================================== */4847 4848#define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv)4849#endif /* __HEXAGON_ARCH___ >= 68 */4850 4851#if __HVX_ARCH__ >= 684852/* ==========================================================================4853 Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf)4854 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4855 Instruction Type: CVI_VA4856 Execution Slots: SLOT01234857 ========================================================================== */4858 4859#define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv)4860#endif /* __HEXAGON_ARCH___ >= 68 */4861 4862#if __HVX_ARCH__ >= 684863/* ==========================================================================4864 Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf)4865 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4866 Instruction Type: CVI_VA4867 Execution Slots: SLOT01234868 ========================================================================== */4869 4870#define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv)4871#endif /* __HEXAGON_ARCH___ >= 68 */4872 4873#if __HVX_ARCH__ >= 684874/* ==========================================================================4875 Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf)4876 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4877 Instruction Type: CVI_VA4878 Execution Slots: SLOT01234879 ========================================================================== */4880 4881#define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv)4882#endif /* __HEXAGON_ARCH___ >= 68 */4883 4884#if __HVX_ARCH__ >= 684885/* ==========================================================================4886 Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf)4887 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4888 Instruction Type: CVI_VX4889 Execution Slots: SLOT234890 ========================================================================== */4891 4892#define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv)4893#endif /* __HEXAGON_ARCH___ >= 68 */4894 4895#if __HVX_ARCH__ >= 684896/* ==========================================================================4897 Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)4898 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)4899 Instruction Type: CVI_VX4900 Execution Slots: SLOT234901 ========================================================================== */4902 4903#define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv)4904#endif /* __HEXAGON_ARCH___ >= 68 */4905 4906#if __HVX_ARCH__ >= 684907/* ==========================================================================4908 Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)4909 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)4910 Instruction Type: CVI_VX_DV4911 Execution Slots: SLOT234912 ========================================================================== */4913 4914#define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv)4915#endif /* __HEXAGON_ARCH___ >= 68 */4916 4917#if __HVX_ARCH__ >= 684918/* ==========================================================================4919 Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)4920 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4921 Instruction Type: CVI_VX_DV4922 Execution Slots: SLOT234923 ========================================================================== */4924 4925#define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv)4926#endif /* __HEXAGON_ARCH___ >= 68 */4927 4928#if __HVX_ARCH__ >= 684929/* ==========================================================================4930 Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)4931 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)4932 Instruction Type: CVI_VX_DV4933 Execution Slots: SLOT234934 ========================================================================== */4935 4936#define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv)4937#endif /* __HEXAGON_ARCH___ >= 68 */4938 4939#if __HVX_ARCH__ >= 684940/* ==========================================================================4941 Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)4942 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)4943 Instruction Type: CVI_VX_DV4944 Execution Slots: SLOT234945 ========================================================================== */4946 4947#define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv)4948#endif /* __HEXAGON_ARCH___ >= 68 */4949 4950#if __HVX_ARCH__ >= 684951/* ==========================================================================4952 Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)4953 C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4954 Instruction Type: CVI_VX_DV4955 Execution Slots: SLOT234956 ========================================================================== */4957 4958#define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv)4959#endif /* __HEXAGON_ARCH___ >= 68 */4960 4961#if __HVX_ARCH__ >= 684962/* ==========================================================================4963 Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)4964 C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)4965 Instruction Type: CVI_VX_DV4966 Execution Slots: SLOT234967 ========================================================================== */4968 4969#define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv)4970#endif /* __HEXAGON_ARCH___ >= 68 */4971 4972#if __HVX_ARCH__ >= 684973/* ==========================================================================4974 Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)4975 C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)4976 Instruction Type: CVI_VX_DV4977 Execution Slots: SLOT234978 ========================================================================== */4979 4980#define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv)4981#endif /* __HEXAGON_ARCH___ >= 68 */4982 4983#if __HVX_ARCH__ >= 684984/* ==========================================================================4985 Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)4986 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)4987 Instruction Type: CVI_VX_DV4988 Execution Slots: SLOT234989 ========================================================================== */4990 4991#define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv)4992#endif /* __HEXAGON_ARCH___ >= 68 */4993 4994#if __HVX_ARCH__ >= 684995/* ==========================================================================4996 Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)4997 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)4998 Instruction Type: CVI_VX_DV4999 Execution Slots: SLOT235000 ========================================================================== */5001 5002#define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv)5003#endif /* __HEXAGON_ARCH___ >= 68 */5004 5005#if __HVX_ARCH__ >= 685006/* ==========================================================================5007 Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)5008 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)5009 Instruction Type: CVI_VX_DV5010 Execution Slots: SLOT235011 ========================================================================== */5012 5013#define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv)5014#endif /* __HEXAGON_ARCH___ >= 68 */5015 5016#if __HVX_ARCH__ >= 685017/* ==========================================================================5018 Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf)5019 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)5020 Instruction Type: CVI_VX_DV5021 Execution Slots: SLOT235022 ========================================================================== */5023 5024#define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv)5025#endif /* __HEXAGON_ARCH___ >= 68 */5026 5027#if __HVX_ARCH__ >= 685028/* ==========================================================================5029 Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf)5030 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)5031 Instruction Type: CVI_VS5032 Execution Slots: SLOT01235033 ========================================================================== */5034 5035#define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv)5036#endif /* __HEXAGON_ARCH___ >= 68 */5037 5038#if __HVX_ARCH__ >= 685039/* ==========================================================================5040 Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf)5041 C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)5042 Instruction Type: CVI_VX5043 Execution Slots: SLOT235044 ========================================================================== */5045 5046#define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv)5047#endif /* __HEXAGON_ARCH___ >= 68 */5048 5049#if __HVX_ARCH__ >= 685050/* ==========================================================================5051 Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)5052 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv)5053 Instruction Type: CVI_VS5054 Execution Slots: SLOT01235055 ========================================================================== */5056 5057#define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv)5058#endif /* __HEXAGON_ARCH___ >= 68 */5059 5060#if __HVX_ARCH__ >= 685061/* ==========================================================================5062 Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)5063 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv)5064 Instruction Type: CVI_VS5065 Execution Slots: SLOT01235066 ========================================================================== */5067 5068#define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv)5069#endif /* __HEXAGON_ARCH___ >= 68 */5070 5071#if __HVX_ARCH__ >= 685072/* ==========================================================================5073 Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)5074 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv)5075 Instruction Type: CVI_VS5076 Execution Slots: SLOT01235077 ========================================================================== */5078 5079#define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv)5080#endif /* __HEXAGON_ARCH___ >= 68 */5081 5082#if __HVX_ARCH__ >= 685083/* ==========================================================================5084 Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)5085 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv)5086 Instruction Type: CVI_VS5087 Execution Slots: SLOT01235088 ========================================================================== */5089 5090#define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv)5091#endif /* __HEXAGON_ARCH___ >= 68 */5092 5093#if __HVX_ARCH__ >= 685094/* ==========================================================================5095 Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf)5096 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)5097 Instruction Type: CVI_VS5098 Execution Slots: SLOT01235099 ========================================================================== */5100 5101#define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv)5102#endif /* __HEXAGON_ARCH___ >= 68 */5103 5104#if __HVX_ARCH__ >= 685105/* ==========================================================================5106 Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf)5107 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv)5108 Instruction Type: CVI_VX_DV5109 Execution Slots: SLOT235110 ========================================================================== */5111 5112#define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv)5113#endif /* __HEXAGON_ARCH___ >= 68 */5114 5115#if __HVX_ARCH__ >= 685116/* ==========================================================================5117 Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf)5118 C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv)5119 Instruction Type: CVI_VX5120 Execution Slots: SLOT235121 ========================================================================== */5122 5123#define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv)5124#endif /* __HEXAGON_ARCH___ >= 68 */5125 5126#if __HVX_ARCH__ >= 695127/* ==========================================================================5128 Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat5129 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)5130 Instruction Type: CVI_VS5131 Execution Slots: SLOT01235132 ========================================================================== */5133 5134#define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv)5135#endif /* __HEXAGON_ARCH___ >= 69 */5136 5137#if __HVX_ARCH__ >= 695138/* ==========================================================================5139 Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat5140 C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv)5141 Instruction Type: CVI_VS5142 Execution Slots: SLOT01235143 ========================================================================== */5144 5145#define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv)5146#endif /* __HEXAGON_ARCH___ >= 69 */5147 5148#if __HVX_ARCH__ >= 695149/* ==========================================================================5150 Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat5151 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv)5152 Instruction Type: CVI_VS5153 Execution Slots: SLOT01235154 ========================================================================== */5155 5156#define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv)5157#endif /* __HEXAGON_ARCH___ >= 69 */5158 5159#if __HVX_ARCH__ >= 695160/* ==========================================================================5161 Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat5162 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv)5163 Instruction Type: CVI_VS5164 Execution Slots: SLOT01235165 ========================================================================== */5166 5167#define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv)5168#endif /* __HEXAGON_ARCH___ >= 69 */5169 5170#if __HVX_ARCH__ >= 695171/* ==========================================================================5172 Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>165173 C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv)5174 Instruction Type: CVI_VX5175 Execution Slots: SLOT235176 ========================================================================== */5177 5178#define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv)5179#endif /* __HEXAGON_ARCH___ >= 69 */5180 5181#if __HVX_ARCH__ >= 735182/* ==========================================================================5183 Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf)5184 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu,5185 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235186 ========================================================================== */5187 5188#define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \5189 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv)5190#endif /* __HEXAGON_ARCH___ >= 73 */5191 5192#if __HVX_ARCH__ >= 735193/* ==========================================================================5194 Assembly Syntax: Vd32.h=Vu32.hf5195 C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu)5196 Instruction Type: CVI_VS5197 Execution Slots: SLOT01235198 ========================================================================== */5199 5200#define Q6_Vh_equals_Vhf(Vu) \5201 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu)5202#endif /* __HEXAGON_ARCH___ >= 73 */5203 5204#if __HVX_ARCH__ >= 735205/* ==========================================================================5206 Assembly Syntax: Vd32.hf=Vu32.h5207 C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu)5208 Instruction Type: CVI_VS5209 Execution Slots: SLOT01235210 ========================================================================== */5211 5212#define Q6_Vhf_equals_Vh(Vu) \5213 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu)5214#endif /* __HEXAGON_ARCH___ >= 73 */5215 5216#if __HVX_ARCH__ >= 735217/* ==========================================================================5218 Assembly Syntax: Vd32.sf=Vu32.w5219 C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu)5220 Instruction Type: CVI_VS5221 Execution Slots: SLOT01235222 ========================================================================== */5223 5224#define Q6_Vsf_equals_Vw(Vu) \5225 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu)5226#endif /* __HEXAGON_ARCH___ >= 73 */5227 5228#if __HVX_ARCH__ >= 735229/* ==========================================================================5230 Assembly Syntax: Vd32.w=Vu32.sf5231 C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu)5232 Instruction Type: CVI_VS5233 Execution Slots: SLOT01235234 ========================================================================== */5235 5236#define Q6_Vw_equals_Vsf(Vu) \5237 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu)5238#endif /* __HEXAGON_ARCH___ >= 73 */5239 5240#if __HVX_ARCH__ >= 735241/* ==========================================================================5242 Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf)5243 C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu,5244 HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT235245 ========================================================================== */5246 5247#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \5248 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv)5249#endif /* __HEXAGON_ARCH___ >= 73 */5250 5251#if __HVX_ARCH__ >= 735252/* ==========================================================================5253 Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf)5254 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu,5255 HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT01235256 ========================================================================== */5257 5258#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \5259 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \5260 ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1)5261#endif /* __HEXAGON_ARCH___ >= 73 */5262 5263#if __HVX_ARCH__ >= 735264/* ==========================================================================5265 Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf)5266 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred5267 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5268 Slots: SLOT01235269 ========================================================================== */5270 5271#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \5272 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \5273 ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)( \5274 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5275 Vv)), \5276 -1)5277#endif /* __HEXAGON_ARCH___ >= 73 */5278 5279#if __HVX_ARCH__ >= 735280/* ==========================================================================5281 Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf)5282 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred5283 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5284 Slots: SLOT01235285 ========================================================================== */5286 5287#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \5288 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \5289 ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)( \5290 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5291 Vv)), \5292 -1)5293#endif /* __HEXAGON_ARCH___ >= 73 */5294 5295#if __HVX_ARCH__ >= 735296/* ==========================================================================5297 Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf)5298 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred5299 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5300 Slots: SLOT01235301 ========================================================================== */5302 5303#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \5304 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \5305 ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)( \5306 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5307 Vv)), \5308 -1)5309#endif /* __HEXAGON_ARCH___ >= 73 */5310 5311#if __HVX_ARCH__ >= 735312/* ==========================================================================5313 Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf)5314 C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu,5315 HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT235316 ========================================================================== */5317 5318#define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \5319 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv)5320#endif /* __HEXAGON_ARCH___ >= 73 */5321 5322#if __HVX_ARCH__ >= 735323/* ==========================================================================5324 Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf)5325 C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu,5326 HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT235327 ========================================================================== */5328 5329#define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \5330 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv)5331#endif /* __HEXAGON_ARCH___ >= 73 */5332 5333#if __HVX_ARCH__ >= 735334/* ==========================================================================5335 Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)5336 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu,5337 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235338 ========================================================================== */5339 5340#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \5341 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv)5342#endif /* __HEXAGON_ARCH___ >= 73 */5343 5344#if __HVX_ARCH__ >= 735345/* ==========================================================================5346 Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)5347 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair5348 Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution5349 Slots: SLOT235350 ========================================================================== */5351 5352#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \5353 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv)5354#endif /* __HEXAGON_ARCH___ >= 73 */5355 5356#if __HVX_ARCH__ >= 735357/* ==========================================================================5358 Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf)5359 C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu,5360 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235361 ========================================================================== */5362 5363#define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \5364 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv)5365#endif /* __HEXAGON_ARCH___ >= 73 */5366 5367#if __HVX_ARCH__ >= 795368/* ==========================================================================5369 Assembly Syntax: Vd32=vgetqfext(Vu32.x,Rt32)5370 C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt)5371 Instruction Type: CVI_VX5372 Execution Slots: SLOT235373 ========================================================================== */5374 5375#define Q6_V_vgetqfext_VR(Vu, Rt) \5376 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt)5377#endif /* __HEXAGON_ARCH___ >= 79 */5378 5379#if __HVX_ARCH__ >= 795380/* ==========================================================================5381 Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32)5382 C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx,5383 HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots:5384 SLOT235385 ========================================================================== */5386 5387#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \5388 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt)5389#endif /* __HEXAGON_ARCH___ >= 79 */5390 5391#if __HVX_ARCH__ >= 795392/* ==========================================================================5393 Assembly Syntax: Vd32.x=vsetqfext(Vu32,Rt32)5394 C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt)5395 Instruction Type: CVI_VX5396 Execution Slots: SLOT235397 ========================================================================== */5398 5399#define Q6_V_vsetqfext_VR(Vu, Rt) \5400 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt)5401#endif /* __HEXAGON_ARCH___ >= 79 */5402 5403#if __HVX_ARCH__ >= 795404/* ==========================================================================5405 Assembly Syntax: Vd32.f8=vabs(Vu32.f8)5406 C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu)5407 Instruction Type: CVI_VX_LATE5408 Execution Slots: SLOT235409 ========================================================================== */5410 5411#define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu)5412#endif /* __HEXAGON_ARCH___ >= 79 */5413 5414#if __HVX_ARCH__ >= 795415/* ==========================================================================5416 Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8)5417 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu,5418 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235419 ========================================================================== */5420 5421#define Q6_Whf_vadd_VV(Vu, Vv) \5422 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv)5423#endif /* __HEXAGON_ARCH___ >= 79 */5424 5425#if __HVX_ARCH__ >= 795426/* ==========================================================================5427 Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf)5428 C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu,5429 HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT235430 ========================================================================== */5431 5432#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \5433 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv)5434#endif /* __HEXAGON_ARCH___ >= 79 */5435 5436#if __HVX_ARCH__ >= 795437/* ==========================================================================5438 Assembly Syntax: Vdd32.hf=vcvt2(Vu32.b)5439 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu)5440 Instruction Type: CVI_VX_DV5441 Execution Slots: SLOT235442 ========================================================================== */5443 5444#define Q6_Whf_vcvt2_Vb(Vu) \5445 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu)5446#endif /* __HEXAGON_ARCH___ >= 79 */5447 5448#if __HVX_ARCH__ >= 795449/* ==========================================================================5450 Assembly Syntax: Vdd32.hf=vcvt2(Vu32.ub)5451 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu)5452 Instruction Type: CVI_VX_DV5453 Execution Slots: SLOT235454 ========================================================================== */5455 5456#define Q6_Whf_vcvt2_Vub(Vu) \5457 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu)5458#endif /* __HEXAGON_ARCH___ >= 79 */5459 5460#if __HVX_ARCH__ >= 795461/* ==========================================================================5462 Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf)5463 C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu,5464 HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT235465 ========================================================================== */5466 5467#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \5468 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv)5469#endif /* __HEXAGON_ARCH___ >= 79 */5470 5471#if __HVX_ARCH__ >= 795472/* ==========================================================================5473 Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf)5474 C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector5475 Vv) Instruction Type: CVI_VX Execution Slots: SLOT235476 ========================================================================== */5477 5478#define Q6_V_vcvt_VhfVhf(Vu, Vv) \5479 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv)5480#endif /* __HEXAGON_ARCH___ >= 79 */5481 5482#if __HVX_ARCH__ >= 795483/* ==========================================================================5484 Assembly Syntax: Vdd32.hf=vcvt(Vu32.f8)5485 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu)5486 Instruction Type: CVI_VX_DV5487 Execution Slots: SLOT235488 ========================================================================== */5489 5490#define Q6_Whf_vcvt_V(Vu) \5491 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu)5492#endif /* __HEXAGON_ARCH___ >= 79 */5493 5494#if __HVX_ARCH__ >= 795495/* ==========================================================================5496 Assembly Syntax: Vd32.f8=vfmax(Vu32.f8,Vv32.f8)5497 C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv)5498 Instruction Type: CVI_VX_LATE5499 Execution Slots: SLOT235500 ========================================================================== */5501 5502#define Q6_V_vfmax_VV(Vu, Vv) \5503 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv)5504#endif /* __HEXAGON_ARCH___ >= 79 */5505 5506#if __HVX_ARCH__ >= 795507/* ==========================================================================5508 Assembly Syntax: Vd32.f8=vfmin(Vu32.f8,Vv32.f8)5509 C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv)5510 Instruction Type: CVI_VX_LATE5511 Execution Slots: SLOT235512 ========================================================================== */5513 5514#define Q6_V_vfmin_VV(Vu, Vv) \5515 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv)5516#endif /* __HEXAGON_ARCH___ >= 79 */5517 5518#if __HVX_ARCH__ >= 795519/* ==========================================================================5520 Assembly Syntax: Vd32.f8=vfneg(Vu32.f8)5521 C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu)5522 Instruction Type: CVI_VX_LATE5523 Execution Slots: SLOT235524 ========================================================================== */5525 5526#define Q6_V_vfneg_V(Vu) \5527 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu)5528#endif /* __HEXAGON_ARCH___ >= 79 */5529 5530#if __HVX_ARCH__ >= 795531/* ==========================================================================5532 Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w)5533 C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector5534 Vv) Instruction Type: CVI_VS Execution Slots: SLOT01235535 ========================================================================== */5536 5537#define Q6_V_vmerge_VVw(Vu, Vv) \5538 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv)5539#endif /* __HEXAGON_ARCH___ >= 79 */5540 5541#if __HVX_ARCH__ >= 795542/* ==========================================================================5543 Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8)5544 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu,5545 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235546 ========================================================================== */5547 5548#define Q6_Whf_vmpy_VV(Vu, Vv) \5549 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv)5550#endif /* __HEXAGON_ARCH___ >= 79 */5551 5552#if __HVX_ARCH__ >= 795553/* ==========================================================================5554 Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8)5555 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair5556 Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution5557 Slots: SLOT235558 ========================================================================== */5559 5560#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \5561 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv)5562#endif /* __HEXAGON_ARCH___ >= 79 */5563 5564#if __HVX_ARCH__ >= 795565/* ==========================================================================5566 Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf)5567 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word325568 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT235569 ========================================================================== */5570 5571#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \5572 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt)5573#endif /* __HEXAGON_ARCH___ >= 79 */5574 5575#if __HVX_ARCH__ >= 795576/* ==========================================================================5577 Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf)5578 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu,5579 Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT235580 ========================================================================== */5581 5582#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \5583 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt)5584#endif /* __HEXAGON_ARCH___ >= 79 */5585 5586#if __HVX_ARCH__ >= 795587/* ==========================================================================5588 Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf)5589 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word325590 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT235591 ========================================================================== */5592 5593#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \5594 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt)5595#endif /* __HEXAGON_ARCH___ >= 79 */5596 5597#if __HVX_ARCH__ >= 795598/* ==========================================================================5599 Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8)5600 C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu,5601 HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT235602 ========================================================================== */5603 5604#define Q6_Whf_vsub_VV(Vu, Vv) \5605 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv)5606#endif /* __HEXAGON_ARCH___ >= 79 */5607 5608#if __HVX_ARCH__ >= 815609/* ==========================================================================5610 Assembly Syntax: Vd32.qf16=vabs(Vu32.hf)5611 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu)5612 Instruction Type: CVI_VS5613 Execution Slots: SLOT01235614 ========================================================================== */5615 5616#define Q6_Vqf16_vabs_Vhf(Vu) \5617 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)5618#endif /* __HEXAGON_ARCH___ >= 81 */5619 5620#if __HVX_ARCH__ >= 815621/* ==========================================================================5622 Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16)5623 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu)5624 Instruction Type: CVI_VS5625 Execution Slots: SLOT01235626 ========================================================================== */5627 5628#define Q6_Vqf16_vabs_Vqf16(Vu) \5629 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)5630#endif /* __HEXAGON_ARCH___ >= 81 */5631 5632#if __HVX_ARCH__ >= 815633/* ==========================================================================5634 Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32)5635 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu)5636 Instruction Type: CVI_VS5637 Execution Slots: SLOT01235638 ========================================================================== */5639 5640#define Q6_Vqf32_vabs_Vqf32(Vu) \5641 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)5642#endif /* __HEXAGON_ARCH___ >= 81 */5643 5644#if __HVX_ARCH__ >= 815645/* ==========================================================================5646 Assembly Syntax: Vd32.qf32=vabs(Vu32.sf)5647 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu)5648 Instruction Type: CVI_VS5649 Execution Slots: SLOT01235650 ========================================================================== */5651 5652#define Q6_Vqf32_vabs_Vsf(Vu) \5653 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)5654#endif /* __HEXAGON_ARCH___ >= 81 */5655 5656#if __HVX_ARCH__ >= 815657/* ==========================================================================5658 Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)5659 C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector5660 Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT01235661 ========================================================================== */5662 5663#define Q6_V_valign4_VVR(Vu, Vv, Rt) \5664 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt)5665#endif /* __HEXAGON_ARCH___ >= 81 */5666 5667#if __HVX_ARCH__ >= 815668/* ==========================================================================5669 Assembly Syntax: Vd32.bf=Vuu32.qf325670 C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu)5671 Instruction Type: CVI_VS5672 Execution Slots: SLOT01235673 ========================================================================== */5674 5675#define Q6_Vbf_equals_Wqf32(Vuu) \5676 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)5677#endif /* __HEXAGON_ARCH___ >= 81 */5678 5679#if __HVX_ARCH__ >= 815680/* ==========================================================================5681 Assembly Syntax: Vd32.f8=Vu32.qf165682 C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu)5683 Instruction Type: CVI_VS5684 Execution Slots: SLOT01235685 ========================================================================== */5686 5687#define Q6_V_equals_Vqf16(Vu) \5688 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)5689#endif /* __HEXAGON_ARCH___ >= 81 */5690 5691#if __HVX_ARCH__ >= 815692/* ==========================================================================5693 Assembly Syntax: Vd32.h=Vu32.hf:rnd5694 C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu)5695 Instruction Type: CVI_VS5696 Execution Slots: SLOT01235697 ========================================================================== */5698 5699#define Q6_Vh_equals_Vhf_rnd(Vu) \5700 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)5701#endif /* __HEXAGON_ARCH___ >= 81 */5702 5703#if __HVX_ARCH__ >= 815704/* ==========================================================================5705 Assembly Syntax: Vdd32.qf16=Vu32.f85706 C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu)5707 Instruction Type: CVI_VP_VS5708 Execution Slots: SLOT01235709 ========================================================================== */5710 5711#define Q6_Wqf16_equals_V(Vu) \5712 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)5713#endif /* __HEXAGON_ARCH___ >= 81 */5714 5715#if __HVX_ARCH__ >= 815716/* ==========================================================================5717 Assembly Syntax: Vd32.qf16=Vu32.hf5718 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu)5719 Instruction Type: CVI_VS5720 Execution Slots: SLOT01235721 ========================================================================== */5722 5723#define Q6_Vqf16_equals_Vhf(Vu) \5724 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)5725#endif /* __HEXAGON_ARCH___ >= 81 */5726 5727#if __HVX_ARCH__ >= 815728/* ==========================================================================5729 Assembly Syntax: Vd32.qf16=Vu32.qf165730 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu)5731 Instruction Type: CVI_VS5732 Execution Slots: SLOT01235733 ========================================================================== */5734 5735#define Q6_Vqf16_equals_Vqf16(Vu) \5736 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)5737#endif /* __HEXAGON_ARCH___ >= 81 */5738 5739#if __HVX_ARCH__ >= 815740/* ==========================================================================5741 Assembly Syntax: Vd32.qf32=Vu32.qf325742 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu)5743 Instruction Type: CVI_VS5744 Execution Slots: SLOT01235745 ========================================================================== */5746 5747#define Q6_Vqf32_equals_Vqf32(Vu) \5748 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)5749#endif /* __HEXAGON_ARCH___ >= 81 */5750 5751#if __HVX_ARCH__ >= 815752/* ==========================================================================5753 Assembly Syntax: Vd32.qf32=Vu32.sf5754 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu)5755 Instruction Type: CVI_VS5756 Execution Slots: SLOT01235757 ========================================================================== */5758 5759#define Q6_Vqf32_equals_Vsf(Vu) \5760 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)5761#endif /* __HEXAGON_ARCH___ >= 81 */5762 5763#if __HVX_ARCH__ >= 815764/* ==========================================================================5765 Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)5766 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,5767 HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT01235768 ========================================================================== */5769 5770#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \5771 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5772 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1)5773#endif /* __HEXAGON_ARCH___ >= 81 */5774 5775#if __HVX_ARCH__ >= 815776/* ==========================================================================5777 Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)5778 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred5779 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5780 Slots: SLOT01235781 ========================================================================== */5782 5783#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \5784 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5785 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \5786 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5787 Vv)), \5788 -1)5789#endif /* __HEXAGON_ARCH___ >= 81 */5790 5791#if __HVX_ARCH__ >= 815792/* ==========================================================================5793 Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)5794 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred5795 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5796 Slots: SLOT01235797 ========================================================================== */5798 5799#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \5800 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5801 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \5802 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5803 Vv)), \5804 -1)5805#endif /* __HEXAGON_ARCH___ >= 81 */5806 5807#if __HVX_ARCH__ >= 815808/* ==========================================================================5809 Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)5810 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred5811 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5812 Slots: SLOT01235813 ========================================================================== */5814 5815#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \5816 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5817 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \5818 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5819 Vv)), \5820 -1)5821#endif /* __HEXAGON_ARCH___ >= 81 */5822 5823#if __HVX_ARCH__ >= 815824/* ==========================================================================5825 Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)5826 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,5827 HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT01235828 ========================================================================== */5829 5830#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \5831 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5832 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1)5833#endif /* __HEXAGON_ARCH___ >= 81 */5834 5835#if __HVX_ARCH__ >= 815836/* ==========================================================================5837 Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)5838 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred5839 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5840 Slots: SLOT01235841 ========================================================================== */5842 5843#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \5844 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5845 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \5846 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5847 Vv)), \5848 -1)5849#endif /* __HEXAGON_ARCH___ >= 81 */5850 5851#if __HVX_ARCH__ >= 815852/* ==========================================================================5853 Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)5854 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred5855 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5856 Slots: SLOT01235857 ========================================================================== */5858 5859#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \5860 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5861 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \5862 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5863 Vv)), \5864 -1)5865#endif /* __HEXAGON_ARCH___ >= 81 */5866 5867#if __HVX_ARCH__ >= 815868/* ==========================================================================5869 Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)5870 C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred5871 Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution5872 Slots: SLOT01235873 ========================================================================== */5874 5875#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \5876 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \5877 (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \5878 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \5879 Vv)), \5880 -1)5881#endif /* __HEXAGON_ARCH___ >= 81 */5882 5883#if __HVX_ARCH__ >= 815884/* ==========================================================================5885 Assembly Syntax: Vd32.w=vilog2(Vu32.hf)5886 C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu)5887 Instruction Type: CVI_VS5888 Execution Slots: SLOT01235889 ========================================================================== */5890 5891#define Q6_Vw_vilog2_Vhf(Vu) \5892 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)5893#endif /* __HEXAGON_ARCH___ >= 81 */5894 5895#if __HVX_ARCH__ >= 815896/* ==========================================================================5897 Assembly Syntax: Vd32.w=vilog2(Vu32.qf16)5898 C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu)5899 Instruction Type: CVI_VS5900 Execution Slots: SLOT01235901 ========================================================================== */5902 5903#define Q6_Vw_vilog2_Vqf16(Vu) \5904 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)5905#endif /* __HEXAGON_ARCH___ >= 81 */5906 5907#if __HVX_ARCH__ >= 815908/* ==========================================================================5909 Assembly Syntax: Vd32.w=vilog2(Vu32.qf32)5910 C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu)5911 Instruction Type: CVI_VS5912 Execution Slots: SLOT01235913 ========================================================================== */5914 5915#define Q6_Vw_vilog2_Vqf32(Vu) \5916 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)5917#endif /* __HEXAGON_ARCH___ >= 81 */5918 5919#if __HVX_ARCH__ >= 815920/* ==========================================================================5921 Assembly Syntax: Vd32.w=vilog2(Vu32.sf)5922 C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu)5923 Instruction Type: CVI_VS5924 Execution Slots: SLOT01235925 ========================================================================== */5926 5927#define Q6_Vw_vilog2_Vsf(Vu) \5928 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)5929#endif /* __HEXAGON_ARCH___ >= 81 */5930 5931#if __HVX_ARCH__ >= 815932/* ==========================================================================5933 Assembly Syntax: Vd32.qf16=vneg(Vu32.hf)5934 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu)5935 Instruction Type: CVI_VS5936 Execution Slots: SLOT01235937 ========================================================================== */5938 5939#define Q6_Vqf16_vneg_Vhf(Vu) \5940 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)5941#endif /* __HEXAGON_ARCH___ >= 81 */5942 5943#if __HVX_ARCH__ >= 815944/* ==========================================================================5945 Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16)5946 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu)5947 Instruction Type: CVI_VS5948 Execution Slots: SLOT01235949 ========================================================================== */5950 5951#define Q6_Vqf16_vneg_Vqf16(Vu) \5952 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)5953#endif /* __HEXAGON_ARCH___ >= 81 */5954 5955#if __HVX_ARCH__ >= 815956/* ==========================================================================5957 Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32)5958 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu)5959 Instruction Type: CVI_VS5960 Execution Slots: SLOT01235961 ========================================================================== */5962 5963#define Q6_Vqf32_vneg_Vqf32(Vu) \5964 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)5965#endif /* __HEXAGON_ARCH___ >= 81 */5966 5967#if __HVX_ARCH__ >= 815968/* ==========================================================================5969 Assembly Syntax: Vd32.qf32=vneg(Vu32.sf)5970 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu)5971 Instruction Type: CVI_VS5972 Execution Slots: SLOT01235973 ========================================================================== */5974 5975#define Q6_Vqf32_vneg_Vsf(Vu) \5976 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)5977#endif /* __HEXAGON_ARCH___ >= 81 */5978 5979#if __HVX_ARCH__ >= 815980/* ==========================================================================5981 Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)5982 C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,5983 HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT01235984 ========================================================================== */5985 5986#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \5987 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv)5988#endif /* __HEXAGON_ARCH___ >= 81 */5989 5990#if __HVX_ARCH__ >= 815991/* ==========================================================================5992 Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)5993 C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,5994 HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT01235995 ========================================================================== */5996 5997#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \5998 __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv)5999#endif /* __HEXAGON_ARCH___ >= 81 */6000 6001#endif /* __HVX__ */6002 6003#endif6004